Intel MFSYS25V2, MFSYS35, Compute Module MFS5000SI Specification
Intel® Compute Module MFS5000SI
Technical Product Specification
Intel order number: E15154-007
Revision 1.4
June 2009
Enterprise Platforms and Services Division
Revision History Intel® Compute Module MFS5000SI TPS
Revision History
Date Revision
Number
July 2007 0.95 Initial release.
August 2007 0.96 Updated
September 2007 1.0 Updated
February 2008 1.1 Updated
November 2008 1.2 Updated
May 2009 1.3 Updated
June 2009 1.4 Updated supported memory configurations
Modifications
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express or
implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except
as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel
products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for
use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and
product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility
whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The Intel
cause the product to deviate from published specifications. Current characterized errata are available on
request.
Intel Corporation server baseboards support peripheral components and contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are
designed and tested to meet the intended thermal requirements of these components when the fully
integrated system is used together. It is the responsibility of the system integrator that chooses not to use
Intel developed server building blocks to consult vendor datasheets and operating parameters to
determine the amount of air flow required for their specific application and environmental conditions. Intel
Corporation can not be held responsible if components fail or the compute module does not operate
correctly when used outside any of their published operating or non-operating limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2007-2009.
Compute Module MFS5000SI may contain design defects or errors known as errata which may
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Intel® Compute Module MFS5000SI TPS Table of Contents
Table of Contents
1. Introduction.............................................................................................................................1
1.1 Chapter Outline........................................................................................................ 1
1.2 Intel® Compute Module Use Disclaimer................................................................... 1
2. Product Overview....................................................................................................................2
2.1 Intel® Compute Module MFS5000SI Feature Set .................................................... 2
2.2 Compute Module Layout.......................................................................................... 3
2.2.1 Connector and Component Locations ..................................................................... 3
2.2.2 External I/O Connector Locations............................................................................ 4
2.2.3 Compute Module Mechanical Drawings .................................................................. 5
3. Functional Architecture ...........................................................................................................6
3.1 Intel® 5000P Memory Controller Hub (MCH) ........................................................... 7
3.1.1 System Bus Interface............................................................................................... 7
3.1.2 Processor Support ...................................................................................................7
3.1.3 Memory Subsystem ................................................................................................. 8
3.2 Intel® 6321ESB I/O Controller Hub ........................................................................ 16
3.2.1 PCI Subsystem ......................................................................................................16
3.2.2 Serial ATA Support ................................................................................................17
3.2.3 Parallel ATA (PATA) Support ................................................................................ 17
3.2.4 USB 2.0 Support.................................................................................................... 18
3.3 Video Support ........................................................................................................18
3.4 Network Interface Controller (NIC) ........................................................................ 19
3.4.1 Intel® I/O Acceleration Technology ........................................................................ 19
3.4.2 MAC Address Definition......................................................................................... 19
3.5 Super I/O ...............................................................................................................19
4. Connector / Header Locations and Pin-outs............................................................................21
4.1 Board Connector Information................................................................................. 21
4.2 Power Connectors ................................................................................................. 21
4.3 I/O Connector Pin-out Definition ............................................................................22
4.3.1 VGA Connector...................................................................................................... 22
4.3.2 I/O Mezzanine Card Connector ............................................................................. 22
4.3.3 Midplane Signal Connector.................................................................................... 23
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Table of Contents Intel® Compute Module MFS5000SI TPS
4.3.4 Serial Port Connector ............................................................................................24
4.3.5 USB 2.0 Connectors ..............................................................................................25
5. Jumper Block Settings ............................................................................................................26
5.1 Recovery Jumper Blocks ....................................................................................... 26
5.1.1 CMOS Clear and Password Reset Usage Procedure ...........................................27
5.1.2 BMC Force Update Procedure .............................................................................. 27
5.1.3 System Status LED – BMC Initialization................................................................ 28
6. Product Regulatory Requirements .........................................................................................29
6.1 Product Regulatory Requirements......................................................................... 29
6.2 Product Regulatory Compliance and Safety Markings ..........................................29
6.3 Product Environmental/Ecology Requirements .....................................................29
6.4 Product Environmental/Ecology Markings ............................................................. 29
Appendix A: Integration and Usage Tips .......................................................................................30
Appendix B: BMC Sensor Tables....................................................................................................31
Appendix C: POST Error Messages and Handling ...........................................................................37
Appendix D: Supported Intel
®
Modular Server System....................................................................40
Glossary.......................................................................................................................................41
Reference Documents..................................................................................................................44
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Intel® Compute Module MFS5000SI TPS List of Figures
List of Figures
Figure 1. Component and Connector Location Diagram ..............................................................3
Figure 2. Intel
Figure 3. Intel
Figure 4. Compute Module Functional Block Diagram .................................................................6
Figure 5. CEK Processor Mounting ..............................................................................................8
Figure 6. Memory Layout ..............................................................................................................9
Figure 7. Recommended Minimum Two-DIMM Memory Configuration ......................................12
Figure 8. Recommended Four-DIMM Configuration................................................................... 13
Figure 9. Single Branch Mode Sparing DIMM Configuration ...................................................... 14
Figure 10. Recovery Jumper Blocks ...........................................................................................26
Figure 11. Intel
®
Compute Module MFS5000SI Front Panel Layout............................................... 4
®
Compute Module MFS5000SI – Hole and Component Positions ........................5
®
Modular Server System MFSYS25 ..................................................................40
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List of Tables Intel® Compute Module MFS5000SI TPS
List of Tables
Table 1. I
2
C Addresses for Memory Module SMB ........................................................................9
Table 2. Maximum 8-DIMM System Memory Configuration – x8 Single Rank ........................... 10
Table 3. Maximum 8-DIMM System Memory Configuration – x4 Dual Rank.............................. 10
Table 4. PCI Bus Segment Characteristics................................................................................. 16
Table 5. Video Modes .................................................................................................................18
Table 6. Serial Header Pin-out.................................................................................................... 20
Table 7. Board Connector Matrix ................................................................................................21
Table 8. Power Connector Pin-out (J1A1) .................................................................................. 21
Table 9. VGA Connector Pin-out (J6A1)..................................................................................... 22
Table 10. 120-pin I/O Mezzanine Card Connector Pin-out .........................................................22
Table 11. 96-pin Midplane Signal Connector Pin-out .................................................................23
Table 12. Internal 9-pin Serial ‘A’ Header Pin-out (J1B1) ...........................................................25
Table 13. External USB Connector Pin-out ................................................................................25
Table 14. Recovery Jumpers ......................................................................................................27
Table 15. BMC Sensors.............................................................................................................. 32
Table 16. Analog Sensor Thresholds.......................................................................................... 36
Table 17. POST Error Messages and Handling.......................................................................... 37
Table 18. POST Error Beep Codes ............................................................................................39
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Intel® Compute Module MFS5000SI TPS 0BIntroduction
1. Introduction
This Technical Product Specification (TPS) provides board-specific information detailing the features,
functionality, and high-level architecture of the Intel
Series Chipsets Server Board Family Datasheet should also be referenced for more in-depth detail of
various board subsystems, including chipset, BIOS, System Management, and System Management
software.
®
Compute Module MFS5000SI. The Intel® 5000
1.1 Chapter Outline
This document is divided into the following chapters:
Chapter 1 – Introduction
Chapter 2 – Product Overview
Chapter 3 – Functional Architecture
Chapter 4 – Connector / Header Locations and Pin-outs
Chapter 5 – Jumper Block Settings
Chapter 6 – Product Regulatory Requirements
Appendix A – Integration and Usage Tips
Appendix B – BMC Sensor Tables
Appendix C – Post Error Messages and Handling
Appendix D – Supported Intel
1.2 Intel
®
Compute Module Use Disclaimer
®
Modular Server System
Intel® Modular Server components require adequate airflow to cool. Intel ensures through its own chassis
development and testing that when these components are used together, the fully integrated system will
meet the intended thermal requirements. It is the responsibility of the system integrator who chooses not
to use Intel-developed server building blocks to consult vendor datasheets and operating parameters to
determine the amount of airflow required for their specific application and environmental conditions. Intel
Corporation cannot be held responsible if components fail or the system does not operate correctly when
used outside any of their published operating or non-operating limits.
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1BProduct Overview Intel® Compute Module MFS5000SI TPS
2. Product Overview
The Intel® Compute Module MFS5000SI is a monolithic printed circuit board with features that were
designed to support the high-density compute module market.
2.1 Intel
Processors 771-pin LGA sockets supporting one or two Dual-Core or Quad-Core Intel® Xeon®
Memory 8 keyed DIMM slots supporting fully buffered DIMM technology (FBDIMM) memory.
Chipset Intel® 5000 Chipset family, which includes the following components:
On-board
Connectors/Headers
On-board Video ATI* ES1000 video controller with 16MB DDR SDRAM
On-board Hard Drive
Controller
LAN Two integrated 10/100/1000 Ethernet ports and two optional 10/100/1000 Ethernet
®
Compute Module MFS5000SI Feature Set
Feature Description
processors 5000 sequence, with system bus speeds of 1066 MHz or 1333 MHz
240-pin DDR2-677 FBDIMMs must be used.
®
Intel
Intel
External connections:
Two USB 2.0 ports
Video connector
Internal connectors/headers:
One DH-10 Serial A debug header
One Intel
LSI* 1064e SAS controller
ports, provided by the Dual Gigabit NIC mezzanine module
5000P Memory Controller Hub
®
6321ESB I/O Controller Hub
®
I/O Mezzanine Connector supporting Dual Gigabit NIC Intel® I/O
Expansion Module (Optional)
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Intel® Compute Module MFS5000SI TPS 1BProduct Overview
2.2 Compute Module Layout
2.2.1 Connector and Component Locations
The following figure shows the board layout of the Intel® Compute Module MFS5000SI. Each connector
and major component is identified by a number or letter. A description of each identified item is provided
below the figure.
Description Description
A Midplane Power Connector B Midplane Signal Connector
C POST Code Diagnostic LEDs D SAS Controller
E FBDIMM Slots F Intel® 5000P Memory Controller Hub (MCH)
G CPU #1 Socket H Voltage Regulator Heatsink
I Power/Fault LEDs J Power Button
K Activity and ID LEDs L Video Connector
M USB1 and USB2 Connectors N CPU #2 Socket
O Intel® 6321ESB I/O Controller Hub P CMOS Battery
Q I/O Mezzanine Card Connector
Figure 1. Component and Connector Location Diagram
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1BProduct Overview Intel® Compute Module MFS5000SI TPS
2.2.2 External I/O Connector Locations
The following drawing shows the layout of the external I/O components for the Intel® Compute Module
MFS5000SI.
A USB ports 1 and 2 E Hard Drive Activity LED
B Video F ID LED
C I/O ports 1 and 2 G Power button
D NIC ports 1 and 2 H Power and Fault LEDs
Figure 2. Intel® Compute Module MFS5000SI Front Panel Layout
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Intel® Compute Module MFS5000SI TPS 1BProduct Overview
2.2.3 Compute Module Mechanical Drawings
Figure 3. Intel
®
Compute Module MFS5000SI – Hole and Component Positions
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2BFunctional Architecture Intel® Compute Module MFS5000SI TPS
3. Functional Architecture
The architecture and design of the Intel® Compute Module MFS5000SI is based on the Intel® 5000
Chipset Family. The chipset is designed for systems based on the Dual-Core and Quad-Core Intel
®
processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz. The
Xeon
chipset is made up of two main components: the Memory Controller Hub (MCH) for the host bridge and
the Intel
®
6321ESB I/O controller hub for the I/O subsystem. This chapter provides a high-level
®
description of the functionality associated with each chipset component and the architectural blocks that
make up the server board. For more in-depth detail of the functionality for each
components and each of the functional architecture blocks, see the Intel
®
of the chipset
5000 Series Chipsets Server
Board Family Datasheet.
Figure 4. Compute Module Functional Block Diagram
Note: The previous diagram uses the Intel
®
5000P MCH as a general reference designator for MCH
components supported on this server board.
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Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture
3.1 Intel
®
5000P Memory Controller Hub (MCH)
This section describes the general functionality of the memory controller hub as it is implemented on this
server board.
The MCH is a single 1432-pin FCBGA package, which includes the following core platform functions:
System Bus Interface for the processor subsystem
Memory Controller
PCI Express* Ports, including the Enterprise South Bridge Interface (ESI)
FBD Thermal Management
SMBus Interface
Additional information about MCH functionality can be obtained from the Intel
Server Board Family Datasheet and the Intel
®
5000P Memory Controller Hub External Design
®
5000 Series Chipsets
Specification.
3.1.1 System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front-side bus interfaces
that connect to the Dual-Core and Quad-Core Intel
bus on the MCH uses a 64-bit wide 1066 or 1333 MHz data bus. The 1333-MHz data bus is capable of
transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of
addressing up to 64 GB of memory. The MCH is the priority agent for both front-side bus interfaces, and
is optimized for one processor on each bus.
®
Xeon® processors 5000 sequence. Each front-side
3.1.2 Processor Support
The Intel® Compute Module MFS5000SI supports one or two Dual-Core Intel® Xeon® processors 5100
sequence or Quad-Core Intel
1066 MHz and 1333 MHz. Previous generations of the Intel
®
Compute Module MFS5000SI. To see a list of the latest processors that have been validated on
Intel
this product, refer to
http://support.intel.com/support/motherboards/server/MFS5000SI/ and select
the Supported Processors List.
3.1.2.1 Processor Population Rules
When two processors are installed, both must be of identical revision, core voltage, and bus/core speed.
Mixed processor steppings is supported in N and N-1 configurations only. When only one processor is
installed, it must be in the socket labeled CPU1. The other socket must be empty.
The board is designed to provide up to 115 A of current per processor. Processors with higher current
requirements are not supported.
When using a single processor configuration, a terminator is not required in the second processor socket.
®
Xeon® processors 5300 and 5400 sequence with system bus speeds of
®
Xeon® processor are not supported in the
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2BFunctional Architecture Intel® Compute Module MFS5000SI TPS
3.1.2.2 Common Enabling Kit (CEK) Design Support
The compute module complies with Intel’s Common Enabling Kit (CEK) processor mounting and heatsink
retention solution. The compute module ships with a CEK spring snapped onto the underside of the
server board, beneath each processor socket. The heatsink attaches to the CEK, over the top of the
processor and the thermal interface material (TIM). For the stacking order of the chassis, CEK spring,
server board, TIM, and heatsink, see the following figure.
The CEK spring is removable, allowing for the use of non-Intel heatsink retention solutions.
Note: The processor heatsink and CEK spring shown in the following diagram are for reference purposes
only. The actual processor heatsink and CEK solutions compatible with this generation server board may
be of a different design.
Heatsink assembly
Thermal interface material (TIM)
Server board
CEK spring
Chassis
Figure 5. CEK Processor Mounting
3.1.3 Memory Subsystem
The MCH masters four fully buffered DIMM (FBD) memory channels. FBD memory utilizes a narrow highspeed frame-oriented interface referred to as a channel. The four FBD channels are organized into two
branches of two channels per branch. Each branch is supported by a separate memory controller. The
two channels on each branch operate in lock step to increase FBD bandwidth. On the server board, the
four channels are routed to eight DIMM slots and are capable of supporting registered DDR2-533 and
DDR2-667 FBDIMM memory (stacked or unstacked). Peak theoretical memory data bandwidth is 6.4
GB/s with DDR2-533 and 8.0 GB/s with DDR2-667.
®
On the Intel
consists of channels A and B, and Branch 1 consists of channels C and D. FBD memory channels are
organized into two branches for RAID 1 (mirroring) support.
Compute Module MFS5000SI, a pair of channels becomes a branch where Branch 0
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Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture
Channel B
Channel A
Channel C
Channel D
MCH
DIMM A1
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
Branch 0
DIMM D2
Branch 1
Figure 6. Memory Layout
To boot the system, the system BIOS on the server board uses a dedicated I
2
C bus to retrieve DIMM
information needed to program the MCH memory registers. The following table provides the I
addresses for each DIMM slot.
TP02299
2
C
2
Table 1. I
C Addresses for Memory Module SMB
Device Address
DIMM A1 0xA0
DIMM A2 0xA2
DIMM B1 0xA0
DIMM B2 0xA2
DIMM C1 0xA0
DIMM C2 0xA2
DIMM D1 0xA0
DIMM D2 0xA2
3.1.3.1 Memory RASUM Features
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and
Manageability) features. These features include the Intel
1
®
x4 Single Device Data Correction (Intel® x4
SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors,
Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. For more information regarding these
features, see the Intel
®
5000 Series Chipsets Server Board Family Datasheet.
1
DIMM Sparing and Memory Mirroring features will be made available post production launch with a BIOS update.
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