Intel BX80623I52500K, Pentium 4 Specification

Intel® Pentium® 4 Proce sso r

Specification Update

August 2008

Revision 071

Document Number: 249199-071

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RI GHT. I ntel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Intel Pentium 4 processor, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Pentium® 4 processor may contain design defects or errors known as errata which may cause the product to deviate

2 Specification Update

Contents

Preface.............................................................................................................................9

Summary Tables of Changes.............................................................................................. 11

General Information ......................................................................................................... 21

Identification Information.................................................................................................. 24

Errata ............................................................................................................................ 31

Specification Changes....................................................................................................... 69

Specification Clarifications ................................................................................................. 70

Documentation Changes ................................................................................................... 74

Specification Update 3

Revision History

Revision Description Date

-001

-002

-003

-004

-005

-006

-007

-008

-009

-010

-011

-012

-013

-014

-015

-016

-017

• Initial Release

• Added errata numbers N41-N44.

• Updated Intel

Pentium® 4 Processor Identification Information. Updated erratum N40. Added errata N45 through N46.

• Added errata N47.

• Updated the processor identification information table.

Removed Possib le system hang du e t o ca cheable line-sp lit loa ds with page-tables in uncacheable (UC) space and Uncacheable memory type prevents physical address code breakpoint match

erratum. Renumbered remaining errata. Modified the workaround for N45. Added errata N46 and N47. Added processor marking information.

• Updated plans column for errata N6, N7, N10, N11, N14, N18,

N19, N21, N23 – N28, N30 – N35, and N41

• Added information for the Intel

Pentium® 4 processor in the

478-pin package, Added erratum N48.

• Updated the Intel

Pentium® 4 Processor Identification

Information table. Added erratum N49.

• Updated Specification Update product key to include the Intel

™

Xeon

processor. Updated erratum N45, added erratum N50

and Specification Change N1.

• Added errata N51 and Specification Clarification N1. Updated

Intel

Pentium® 4 Processor Identification Information table.

• Added errata N52 and N53 and Specification Clarification N2.

• Release for launch of new frequencies and the 478-pin

package. Updated Intel

Pentium® 4 Processor Identification

Information table.

• Added errata N54 -- N56.

• Added erratum N57. Added Specification Clarification N3.

Updated Intel

Pentium® 4 Processor Identification Information

table.

• Added Documentation Changes N1 and N2.

• Added erratum N58 and Documentation Change N3.

• Added Intel

Pentium® 4 Processor with 512-KB cache in 0.13

micron process information.

November 2000

December 2000

January 2001

February 2001

March 2001

April 2001

May 2001

June 2001

July 2001

August 2001

September

October 2001

November 2001

December 2001

January 2002

2001

4 Specification Update

Revision Description Date

-018

-019

-020

-021

-022

-023

-024

-025

-026

-027

-028

-029

-030

-031

-032

-033

-034

-035

-036

-037

-038

• Added Documentation Change N4.

• Added errata N60 and N61.

• Added Documentation Change N5

• Added errata N62 and N63. Removed Documentation Changes,

Specification Clarifications, and Specification Changes that have been incorporated into documentation. Added Specification Clarifications N1 – N5.

• Updated erratum N37. Added errata N64. Added Specification

Change N1 to N3. Removed Documentation Changes that have been incorporated into the documentation. Added Documentation Changes N1 and N2.

• Added erratum N65. Removed Documentation Changes that

have been incorporated into the documentation. Added Documentation Change N1 and N2.

• Added erratum N66. Removed Documentation Changes that

have been incorporated into the documentation. Added Documentation Changes N3 to N12.

• Removed Documentation Changes that have been incorporated

into the documentation.

• Added 2.80 GHz and C1 stepping information.

• Updated erratum N39. Added Documentation Changes N3 to

N24.

• Added erratum N67. Added Documentation Changes N25 to

N32.

• Added Package Markings under General Information.

• Added Erratum N68. Added Specification Clarification N1.

Added Specification Changes N3 and N4. Added Documentation Changes N33-42.

• Added eight S-spec numbers under identification information

table.

• Added Errata N69 and N70.

• Added Erratum N71.

• Added full graphics range to General Information section. Minor

typographical errors from text conversion corrected.

• Updated Erratum N70. Added new Errata N72 and N73.

• Added S-spec numbers under identification information table.

• Added Erratum N74.

• Added Specification Clarification N2.

• Added Erratum N75 and Updated Errata N68 and N74.

• Added 3.20 GHz S-spec number information.

January 2002

February 2002

March 2002

April 2002

May 2002

June 2002

July 2002

August 2002

September

2002

October 2002

November 2002

December 2002

January 2003

February 2003

March 2003

April 2003

May 2003

June 2003

Specification Update 5

Revision Description Date

-039

-040

-041

-042

-043

-044

-045

-046

-047

-048

-049

-050

• Added Errata N76 and N77.

• Added Erratum N78 and Updated Erratum N69.

• Added N2 to specification changes.

• Added Errata N79 to N82.

• Added Erratum N83.

• Release for launch of Intel

Pentium® 4 Processor Extreme

Edition Supporting Hyper-Threading Technology.

• Added Erratum N84

Added S-Spec number under identification information table.

• Added Erratum N85 and Updated Erratum N83.

• Release 3.40 GHz Intel

Pentium® 4 Processor Extreme Edition

Supporting Hyper-Threading Technology.

• Added S-Spec number under identification information table.

• Added Intel

Pentium® 4 processor on 90 nm process.

• Removed Specification Change N2.

• Removed Specification Clarification Change N2

• Added Errata 90 to N92.

o N9 and /N91 removed in rev049. o N92 changed to N86

• Added S-Spec number under identification information table.

• Updated Errata N9 and N85.

• Updated Erratum N38

• Added Erratum N93.

o N93 is errata N87 in rev049

• Relocated Intel

content to the Intel

Pentium® 4 processor on 90 nm process

Pentium® 4 Processor on 90 nm Process

Specification Update

o Removed Figure 5 o Removed Notes 23 thru 26 in Table 1. Notes 27/28

renumbered to Notes 23/24 respectively

o Removed corresponding S-Spec numbers: SL7B8,

SL79L, SL79K, SL7D8, SL7E8

o Removed Errata N86-N90. Errata N91, N92, and N93

renumbered to N86, N87, and N88 respectively.

o Removed references to Intel

Pentium® 4 processor on

90 nm process documentation

• Added Erratum N89 thru N91

• Added Figure Numbers to each Figure

• Added content for Intel Pentium 4 Extreme Edition on 0.13

July 2003

August 2003

September

2003

October 2003

November 2003

“Out of Cycle”

February 2004

March 2004

April 2004

May 2004

June 2004

“Out of Cycle”

June 21 2004

6 Specification Update

Revision Description Date

micron process in 775-LGA package

o Added Figure 5 o Added Datasheet information and its link o Added S-spec number SL7GD

-051

-052

-053

-054

-055

-056

-057

-058

-059

-060

-061

-062

-063

-064

-065

-066

-067

-068

• Added S-Spec number under identification information table

• Updated Summary Tables of Changes (Errata N16, N51, N56,

N69, N79, N84, N85 and N92)

• Modified erratum N69, and added erratum N92

• Updated Figure 7 diagram

• Added Errata N93-95

• Updated processor identification table, and added Errata N96-

• Added 1066 Products in processor identification table

• Added Erratum N98

• Added Erratum N99

• Added Erratum N100

• Updated code used in summary table, and updated processor

identification table

• Added Specification Clarification and updated processor

identification table

• Updated Related Documents table

• Added new Erratum N101

• Updated processor identification information table

• Updated Erratum N68.

• Updated links to Software Developers Manuals.

• Added errata N102 and N103.

• Added erratum N104. Updated Summary Table of Changes.

• Updated Software Developer Manuals Name. Updated

Summary Table of Changes.

• Updated Summary Table of Changes.

Aug 2004

“Out of Cycle”

August 12,

2004

Sept 2004

Oct 2004

“Out of Cycle”

November 1,

2004

Nov 2004

December 2004

February 2005

April 2005

July 2005

October 2005

January 2006

March 2006

April 2006

June 2006

October 2006

December 2006

January 2007

Specification Update 7

Revision Description Date

-069

-070

-071

• Updated Summary Table of Changes.

• Updated Summary Table of Changes

May 2007

April 2008

August 2008

8 Specification Update

Preface

This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.

Information types defined in the Nomenclature section of this document are consolidated into this update document and are no longer published in other documents. This document may also contain information that has not been previously published.

Affected Documents

Document Title Document

Intel® Pentium® 4 Processor in the 423-pin Package

datasheet

Intel® Pentium® 4 Processor in the 478-pin Package datasheet

Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and In te l Edition Supportin g H y p e r-Thre a d in g Tech nology

Intel® Pentium® 4 Processor Extreme Edition on 0.13 Micron Process in the 775-land Package datasheet

NOTES:

1. Hyper-Threading Technology requires a computer system with an Intel

processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See <<http:// www.intel.com/info/hyperthreading/>> for more information including details on which processors support HT Technology.

Pentium® 4 Processor Extreme

datasheet

Number/Location

http://developer.intel.com/d esign/pentium4/datashts/24

http://developer.intel.com/d esign/pentium4/datashts/29

http://intel.com/design/Penti

um4/datashts/302351.htm

249198-005

9198.htm

249887-003

9887.htm

298643-012

8643.htm

302350-001

Pentium® 4

Related Documents

Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 1: Basic

Specification Update 9

Document Title and Link

Architecture

Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M

Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z

Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 3A: System Programming Guide

Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 3B: System Programming Guide

Nomenclature

Preface

Document Title and Link

Errata are design defects or errors. Errata may cause the Intel

Pentium® 4 processor’s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications.

Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

10 Specification Update

Summary Tables of Changes

The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations:

Codes Used in Summary Table

Stepping

X: Erratum, Specification Change or Clarification that applies

to this stepping.

Status

Row

Note: Each Specification Update item is prefixed with a capital letter to distinguish the

(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification

change does not apply to listed stepping.

Doc: Document change or update that will be implemented.

PlanFix: This erratum may be fixed in a future stepping of the

product.

Fixed: This erratum has been previously fixed.

NoFix: There are no plans to fix this erratum.

Shaded: This item is either new or modified from the previous

version of the document.

product. The key below details the letters that are used in Intel’s microprocessor Specification Updates:

A = Dual-Core Intel® Xeon® processor 7000 sequence

C = Intel® Celeron® processor

D = Dual-Core Intel® Xeon® processor 2.80 GHz

Specification Update 11

Summary Tables of Changes

E = Intel® Pentium® III processor

F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D

processor

I = Dual-Core Intel® Xeon® processor 5000 series

J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache

K = Mobile Intel® Pentium® III processor

L = Intel® Celeron® D processor

M = Mobile Intel® Celeron® processor

N = Intel® Pentium® 4 processor

O = Intel® Xeon® processor MP

P = Intel ® Xeon® processor

Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology

on 90-nm process technology

R = Intel® Pentium® 4 processor on 90 nm process

S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2

cache versions)

T = Mobile Intel® Pentium® 4 processor-M

U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache

V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA

package

W= Intel® Celeron® M processor

X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and

Intel® processor A100 and A110 with 512-KB L2 cache

Y = Intel® Pentium® M processor

Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus

AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor

Extreme Edition 955, 965

AB = Intel® Pentium® 4 processor 6x1 sequence

AC = Intel(R) Celeron(R) processor in 478 pin package

AD = Intel(R) Celeron(R) D processor on 65nm process

AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm

process

AF = Dual-Core Intel® Xeon® processor LV

AG = Dual-Core Intel® Xeon® processor 5100 series

AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor

technology

AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop

processor E6000 and E4000 sequence

12 Specification Update

Summary Tables of Changes

AJ = Quad-Core Intel® Xeon® processor 5300 series

AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®

Core™2 Quad processor Q6000 sequence

AL = Dual-Core Intel® Xeon® processor 7100 series

AM = Intel® Celeron® processor 400 sequence

AN = Intel® Pentium® dual-core processor

AO = Quad-Core Intel® Xeon® processor 3200 series

AP = Dual-Core Intel® Xeon® processor 3000 series

AQ = Intel® Pentium® dual-core desktop processor E2000 sequence

AR = Intel® Celeron® processor 500 series

AS = Intel® Xeon® processor 7200, 7300 series

AT = Intel® Celeron® processor 200 series

AU = Intel® Celeron® Dual Core processor T1400

AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad

processor Q9000 series

AW = Intel® Core™ 2 Duo processor E8000 series

AX = Quad-Core Intel® Xeon® processor 5400 series

AY= Dual-Core Intel® Xeon® processor 5200 series

AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-

nm Process

AAA = Quad-Core Intel® Xeon® processor 3300 series

AAB = Dual-Core Intel® Xeon® E3110 Processor

AAC = Intel® Celeron® dual-core processor E1000 series

AAD = Intel® Core™2 Extreme Processor QX9775Δ

AAE = Intel® Atom™ processor Z5xx series

AAF = Intel® Atom™ processor 200 series

AAG = Intel® Atom™ processor N series

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

I/O restart in SMM may fail after

N1 X X X X X X X X No Fix

N2 X X X X X X X X No Fix

simultaneous machine check exception (MCE)

MCA registers may contain invalid information if RESET# occurs and PWRGOOD is not held asserted

Specification Update 13

Summary Tables of Changes

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

Uncacheable (UC) code in same line as

N3 X X X X Fixed

N4 X X X X X X X X No Fix Transaction is not retried after BINIT#

N5 X X X X X X X X No Fix

N6 X Fixed

N7 X Fixed

N8 X X X X X X X X No Fix

N9 X X X X X X X X No Fix

N10 X Fixed

N11 X Fixed

N12 X X X X X X X X No Fix

N13 X X X X X X X X No Fix

N14 X Fixed

N15 X X X X Fixed

N16 X X X X Fixed

N17 X X X X Fixed

N18 X Fixed

N19 X Fixed

N20 X X X X Fixed

write back (WB) data may lead to data corruption

Invalid opcode 0FFFh requires a ModRM byte

RFO-ECC-snoop-MCA combination can result in two lines being corrupted in main memory

Overlap of MTRRs with the same memory type results in a type of uncacheable (UC)

FSW may not be completely restored after page fault on FRSTOR or FLDENV instructions

The Proce sso r Signals Pa ge-Fault Excep t ion (#PF) Instead of Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B Instruction

IERR# may not go active when an internal error occurs

All L2 cache uncorrectable errors are logged as data writes

When in no-fill mode the memory type of large pages are incorrectly forced to uncacheable

Processor may hang due to speculative page walks to non-existent system memory

Load operations may get stale data in the presence of memory address aliasing

Writing a performance counter may result in incorrect value

IA32_MC0_STATUS register overflow bit not set correctly

Performance counter may contain incorrect value after being stopped

The TAP drops the last bit during instruction register shifting

Data breakpoints on the high half of a floating point line split may not be captured

MCA error code field in IA32_MC0_STATUS register may become out of sync with the rest of the

14 Specification Update

Summary Tables of Changes

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

N21 X Fixed

N22 X X X X X X X X No Fix

N23 X Fixed

N24 X Fixed

N25 X Fixed

N26 X Fixed

N27 X Fixed

N28 X Fixed

N29 X X Fixed

N30 X Fixed

N31 X Fixed

N32 X Fixed

N33 X Fixed

N34 X Fixed

N35 X Fixed

N36 X X Fixed

N37 X X X X X X X X No Fix

N38 X X X X X X X X No Fix

Processor may hang on a correctable error and snoop combination

The IA32_MC1_STATUS register may contain incorrect information for correctable errors

MCA error incorrectly logged as prefetches

Speculative loads which hit the L2 cache and get an uncorrectable error will log erroneous information

Processor may fetch reset vector from cache if A20M# is asserted during init

A correctable error on an L2 cache shared state line hit with go to invalid snoop hangs processor

System hang due to uncorrectable error and bus lock combination

Incorrect address for an L1 tag parity error is logged in IA32_MC1_ADDR register

REP MOV instruction with overlapping source and destination may result in data corruption

Stale data in processor translation cache may result in hang

I/O buffers for FERR#, PROCHOT# and THERMTRIP# are not AGTL+

RFO and correctable error combination may cause lost store or hang

RFO and correctable error may incorrectly signal the machine check handler

Processor may report invalid TSS fault instead of double fault during mode C paging

IA32_MC0_STATUS incorrect after illegal APIC request

Thermal status log bit may not be set when the thermal control circuit is active

Debug mechanisms may not function as expected

Machine check architecture error reporting and recovery may not work

Specification Update 15

Summary Tables of Changes

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

as expected

N39 X X X X Fixed

N40 X X X X X X X X No Fix

N41 X Fixed

N42 X X X X Fixed

N43 X X X X X X X X No Fix

N44 X X X X Fixed

N45 X X Fixed

N46 X X Fixed

N47 X X X Fixed

N48 X X X X Fixed

N49 X X X X Fixed

N50 X X X X X Fixed

N51 X X X Fixed

N52 X X X X X X X X No Fix

N53 X X X X X Fixed

N54 X X X X Fixed

N55 X X X X X X X X No Fix

Processor may Timeout Waiting for a Device to Respond after ~0.67 Seconds

Cascading of Performance Counters does not work Correctly when Forced Overflow is Enabled

Possible Machine Check Due to LineSplit Loads with Page-Tables in Uncacheable (UC) Space

IA32_MC1_STATUS MSR ADDRESS VALID bit may be set when no Valid Address is Available

EMON event counting of x87 loads may not work as expected

Software controlled clock modulation using a 12.5% or 25% duty cycle may cause the processor to hang

Speculative page fault may cause livelock

PAT index MSB may be calculated incorrectly

SQRTPD and SQRTSD may return QNaN indefinite instead of negative zero

Bus invalidate line requests that return unexpected data may result in L1 cache corruption

Write Combining (WC) load may result in unintended address on system bus

Incorrect data may be returned when page tables are in Write Combining (WC) memory space

Buffer on resistance may exceed specification

Processor issues inconsistent transaction size attributes for locked operation

Multiple accesses to the same S-state L2 cache line and ECC error combination may result in loss of cache coherency

Processor may hang when resuming from Deep Sleep state

When the processor is in the System Management Mode (SMM), debug registers may be fully writeable

16 Specification Update

Summary Tables of Changes

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

Associated counting logic must be

N56 X X X X Fixed

configured when using Event Selection Control (ESCR) MSR

IA32_MC0_ADDR and IA32_MC0_MISC

N57 X X X X X X X X No Fix

registers will contain invalid or stale data following a Data, Address, or Response Parity Error

CR2 may be incorrect or an incorrect

N58 X X X X X Fixed

page fault error code may be pushed onto stack after execution of an LSS instruction

N59 X Fixed

BPM[5:3]# V specification

does not meet

Processor may hang under certain

N60 X X X X No Fix

frequencies and 12.5% STPCLK# duty cycle

System may hang if a fatal cache error causes Bus Write Line (BWL)

N61 X X X X X X X X No Fix

transaction to occur to the same cache line address as an outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL)

N62 X X X X X Fixed

L2 cache may contain stale data in the Exclusive state

Re-mapping the APIC base address to

N63 X X X X X X Fixed

a value less than or equal to 0xDC001000 may cause IO and Special Cycle failure

N64 X X X Fixed

N65 X X X X X Fixed

Erroneous BIST result found in EAX register after reset

Processor does not flag #GP on nonzero write to certain MSRs

Simultaneous assertion of A20M# and

N66 X X X X X X X X No Fix

INIT# may result in incorrect data fetch

N67 X X X X X Fixed

N68 X X X X X X X X No Fix

N69 X X

Plan

Fix

N70 X Fixed

N71 X X X X No Fix

CPUID instruction returns incorrect number of ITLB entries

A Write to an APIC Register Sometimes May Appear to Have Not Occurred

STPCLK# Signal Assertion under Certain Conditions May Cause a System Hang

Store to Load Data Forwarding may Result in Switched Data Bytes

Parity Error in the L1 Cache may Cause the Processor to Hang

Specification Update 17

Summary Tables of Changes

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

The TCK Input in the Test Access Port

N72 X X Fixed

N73 X X X No Fix

N74 X X

N75 X X X No Fix

N76 X X X X X X No Fix

N77 X X X X X X X X No Fix

N78 X X X X X X X X No Fix

N79 X X1 X1

N80 X X X X X X X X No Fix

N81 X X X X X X X X No Fix

N82 X X X No Fix

N83 X X X X X X X X

N84 X

N85 X X X No Fix

Plan

Fix

Plan

Fix

Plan

Fix

Plan

Fix

(TAP) is Sensitive to Low Clock Edge Rates and Prone to Noise Coupling Onto TCK's Rising or Falling Edges

Disabling a Local APIC Disables Both Logical Processor APICs on a HyperThreading Technology Enabled Processor

A circuit marginality in the 800 MHz Front Side Bus power save circuitry may cause a system and/or application hang or may result in incorrect data

Using STPCLK# and Executing Code From Very Slow Memory Could Lead to a System Hang

Changes to CR3 Register do not Fence Pending Instruction Page Walks

The State of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May be Incorrect

Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock

Simultaneous Page Faults at Similar Page Offsets on Both Logical Processors of an Hyper-Threading Technology Enabled Processor May Cause Application Failure

System Bus Interrupt Messages Without Data Which Receive a HardFailure Response May Hang the Processor

Memory Type of the Load Lock Different from its Corresponding Store Unlock

Shutdown and IERR# May Result Due to a Machine Check Exception on a Hyper-Threading Technology Enabled Processor

A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect Address to Be Reported to the #GP Exception Handler

Simultaneous Cache Line Eviction From L2 and L3 Caches may Result in the Write Back of Stale Data

Locks and SMC Detection May Cause the Processor to Temporarily Hang

18 Specification Update

Summary Tables of Changes

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

Incorrect Debug Exception (#DB) May

N86 X X X X X X X X No Fix

Occur When a Data Breakpoint is set on an FP Instruction

N87 X

Plan Fix

N88 X X X X X X X X No Fix

Modified Cache Line Eviction From L2 Cache May Result in Writeback of Stale Data

xAPIC Ma y Not Report Some Illegal Vector Errors

Incorrect Duty Cycle is Chosen whe n On-

N89 X X X

Plan

Fix

Demand Clock Modula tion is Enabled in a Processor Supporting Hyper-Threading Technology

Memory Aliasing of Pages as Uncacheable

N90 X X X X X X X X No Fix

Memory Type and Write Back (WB) May Hang the System

N91 X X

Plan

Fix

N92 X X X No Fix

N93 X X X X X X X X No Fix

A Timing Marginality in the Instruction Decode r Unit May Cause an Unpredictable Applicatio n Behav ior and/or System Hang

Missing Stop Gran t Ackn owledge Special Bus Cycle May Cause a System Hang

Check Exceptions May not Update LastExcept ion Record MSRs (LERs)

Stores to Page Tab l es May Not Be Visible to

N94 X X X X X X X X No Fix

Pagewalks for Subsequent Loads Without Serializing or Inv alidating the Page Table Entry

N95 X X

Plan

Fix

A Timing Marginality in the Arithmetic Lo gic Unit (ALU) May Cause Indeterminate Behavior

With TF (Trap Flag) Asserted , F P I nstruction

N96 X X X X X X X X No Fix

That Triggers an Unmasked FP Exception May Take Sing le Step Tra p Before Retirement of Instruction

BTS(Branch Trace Store) an d PEBS(Precise

N97 X X X X X X X X No Fix

Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer

Brand String Field Reports Incorrect Maximum

N98 X No Fix

Operating Frequency on Intel Extreme Edition Proce ssor with 1066 MHz

FSB Memory Ordering Failure May Occur wi th

Snoop Filtering Third Party Agents after

N99 X X X X X X X X No Fix

Issuing and Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus Locked Write) Transaction

Control Register 2 (CR2) Can be Updated

N100 X X X X X X X X No Fix

during a REP MOVS/STOS Instruction with Fast Strings Enabled

N101 X X X X X X X X No Fix

Writing the Local Vector Table (LVT)

Pentium® 4

Specification Update 19

Summary Tables of Changes

No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA

when an Interrupt is Pending May Cause an Unexpected Interrupt

Using 2M/4M Pages When A20M# Is

N102 X X X X X X X X No Fix

N103 X X X X X X X X No Fix

N104 X X X X X X X X No Fix

NOTE:

1. For these steppings, this erratum may be worked around in BIOS.

Asserted May Result in Incorrect Address Translations

Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue

Debug Status Register (DR6) Breakpoint Condition Detected Flags May be set Incorrectly

No. B2 C1 D0 E0 B0 C1 D1 M0 Plans SPECIFICATION CHANGES

There are no specification changes in

this Specification Update revision.

No. B2 C1 D0 E0 B0 C1 D1 M0 Plans SPECIFICATION CLARIFICATIONS

N1 X X X X X X X X Doc

Specification clarification with respect to time stamp counter

No. B2 C1 D0 E0 B0 C1 D1 M0 Plans DOCUMENTATION CHANGES

There are no Documentation Changes

in this Specification Update revision.

20 Specification Update

m ©

S -

2 -

General Information

General Informa ti o n

Figure 1 Intel® Pentium® 4 Processor in the 423-Pin Package and Boxed Pentium 4

Processor in the 423-Pin Package Markings

Frequency/Cache/Bus/Voltage

2-D Matrix Mark

S-Spec/Country of Assy

FPO - Serial #

Intel

®bbb

pentium

1.5GHz/256/400/1.7V

1.5GHz/256/400/1.7V SL4SH MALAY

SYYYY XXXXXX

1234567

FFFFFFFF-NNNN i m c ‘00

i m c ‘00

®bbb

-1272

Figure 2 Intel® Pentium® 4 Processor in the 478-Pin Package Markings Example 1

S-Spec/Count ry of Assy

Frequency/Cache/Bus/Voltage

GHZ/256/400/1.75V

SYYYY XXXXXX

FPO - Serial #

2-D Matr ix Mark

Figure 3 Pentium 4 Processor in the 478-Pin Package Markings Example 2

Spec/Country of Assy

FPO - Serial #

D Matrix Mark

Specification Update 21

‘02

i PENTIUM® 4

2A GHZ/512/400/1.50V

2 GHZ/256/400/1.75V

SYYYY XXXXXX

FFFFFFFF - NNNN

FFFFFFFF

‘01

NNNN

Frequency/Cache/Bus/Voltage

General Information

Figure 4 Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process,

Intel

Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Boxed Pentium 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Processor Markings

m c

`01

Frequency/Cache/Bus/Voltage

2-D Matr ix Mark

S-Spec /C ountry of Assy

FPO – Ser ial #

INTEL PENTIUM® 4

2.40 GHZ/512/800/1.50V SYYYY XXXXXX

FFFFFFFF–NNNN

Figure 5 Multiple VIDs Example 1

`03

AAAAAAAA NNNN

Frequency/Cache/Bus

unique unit identifier ATPO Serial #

S-Spec/Country of Assy

FPO

2-D Matrix Mark

INTEL

PENTIUM® 4

2.40 GHZ/512/800 SYYYY XXXXXX

FFFFFFFF

Figure 6 Multiple VIDs Example 2

m c

`01

Frequency/Cache/Bus

2-D Matrix Mark

S-Spec/Country of Assy

FPO – Serial #

INTEL PENTIUM® 4

2.40 GHZ/512/800 SYYYY XXXXXX

FFFFFFFF–NNNN

22 Specification Update

General Information

Figure 7 Intel® Pentium® 4 Extreme Edition on 0.13 micron in the 775-Land LGA

Package Marking

Frequency/

S-Spec/

Country of Assy

FPO

2-D Matrix Mark

m c

INTEL

PENTIUM®4

3.40 GHZ/512/800 SYYYY XXXXXX FFFFFFFF

`04

ATTPO S/N

L2 Cache/

Bus

Uniqu e Un it

Identifier

ATPO

Serial #

Specification Update 23

+ 51 hidden pages

Intel BX80623I52500K, Pentium 4 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual