Intel BV80605001914AG - Processor - 1 x Xeon X3430, BX80605X3440 - Quad Core Xeon X3440, Xeon 3400 Series Specification

Intel® Xeon® Processor 3400 Series

Specification Update

May 2010

Reference Number: 322373-009

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Specification Update

Contents

Revision History...............................................................................................................5

Preface .............................................................................................................................. 6

Summary Tables of Changes.......................................................................................... 8

Identification Information ..............................................................................................16

Errata...............................................................................................................................19

Specification Changes...................................................................................................55

Specification Clarifications ...........................................................................................56

Documentation Changes ...............................................................................................57

Specification Update

Contents

Specification Update

Revision History

Revision Description Date

-001 Initial Release September 2009

-002 Added Errata AAO101-AAO109. October 2009

Updated the Processor Identification Table to include two additional SKUs:

-003

-004 Updated Errata AAO89 and AAO99. December 2009

-005 Added Erratum AAO114. January 2010

-006 Added Errata AAO115 and AAO116. February 2010

-007 Added Erratum AAO17. March 2010

-008 Added Errata AAO18 and AAO19. April 2010

-009 Updated the Processor Identification Table to include Intel® Xeon® Processor X3480 May 2010

• Intel® Xeon® Processor X3430 (S-Spec Number: SLBLJ).

• Intel® Xeon® Processor L3426 (S-Spec Number: SLBN3).

Added Errata AAO110- AAO113.

November 2009

Specification Update

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Xeon® Processor 3400 Series Datasheet - Volume 1 322371-003

Intel

Xeon® Processor 3400 Series Datasheet - Volume 2

Intel

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to

deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

Specification Update

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

Status

Row

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping.

(No mark)

or (Blank box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

(Page): Page location of item in this document.

Doc: Document change or update will be implemented.

Plan Fix: This erratum may be fixed in a future stepping of the product.

Fixed: This erratum has been previously fixed.

No Fix: There are no plans to fix this erratum.

Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document.

Specification Update

Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates:

A = Intel

C = Intel

D = Intel

Xeon® processor 7000 sequence

Celeron® processor

Xeon® processor 2.80 GHz

E = Intel® Pentium® III processor

F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor

I = Intel

Xeon® processor 5000 series

J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache

K = Mobile Intel® Pentium® III processor

L = Intel

Celeron® D processor

M = Mobile Intel® Celeron® processor

N = Intel® Pentium® 4 processor

O = Intel

Xeon® processor MP

P = Intel ® Xeon® processor

Q = Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading technology on 90-

nm process technology

R = Intel

Pentium® 4 processor on 90 nm process

S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache

versions)

T = Mobile Intel

Pentium® 4 processor-M

U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache

V = Mobile Intel

Celeron® processor on .13 micron process in Micro-FCPGA package

W= Intel® Celeron® M processor

X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and Intel® processor

A100 and A110 with 512-KB L2 cache

Y = Intel

Z = Mobile Intel

AA = Intel

Pentium® M processor

Pentium® 4 processor with 533 MHz system bus

Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme

Edition 955, 965

AB = Intel

AC = Intel

AD = Intel

AE = Intel

AF = Intel

Pentium® 4 processor 6x1 sequence

Celeron® processor in 478 pin package

Celeron® D processor on 65nm process

Core™ Duo processor and Intel® Core™ Solo processor on 65nm process

Xeon® processor LV

AG = Intel® Xeon® processor 5100 series

AH = Intel

AI = Intel

Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology

Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000

and E4000 sequence

Specification Update

AJ = Intel® Xeon® processor 5300 series

AK = Intel

Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad

processor Q6000 sequence

AL = Intel

AM = Intel

AN = Intel

Xeon® processor 7100 series

Celeron® processor 400 sequence

Pentium® dual-core processor

AO = Intel® Xeon® processor 3200 series

AP = Intel® Xeon® processor 3000 series

AQ = Intel

Pentium® dual-core desktop processor E2000 sequence

AR = Intel® Celeron® processor 500 series

AS = Intel® Xeon® processor 7200, 7300 series

AU = Intel

Celeron® dual-core processor T1400

AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000

series

AW = Intel

Core™2 Duo processor E8000 series

AX = Intel® Xeon® processor 5400 series

AY = Intel® Xeon® processor 5200 series

AZ= Intel

Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm process

AAA= Intel® Xeon® processor 3300 series

AAB= Intel® Xeon® E3110 processor

AAC= Intel

Celeron® dual-core processor E1000 series

AAD = Intel® Core™2 Extreme processor QX9775

AAE = Intel® Atom™ processor Z5xx series

AAF = Intel

Atom™ processor 200 series

AAG = Intel® Atom™ processor N series

AAH = Intel® Atom™ processor 300 series

AAI = Intel

Xeon® processor 7400 series

AAJ = Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel® Core™ i7-900

desktop processor series

AAK= Intel

AAL = Intel

AAN = Intel

AAO = Intel

AAP = Intel

Xeon® processor 5500 series

Pentium® dual-core processor E5000 series

Core™ i7-800 and i5-700 desktop processor series

Xeon® processor 3400 series

Core™ i7-900 mobile processor Extreme Edition Series, Intel® Core™ i7-800 and i7-

700 mobile processor series

AAT = Intel

Core™ i7-600, i5-500, i5-400 and i3-300 mobile processor series

AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor

G6950

Specification Update

Errata (Sheet 1 of 5)

Number

AAO1

AAO2

AAO3

AAO4

AAO5

AAO6

AAO7

AAO8

AAO9

AAO10

AAO11

AAO12

AAO13

AAO14

AAO15

AAO16

AAO17

AAO18

AAO19

AAO20

AAO21

AAO22

AAO23

AAO24

AAO25

AAO26

Steppings

B-1

Status ERRATA

XNo FixThe Processor May Report a #TS Instead of a #GP Fault

REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page

XNo Fix

Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations

XNo Fix

Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack

XNo FixPerformance Monitor SSE Retired Instructions May Return Incorrect Values

XNo FixPremature Execution of a Load Operation Prior to Exception Handler Invocation

XNo FixMOV To/From Debug Registers Causes Debug Exception

XNo Fix

Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update

XNo FixValues for LBR/BTS/BTM will be Incorrect after an Exit from SMM

XNo FixSingle Step Interrupts with Floating Point Exception Pending May Be Mishandled

XNo FixFault on ENTER Instruction May Result in Unexpected Values on Stack Frame

XNo Fix

IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception

General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted

General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit

LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode

XNo FixMONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang

XNo Fix

Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode

Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter may be Incorrect

XNo FixA VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed

XNo FixDelivery Status of the LINT0 Register of the Local Vector Table May be Lost

XNo FixPerformance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately

XNo Fix

#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code

Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction

An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/

XNo Fix

POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception

XNo FixIA32_MPERF Counter Stops Counting During On-Demand TM1

XNo Fix

The Memory Controller tTHROT_OPREF Timings May be Violated During Self Refresh Entry

XNo FixProcessor May Over Count Correctable Cache MESI State Errors

Specification Update

Errata (Sheet 2 of 5)

Number

AAO27

AAO28

AAO29

AAO30

AAO31

AAO32

AAO33

AAO34

AAO35

AAO36

AAO37

AAO38

AAO39

AAO40

AAO41

AAO42

AAO43

AAO44

AAO45

AAO46

AAO47

AAO48

AAO49

AAO50

AAO51

AAO52

AAO53

AAO54

Steppings

B-1

XNo Fix

Status ERRATA

Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work

Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio

XNo FixPECI Does Not Support PCI Configuration Reads/Writes to Misaligned Addresses

XNo FixOVER Bit for IA32_MCi_STATUS Register May Get Set on Specific lnternal Error

XNo Fix

Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt

XNo FixFaulting MMX Instruction May Incorrectly Update x87 FPU Tag Word

XNo Fix

xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode

Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures

XNo FixB0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set

XNo FixCore C6 May Clear Previously Logged TLB Errors

XNo FixPerformance Monitor Event MISALIGN_MEM_REF May Over Count

XNo Fix

Changing the Memory Type for an In-Use Page Translation May Lead to MemoryOrdering Violations

XNo FixRunning with Write Major Mode Disabled May Lead to a System Hang

XNo Fix

Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6

XNo FixTwo xAPIC Timer Event Interrupts May Unexpectedly Occur

XNo Fix

EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine

XNo FixFREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM

XNo FixAPIC Error “Received Illegal Vector” May be Lost

XNo Fix

DR6 May Contain Incorrect Information When the First Instruction After a MOV SS,r/ m or POP SS is a Store

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang

XNo FixIA32_PERF_GLOBAL_CTRL MSR May be Incorrectly Initialized

XNo FixECC Errors Can Not be Injected on Back-to-Back Writes

XNo Fix

Performance Monitor Interrupts Generated From Uncore Fixed Counters (394H) May be Ignored

Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected

Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand

XNo FixFaulting Executions of FXRSTOR May Update State Inconsistently

XNo Fix

Performance Monitor Event EPT.EPDPE_MISS May be Counted While EPT is Disable

XNo FixMemory Aliasing of Code Pages May Cause Unpredictable System Behavior

Specification Update

Errata (Sheet 3 of 5)

Number

AAO55

AAO56

AAO57

AAO58

AAO59

AAO60

AAO61

AAO62

AAO63

AAO64

AAO65

AAO66

AAO67

AAO68

AAO69

AAO70

AAO71

AAO72

AAO73

AAO74

AAO75

AAO76

AAO77

AAO78

AAO79

AAO80

AAO81

Steppings

B-1

Status ERRATA

XNo FixPerformance Monitor Counters May Count Incorrectly

XNo Fix

Processor Forward Progress Mechanism Interacting With Certain MSR/CSR Writes May Cause Unpredictable System Behavior

Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change

System May Hang if MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL Commands Are Not Issued in Increasing Populated DDR3 Rank Order

Package C3/C6 Transitions When Memory 2x Refresh is Enabled May Result in a System Hang

Back to Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS.MSCOD

XNo FixMemory Intensive Workloads with Core C6 Transitions May Cause System Hang

XNo Fix

Corrected Errors With a Yellow Error Indication May be Overwritten by Other Corrected Errors

XNo FixPSI# Signal May Incorrectly be Left Asserted

XNo Fix

Memory ECC Errors May be Observed When a UC Partial Write is Followed by a UC Read to the Same Location

Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount

XNo FixRapid Core C3/C6 Transitions May Cause Unpredictable System Behavior

XNo Fix

Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May Count Inaccurately

A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or PDPTE

XNo FixCPURESET Bit Does Not Get Cleared

XNo FixPHOLD Disable in MISCCTRLSTS Register Does Not Work

XNo Fix

PCIe PMCSR Power State Field Incorrectly Allows Requesting of the D1 and D2 Power States

PECI Accesses to Registers May Fail When Processor is Transitioning to/from Package C6 Power State

XNo FixConcurrent Updates to a Segment Descriptor May be Lost

XNo FixPMIs May be Lost During Core C6 Transitions

XNo Fix

Uncacheable Access to a Monitored Address Range May Prevent Future Triggering of the Monitor Hardware

BIST Results May be Additionally Reported After a GETSEC[WAKEUP] or INIT-SIPI Sequence

XNo FixPending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected

XNo FixVM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction

XNo FixMalformed PCIe Packet Generated Under Heavy Outbound Load

XNo FixPCIe Operation in x16 Mode With Inbound Posted Writes May be Unreliable

Specification Update

Errata (Sheet 4 of 5)

Number

AAO82

AAO83

AAO84

AAO85

AAO86

AAO87

AAO88

AAO89

AAO90

AAO91

AAO92

AAO93

AAO94

AAO95

AAO96

AAO97

AAO98

AAO99

AAO100

AAO101

AAO102

AAO103

AAO104

AAO105

AAO106

AAO107

AAO108

Steppings

B-1

Status ERRATA

XNo FixUnpredictable PCI Behavior Accessing Non-existent Memory Space

XNo Fix

PECI MbxGet() Commands May Fail Several Times Before Passing When Issued During Package C6

VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI Blocking

Intel® VT-d Receiving Two Identical Interrupt Requests May Corrupt Attributes of

XNo Fix

Remapped Interrupt or Hang a Subsequent Interrupt-Remap-Cache Invalidation Command

XNo FixS1 Entry May Cause Cores to Exit C3 or C6 C-State

XNo Fix

Multiple Performance Monitor Interrupts are Possible on Overflow of IA32_FIXED_CTR2

XNo FixLBRs May Not be Initialized During Power-On Reset of the Processor

XNo Fix

Unexpected Interrupts May Occur on C6 Exit If Using APIC Timer to Generate Interrupts

Package C6 Exit with Memory in Self-Refresh When Using DDR3 RDIMM Memory May Lead to a System Hang

LBR, BTM or BTS Records May have Incorrect Branch From Information After an EIST Transition, T-states, C1E, or Adaptive Thermal Throttling

XNo FixPECI GetTemp() Reads May Return Invalid Temperature Data in Package C6 State

XNo Fix

PECI PCIConfigRd() Followed by a GetTemp() May Cause System Hang in Package C6 State

PECI Mailbox Commands During Package C6 Idle State Transitions May Result in Unpredictable Processor Behavior

XNo FixVMX-Preemption Timer Does Not Count Down at the Rate Specified

XNo Fix

Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0

XNo FixSVID and SID of Devices 8 and 16 only implement bits [7:0]

XNo FixNo_Soft_Reset Bit in the PMCSR Does Not Operate as Expected

XNo FixVM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size

XNo Fix

PCIConfigRd() and PCIConfigWr() PECI Commands May Silently Fail During Package C6 Exit Events

Performance Monitoring Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA May Not Count Events Correctly

XNo FixStorage of PEBS Record Delayed Following Execution of MOV SS or STI

XNo Fix

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions

INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for a Large Page

XNo FixThe PECI Bus May be Tri-stated After System Reset

XNo FixLER MSRs May Be Unreliable

XNo FixMultiple ECC Errors May Result in Incorrect Syndrome Being Logged

XNo Fix

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

Specification Update

Errata (Sheet 5 of 5)

Number

AAO109

AAO110

AAO111

AAO112

AAO113

AAO114

AAO115

AAO116

AAO117

AAO118

AAO119

Steppings

B-1

Status ERRATA

XNo FixDebug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints

XNo FixAn Exit From the Core C6-state May Result in the Dropping of an Interrupt

XNo FixPCIe Extended Capability Structures May be Incorrect

XNo FixPMIs During Core C6 Transitions May Cause the System to Hang

XNo FixIA32_MC8_CTL2 MSR is Not Cleared on Processor Warm Reset

XNo FixThe TPM's Locality 1 Address Space Can Not be Opened

XNo Fix

The Combination of a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to Processor Livelock

PCIe Link Bit Errors Present During L0s Entry May Cause the System to Hang During L0s Exit

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode

IOTLB Invalidations Not Completing on Intel ® VT-d Engine for Integrated High Definition Audio

XNo FixIO_SMI Indication in SMRAM State Save Area May Be Lost

Specification Changes

Number SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

Specification Update

Identification Information

Component Identification via Programming Interface

The Intel Xeon processor 3400 series stepping can be identified by the following register contents:

Extended

Model

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

Note:

1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8],

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are

3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Tab le 1 for the processor

Extended

Family

00000000b 0001b 00b 0110 1110b xxxxb

to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,

or Intel

used to identify the model of the processor within the processor’s family.

processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor system).

register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

stepping ID number in the CPUID information.

Core™ processor family.

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID

value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The Intel Xeon processor 3400 series can be identified by the following register contents:

Stepping Vendor ID

B-1 8086h D130h 11h

Notes:

1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI

2. The Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in

3. The Revision Number corresponds to bits 7:0 of the Revis ion ID Regist er locat ed at off set 08h i n the PCI

function 0 configuration space.

the PCI function 0 configuration space.

function 0 configuration space.

Device ID

Revision ID

Specification Update

Component Marking Information

LOT NO S/N

The processor stepping can be identified by the following component markings.

Figure 1. Processor Production Top-side Markings (Example)

Table 1. Processor Identification (Sheet 1 of 2)

S-Spec

Number

Processor

Number

Stepping

Processor Signature

Core Frequency

(GHz) /

DDR3 (MHz)

SLBPT X3480 B-1 106E5h 3.06 / 1333

SLBJH X3470 B-1 106E5h 2.93 / 1333

SLBJK X3460 B-1 106E5h 2.80 / 1333

SLBLD X3450 B-1 106E5h 2.66 / 1333

SLBLF X3440 B-1 106E5h 2.53 / 1333

Max Intel®

Turbo Boost

Technology

Frequency

(GHz)

4 core: 3.33 3 core: 3.33 2 core: 3.60 1 core: 3.73

4 core: 3.20 3 core: 3.20 2 core: 3.46 1 core: 3.60

4 core: 2.93 3 core: 2.93 2 core: 3.33 1 core: 3.46

4 core: 2.80 3 core: 2.80 2 core: 3.20 1 core: 3.20

4 core: 2.66 3 core: 2.66 2 core: 2.80 1 core: 2.93

Shared

L3 Cache

Size (MB)

Notes

1, 3, 4,

5, 6

1, 3, 4,

5, 6

1, 3, 4,

5, 6

1, 3, 4,

5, 6

1, 3, 4,

5, 6

Specification Update

Table 1. Processor Identification (Sheet 2 of 2)

S-Spec

Number

Processor

Number

Stepping

Processor Signature

SLBLJ X3430 B-1 106E5h 2.40 / 1333

SLBN3 L3426 B-1 106E5h 1.86 / 1333

Notes:

1. This processor has TDP of 95W and meets the 1156_VR_CONF_09B VR Configuration.

2. This column indicates maximum Intel

3. Intel

4. Intel

5. Intel

6. Intel

7. This processor has TDP of 45 W.

8. The core frequency reported in the processor brand string is rounded to 2 decimal digits. (For example,

active respectively.

Hyper-Threading Technology enabled.

Trusted Execution Technology (Intel® TXT) enabled.

Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled.

Virtualization Technology for Directed I/O (Intel® VT-d) enabled.

core frequency of 3.4666, repeating 6, is reported as @3.47 in brand string. Core frequency of 3.3333, is reported as @3.33 in brand string.)

Core Frequency

Turbo Boost Technology frequency (GHz) for 4, 3, 2, or 1 cores

(GHz) /

DDR3 (MHz)

Max Intel®

Turbo Boost

Technology

Frequency

(GHz)

4 core: 2.53 3 core: 2.53 2 core: 2.66 1 core: 2.80

4 core: 2.13 3 core: 2.13 2 core: 3.06 1 core: 3.20

Shared

L3 Cache

Size (MB)

Notes

1, 4, 5,

3, 4, 5,

6, 7

Specification Update

Errata

AAO1. The Processor May Report a #TS Instead of a #GP Fault

Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)

instead of a #GP fault (general protection exception).

Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP

fault. Intel has not observed this erratum with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AAO2. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing

Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations

Problem: Under certain conditions as described in the Software Developers Manual section "Out-

of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data size or may observe memory ordering violations.

Implication: Upon crossing the page boundary the following may occur, dependent on the new page

memory type:

Workaround:

• UC the data size of each write will now always be 8 bytes, as opposed to the original data size.

• WP the data size of each write will now always be 8 bytes, as opposed to the original data size and there may be a memory ordering violation.

• WT there may be a memory ordering violation.

Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,

WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled.

Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update

+ 44 hidden pages

Intel BV80605001914AG - Processor - 1 x Xeon X3430, BX80605X3440 - Quad Core Xeon X3440, Xeon 3400 Series Specification

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® Xeon® Processor 3400 Series

Revision History

Preface

Affected Documents

Related Documents

Nomenclature

Summary Tables of Changes

Codes Used in Summary Tables

Stepping

Page

Status

Errata (Sheet 1 of 5)

Specification Changes

Specification Clarifications

Identification Information

Component Identification via Programming Interface

Component Marking Information

Errata