Intel BX80605I7870 - Core i7 2.93 GHz Processor, Core i7 Datasheet

Intel® Core™ i7 Processor Extreme Edition and Intel

Core™ i7

Processor

Datasheet, Volume 2

November 2008

Document Number: 320835-002

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Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.

Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor may contain design defects or errors known as

Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technologyenabled chipset, BIOS and operating system. Performance will va ry de pe ndi ng on the specific hardware and software y ou use. For more information including details on which processors support HT Technology, see

http://www.intel.com/products/ht/hyperthreading_more.htm

64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled

Intel

for Intel depending on your hardware and software configuration s. See www .intel.com/info/em64t for more information including details on which processors support Intel

± Intel for some uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on

64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary

Virtualization T echnology requires a compute r system with a processor, chipset, BIOS, virtual machine monitor (VMM) and

64 or consult with your system vendor for more information.

hardware and software configurations. Intel Virtualization Technology-enabled VMM applications are currently in development. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting

operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Enhanced Intel® SpeedStep Technology. See the Processor Spec Finder Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost

Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com

Intel, Xeon, Enhanced Intel SpeedStep Technology and the Intel logo are trademarks of Intel Corporation in the United States and other countries.

or contact your Intel representative for more information.

2 Datasheet

Contents

1Introduction............................................................................................................11

1.1 Terminology .....................................................................................................11

1.1.1 Processor Terminology ........................ .. .. ..............................................11

1.2 References.......................................................................................................13

2 Register Description ................................................................................................15

2.1 Register Terminology.........................................................................................15

2.2 Platform Configuration Structure .........................................................................16

2.3 Device Mapping................... .. ... ......................... .. ......................... .. ...................17

2.4 Detailed Configuration Space Maps......................................................................19

2.5 PCI Standard Registers ......................................................................................37

2.5.1 VID - Vendor Identification Register ........................................................37

2.5.2 DID - Device Identification Register.........................................................37

2.5.3 RID - Revision Identification Register.......................................................38

2.5.4 CCR - Class Code Register .....................................................................38

2.5.5 HDR - Header Type Register...................................................................39

2.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor

Identification Register ...........................................................................39

2.5.7 PCICMD - Command Register.................................................................40

2.5.8 PCISTS - PCI Status Register..................................................................41

2.6 SAD - System Address Decoder Registers.............................................................42

2.6.1 SAD_PAM0123 .....................................................................................42

2.6.2 SAD_PAM456.......................................................................................44

2.6.3 SAD_HEN ............................................................................................45

2.6.4 SAD_SMRAM........................................................................................45

2.6.5 SAD_PCIEXBAR....................................................................................46

2.6.6 SAD_DRAM_RULE_0, S AD_DRAM_RULE_1, SAD_DRAM_RULE_2,

2.6.7 SAD_INTERLEAVE_LIST_0, SAD_INTERLEAVE_LIST_1

2.7 Intel QPI Link Registers......................................................................................48

2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 ............................................................48

2.8 Integrated Memory Controller Control Registers ....................................................48

2.8.1 MC_CONTROL ......................................................................................48

2.8.2 MC_STATUS.........................................................................................50

2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS..................................................51

2.8.4 MC_SMI_SPARE_CNTRL.........................................................................52

2.8.5 MC_RESET_CONTROL............................................................................52

2.8.6 MC_CHANNEL_MAPPER..........................................................................53

2.8.7 MC_MAX_DOD......................................................................................54

2.8.8 MC_RD_CRDT_INIT...............................................................................55

2.8.9 MC_CRDT_WR_THLD.............................................................................56

2.8.10 MC_SCRUBADDR_LO.............................................................................56

2.8.11 MC_SCRUBADDR_HI.............................................................................57

2.9 TAD – Target Address Decoder Registers..............................................................58

2.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_1

SAD_DRAM_RULE_3 SAD_DRAM_RULE_4, SAD_DRAM_RULE_5

SAD_DRAM_RULE_6, SAD_DRAM_RULE_7 ...............................................46

SAD_INTERLEAVE_LIST_2, SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4, SAD_INTERLEAVE_LIST_5

SAD_INTERLEAVE_LIST_6, SAD_INTERLEAVE_LIST_7...............................47

TAD_DRAM_RULE_2, TAD_DRAM_RULE_3 TAD_DRAM_RULE_4, TAD_DRAM_RULE_5

TAD_DRAM_RULE_6, TAD_DRAM_RULE_7................................................58

Datasheet 3

2.9.2 TAD_INTERLEAVE_LIST_0, TAD _INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5

TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7................................59

2.10 Integrated Memory Controller Channel Control Registers.........................................60

2.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD

MC_CHANNEL_2_DIMM_RESET_CMD.......................................................60

2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD

MC_CHANNEL_2_DIMM_INIT_CMD..........................................................61

2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS

MC_CHANNEL_2_DIMM_INIT_PARAMS.....................................................62

2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS

MC_CHANNEL_2_DIMM_INIT_STATUS .....................................................63

2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD

MC_CHANNEL_2_DDR3CMD....................................................................64

2.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT

MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT......................................65

2.10.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1

MC_CHANNEL_2_MRS_VALUE_0_1..........................................................65

2.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2

MC_CHANNEL_2_MRS_VALUE_2 .............................................................66

2.10.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT

MC_CHANNEL_2_RANK_PRESENT............................................................66

2.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A

MC_CHANNEL_2_RANK_TIMING_A..........................................................67

2.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B

MC_CHANNEL_2_RANK_TIMING_B..........................................................70

2.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING

MC_CHANNEL_2_BANK_TIMING..............................................................71

2.10.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING

MC_CHANNEL_2_REFRESH_TIMING.........................................................71

2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING

MC_CHANNEL_2_CKE_TIMING................................................................72

2.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING

MC_CHANNEL_2_ZQ_TIMING .................................................................72

2.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS

MC_CHANNEL_2_RCOMP_PARAMS...........................................................73

2.10.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1

MC_CHANNEL_2_ODT_PARAMS1.............................................................73

2.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2

MC_CHANNEL_2_ODT_PARAMS2.............................................................74

4 Datasheet

2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD

MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD......................................... 74

2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD

MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD......................................... 75

2.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR

MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR........................................ 75

2.10.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR

MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR........................................ 75

2.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS

MC_CHANNEL_2_WAQ_PARAMS .............................................................76

2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS

MC_CHANNEL_2_SCHEDULER_PARAMS ...................................................77

2.10.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS

MC_CHANNEL_2_MAINTENANCE_OPS .....................................................77

2.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS

MC_CHANNEL_2_TX_BG_SETTINGS........................................................78

2.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS

MC_CHANNEL_2_RX_BGF_SETTINGS......................................................78

2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS

MC_CHANNEL_2_EW_BGF_SETTINGS......................................................79

2.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS

MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS.........................................79

2.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY

MC_CHANNEL_2_ROUND_TRIP_LATENCY.................................................79

2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1

MC_CHANNEL_2_PAGETABLE_PARAMS1 ..................................................80

2.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS2

MC_CHANNEL_2_PAGETABLE_PARAMS2 ..................................................80

2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1

MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2.......................................81

2.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1

MC_TX_BG_CMD_OFFSET_SETTINGS_CH2...............................................81

2.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1

MC_TX_BG_DATA_OFFSET_SETTINGS_CH2 .............................................81

2.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH

MC_CHANNEL_2_ADDR_MATCH..............................................................82

2.10.37 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK

MC_CHANNEL_2_ECC_ERROR_MASK.......................................................83

2.10.38 MC_CHANNEL_0_ECC_ERROR_INJECT MC_CHANNEL_1_ECC_ERROR_INJECT

MC_CHANNEL_2_ECC_ERROR_INJECT.....................................................83

Datasheet 5

2.10.39 Error Injection Implementation...............................................................84

2.11 Integrated Memory Controller Channel Address Registers........................................85

2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2 ................................85

2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2 ................................86

2.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2 ................................87

2.11.4 MC_SAG_CH0_0, MC_SAG _CH0_1, MC_SAG_CH0_2 MC_SAG_CH0_3, MC_SAG_CH0_4, MC_SAG_CH0_5 MC_SAG_CH0_6, MC_SAG_CH0_7, MC_SAG_CH1_0 MC_SAG_CH1_1, MC_SAG_CH1_2, MC_SAG_CH1_3 MC_SAG_CH1_4, MC_SAG_CH1_5, MC_SAG_CH1_6 MC_SAG_CH1_7, MC_SAG_CH2_0, MC_SAG_CH2_1 MC_SAG_CH2_2, MC_SAG_CH2_3, MC_SAG_CH2_4

MC_SAG_CH2_5, MC_SAG_CH2 _ 6, MC_ S AG_ C H 2_ 7..................................88

2.12 Integrated Memory Controller Channel Rank Registers............................................89

2.12.1 MC_RIR_LIMIT_CH0_0, MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2, MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4, MC_RIR_LIMIT_CH0_5 MC_RIR_LIMIT_CH0_6, MC_RIR_LIMIT_CH0_7 MC_RIR_LIMIT_CH1_0, MC_RIR_LIMIT_CH1_1 MC_RIR_LIMIT_CH1_2, MC_RIR_LIMIT_CH1_3 MC_RIR_LIMIT_CH1_4, MC_RIR_LIMIT_CH1_5 MC_RIR_LIMIT_CH1_6, MC_RIR_LIMIT_CH1_7 MC_RIR_LIMIT_CH2_0, MC_RIR_LIMIT_CH2_1 MC_RIR_LIMIT_CH2_2, MC_RIR_LIMIT_CH2_3 MC_RIR_LIMIT_CH2_4, MC_RIR_LIMIT_CH2_5

MC_RIR_LIMIT_CH2_6, MC_RIR_LIMIT_CH2_7 .........................................89

2.12.2 MC_RIR_WAY_CH0_0, MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2, MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4, MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6, MC_RIR_WAY_CH0_7 MC_RIR_WAY_CH0_8, MC_RIR_WAY_CH0_9 MC_RIR_WAY_CH0_10, MC_RIR_WAY_CH0_11 MC_RIR_WAY_CH0_12, MC_RIR_WAY_CH0_13 MC_RIR_WAY_CH0_14, MC_RIR_WAY_CH0_15 MC_RIR_WAY_CH0_16, MC_RIR_WAY_CH0_17 MC_RIR_WAY_CH0_18, MC_RIR_WAY_CH0_19 MC_RIR_WAY_CH0_20, MC_RIR_WAY_CH0_21 MC_RIR_WAY_CH0_22, MC_RIR_WAY_CH0_23 MC_RIR_WAY_CH0_24, MC_RIR_WAY_CH0_25 MC_RIR_WAY_CH0_26, MC_RIR_WAY_CH0_27 MC_RIR_WAY_CH0_28, MC_RIR_WAY_CH0_29

MC_RIR_WAY_CH0_30, MC_RIR_WAY_CH0_31.........................................90

2.12.3 MC_RIR_WAY_CH1_0, MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2, MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4, MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6, MC_RIR_WAY_CH1_7 MC_RIR_WAY_CH1_8, MC_RIR_WAY_CH1_9 MC_RIR_WAY_CH1_10, MC_RIR_WAY_CH1_11 MC_RIR_WAY_CH1_12, MC_RIR_WAY_CH1_13 MC_RIR_WAY_CH1_14, MC_RIR_WAY_CH1_15 MC_RIR_WAY_CH1_16, MC_RIR_WAY_CH1_17 MC_RIR_WAY_CH1_18, MC_RIR_WAY_CH1_19 MC_RIR_WAY_CH1_20, MC_RIR_WAY_CH1_21 MC_RIR_WAY_CH1_22, MC_RIR_WAY_CH1_23 MC_RIR_WAY_CH1_24, MC_RIR_WAY_CH1_25 MC_RIR_WAY_CH1_26, MC_RIR_WAY_CH1_27 MC_RIR_WAY_CH1_28, MC_RIR_WAY_CH1_29

MC_RIR_WAY_CH1_30, MC_RIR_WAY_CH1_31.........................................91

2.12.4 MC_RIR_WAY_CH2_0, MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2, MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4, MC_RIR_WAY_CH2_5

6 Datasheet

MC_RIR_WAY_CH2_6, MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8, MC_RIR_WAY_CH2_9 MC_RIR_WAY_CH2_10, MC_RIR_WAY_CH2_11 MC_RIR_WAY_CH2_12, MC_RIR_WAY_CH2_13 MC_RIR_WAY_CH2_14, MC_RIR_WAY_CH2_15 MC_RIR_WAY_CH2_16, MC_RIR_WAY_CH2_17 MC_RIR_WAY_CH2_18, MC_RIR_WAY_CH2_19 MC_RIR_WAY_CH2_20, MC_RIR_WAY_CH2_21 MC_RIR_WAY_CH2_22, MC_RIR_WAY_CH2_23 MC_RIR_WAY_CH2_24, MC_RIR_WAY_CH2_25 MC_RIR_WAY_CH2_26, MC_RIR_WAY_CH2_27 MC_RIR_WAY_CH2_28, MC_RIR_WAY_CH2_29

MC_RIR_WAY_CH2_30, MC_R IR_ W AY_ CH2_31 ........................................92

2.13 Memory Thermal Control................................................... .. .. .. ...........................93

2.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1

MC_THERMAL_CONTROL2......................................................................93

2.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1

MC_THERMAL_STATUS2........................................................................93

2.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1

MC_THERMAL_DEFEATURE2...................................................................94

2.13.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1

MC_THERMAL_PARAMS_A2....................................................................94

2.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1

MC_THERMAL_PARAMS_B2....................................................................95

2.13.6 MC_COOLING_COEF0 MC_COOLING_COEF1

MC_COOLING_COEF2............................................................................95

2.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1

MC_CLOSED_LOOP2 .............................................................................96

2.13.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1

MC_THROTTLE_OFFSET2.......................................................................96

2.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1

MC_RANK_VIRTUAL_TEMP2 ...................................................................97

2.13.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1

MC_DDR_THERM_COMMAND2................................................................97

2.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1

MC_DDR_THERM_STATUS2....................................................................98

2.14 Integrated Memory Controller Miscellaneous Registers............................................98

2.14.1 MC_DIMM_CLK_RATIO_STATUS .............................................................98

2.14.2 MC_DIMM_CLK_RATIO ..........................................................................99

Datasheet 7

Tables

1-1 References........................................................................................................13

2-1 Functions Specifically Handled by the Processor.....................................................18

2-2 Device 0, Function 0: Generic Non-core Registers ..................................................19

2-3 Device 0, Function 1: System Address Decoder Registers........................................20

2-4 Device 2, Function 0: Intel QPI Link 0 Registers.....................................................21

2-5 Device 2, Function 1: Intel QPI Physical 0 Registers ...............................................22

2-6 Device 3, Function 0: Integrated Memory Controller Registers ....... ..........................23

2-7 Device 3, Function 1: Target Address Decoder Registers .........................................24

2-8 Device 4, Function 0: Integrated Memory Controller Channel 0

Control Registers..................... ... ......................... .. .. ......................... .. ... ............25

2-9 Device 4, Function 1: Integrated Memory Controller Channel 0

Address Registers..............................................................................................26

2-10 Device 4, Function 2: Integrated Memory Controller Channel 0

Rank Registers..................................................................................................27

2-11 Device 4, Function 3: Integrated Memory Controller Channel 0

Thermal Control Registers............................................. .. ............................ ........28

2-12 Device 5, Function 0: Integrated Memory Controller Channel 1

Control Registers..................... ... ......................... .. .. ......................... .. ... ............29

2-13 Device 5, Function 1: Integrated Memory Controller Channel 1

Address Registers..............................................................................................30

2-14 Device 5, Function 2: Integrated Memory Controller Channel 1

Rank Registers..................................................................................................31

2-15 Device 5, Function 3: Integrated Memory Controller Channel 1

Thermal Control Registers............................................. .. ............................ ........32

2-16 Device 6, Function 0: Integrated Memory Controller Channel 2

Control Registers..................... ... ......................... .. .. ......................... .. ... ............33

2-17 Device 6, Function 1: Integrated Memory Controller Channel 2

Address Registers..............................................................................................34

2-18 Device 6, Function 2: Integrated Memory Controller Channel 2

Rank Registers..................................................................................................35

2-19 Device 6, Function 3: Integrated Memory Controller Channel 2

Thermal Control Registers............................................. .. ............................ ........36

8 Datasheet

Revision History

Revision

Number

-001 Initial release. November 2008

-002 Updated section 2.2 and Table 2.3. November 2008

Description Date

Datasheet 9

10 Datasheet

Introduction

1 Introduction

The Intel® Core™ i7 processor Extreme Edition and Intel® Core™ i7 processor are intended for high performance high-end desktop, Uni-processor (UP) server, and workstation systems. The processor implements key new technologies:

• Integrated Memory Controller

• Point-to-point link interface based on Intel® QuickPath Interconnect (Intel® QPI). Reference to this interface may sometimes be abbreviated with Intel QPI throughout this document.

Note: In this document the Intel

processor will be referred to as “the processor.” This datasheet provides register descriptions for some of the registers located on the

processor. The processor is optimized for performance with the power efficiencies of a low-power

microarchitecture to enable smaller, quieter systems.

The Intel multi-core processors, based on 45 nm process technology. Processor features vary by component and include up to two Intel QuickPath Interconnect point to point links capable of up to 6.4 GT/s, up to 8 MB of shared cache, and an integrated memory controller. The processors support all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced Technologies: Execute Disable Bit, Intel Technology (Intel® VT), Intel® Turbo Boost Technology, and Hyper-Threading Technology.

Core™ i7 processor Extreme Edition and Intel® Core™ i7 processor are

64 Technology, Enhanced Intel SpeedStep® Technology, Intel® Virtualization

Core™ i7 processor Extreme Edition and Intel® Core™ i7

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested.

1.1.1 Processor Terminology

Commonly used terms are explained here for clarification:

• DDR3 — Double Data Rate 3 synchronous dynamic random access memory (SDRAM) is the name of the new DDR memory standard that is being developed as the successor to DDR2 SDRAM.

• Enhanced Intel SpeedStep® Technology — Enhanced Intel SpeedStep Technology allows trade-offs to be made between performance and power consumption.

• Execute Disable Bit — Execute Disable allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel Architecture Software Developer's Manual for

Datasheet 11

Introduction

more detailed information. Refer to http://developer.intel.com/ for future reference on up to date nomenclatures.

• Eye Definitions — The eye at any point along the data channel is defined to be the creation of overlapping of a large number of Unit Interval of the data signal and timing width measured with respect to the edges of a separate clock signal at any other point. Each differential signal pair by combining the D+ and D- signals produces a signal eye.

• 1366-land LGA package — The processor is available in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of the processor die mounted on a land grid array substrate with an integrated heat spreader (IHS).

• Functional Operation — Refers to the normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied.

• Integrated Memory Controller (IMC) — A memory controller that is integrated in the processor silicon.

• Integrated Heat Spreader (IHS) — A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

• Intel

64 Architecture — An enhancement to Intel's IA-32 architec ture, allowing

the processor to execute operating systems and applications written to take advantage of Intel 64. Further details on Intel 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/.

• Intel

QuickPath Interconnect – A cache-coherent, link-based interconnect

specification for Intel processor, chipset, and I/O bridge components. Sometimes abbreviated as Intel QPI.

• Intel® QPI — Abbreviation for Intel® QuickPath Interconnect.

• Intel® Virtualization Technology (Intel® VT) — A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions. Intel VT provides a foundation for widely-deployed virtualization solutions and enables more robust hardware assisted virtualization solutions. More information can be found at: http://www.intel.com/technology/virtualization/

• Jitter — Any timing variation of a transition edge or edges from the defined Unit Interval.

• LGA136 6 Socket — The processor (in the LGA-1366 package) mates with the system board through this surface mount, 1366-contact socket.

• Mirror Port - Pads located on the top side of the processor package used to provide logic analyzer probing access for Intel QPI signal analysis.

• Non-core — The portion of the processor comprising the shared cache, IMC and Intel QPI Link interface.

• OEM — Original Equipment Manufacturer.

• Storage Conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray , or loose. Processors ma y be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks.

• Intel

Core™ i7 processor Extreme Edition and Intel® Core™ i7 processor

— The desktop product, including processor substrate and integrated heat spreader (IHS).

12 Datasheet

Introduction

• Unit Interval (UI) — Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances

, t2, tn,...., tk then the UI at instance “n” is defined as:

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.

Table 1-1. References

Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor

Intel Specification Update

Intel® Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor Datasheet, Volume 1

Intel® Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor and LGA1366 Socket Thermal and Mechanical Design Guide

Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual

• Volume 1: Basic Architecture

• Volume 2A: Instruction Set Reference, A-M

• Volume 2B: Instruction Set Reference, N-Z

• Volume 3A: System Programming Guide, Part 1

• Volume 3B: Systems Programming Guide, Part 2

UI n = t n - t

Document Location

n - 1

http://download.intel.com

/design/processor/specup

dt/320836.pdf

http://download.intel.com /design/processor/datasht

s/320834.pdf

http://download.intel.com /design/processor/designe

x/320837.pdf

http://www.intel.com/pro

ducts/processor/manuals/

Datasheet 13

Introduction

14 Datasheet

2 Register Description

The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification, Revision 2.3, as well as the PCI Express* enhanced configuration mechanism as specified in the PCI Express Base Specification, Revision 1.1. All the registers are organized by bus, device, function, etc. as defined in the PCI Express Base Specification, Revision 1.1. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number. All multi-byte numeric fields use “little-endian” ordering (i.e., lower addresses contain the least significant parts of the field).

As processor features vary by component, not all of the register descriptions in this document apply to all processors. This document highlights registers which do not apply to all processor components. Refer to the particular processor's Specification Update for a list of features supported.

2.1 Register Terminology

Registers and register bits are assigned one or more of the following attributes. These attributes define the behavior of register and the bit(s) that are contained with in. All bits are set to default values by hard reset. Sticky bits retain their states between hard

resets.

Term Description

WO RW

RCW

RW1C

RW0C

RW1S

RW0S

RWL

RWO

RRW

Read Only. If a register bit is read on ly, the hardware sets its state. The bit may be read by software. Writes to this bit have no effect.

Write Only. The register bit is not implemented as a bit. The write causes some hardware event to take place.

Read/Write. A register bit with this attribute can be read and written by software. Read Clear: The bit or bits can be read by software, but the act of reading causes the

value to be cleared. Read Clear/Write: A register bit with this attribute will get cleared after the read. The

In order to clear this bit, a one must be written to it. Writing a zero will have no effect. Read/Write 0 Clear. A register bit with this attribute can be read or cleared by software.

In order to clear this bit, a zero must be written to it. Writing a one will have no effect. Read/Write 1 Set: A register bit can be either read or set by software. In order to set

this bit, a one must be written to it. Writing a zero to this bit has no effect. Hardware will clear this bit.

Read/Write 0 Set: A register bit can be either read or set by software. In order to set this bit, a zero must be written to it. Writing a one to this bit has no effect. Hardware will clear this bit.

Read/Write/Lock. A register bit with this attribute can be read or written by software. Hardware or a configuration bit can lock the bit and prevent it from being updated.

Read/Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. This attribute is applied on a bit by bit basis. For example, if the RWO attribute is applied to a 2 bit field, and only one bit is written, then the written bit cannot be rewritten (unless reset). The unwritten bit, of the field, may still be written once. This is special case of RWL.

Read/Restricted Write. This bit can be read and written by software. However, only supported values will be written. Writes of non supported values will have no effect.

Lock. A register bit with this attribute becomes Read Only after a lock bit is set.

Datasheet 15

Term Description

Reserved Bit. This bit is reserved for future expansion and must not be writte n. The PCI

RSVD

Reserved Bits

Reserved Registers

Default Value upon a Reset

“ST” appended to the end of a

Local Bus Specification, Revision 2.2 requires that reserved bits must be preserved. Any software that modifies a register that contains a reserved bit is res ponsible for reading the register, modifying the desired bits, and writing back the result.

Some of the processor registers described in this section cont ain reserv ed bits. The se bits are labeled “Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, softw are must ens ure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note that software does not need to perform a read-merge-write operation for the Configuration Address (CONFIG_ADDRESS) register.

In addition to reserved bits within a register, the processor contains address locations in the configuration space that are marked either “Reserved” or “Intel Reserved”. The processor responds to accesses to “Reserved” address locations by completing the host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8, 16, or 32 bits in size). Writes to “R eser ved” register s have no effec t on the processor. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure . Reads to “Intel Reserved” registers may return a non-zero value.

Upon a reset, the processor sets all of its internal configuration register s to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the processor registers accordingly.

The bit is “sticky” or unchanged by a hard reset. These bits can only be cleared by a PWRGOOD reset.

bit name

2.2 Platform Configuration Structure

The processor contains 6 PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number.

• Device 0: Generic processor non-core. Device 0, Function 0 contains the generic non-core configuration registers for the processor and resides at DID (Device ID) of 2C41h. Device 0, Function 1 contains the System Address Decode registers and resides at DID of 2C01h.

• Device 2: Intel QPI. Device 2, Function 0 contains the Intel Interconnect configuration registers for Intel QPI Link 0 and resides at DID of 2C10h. Device 2, Function 1 contains the physical layer registers for Intel QPI Link 0 and resides at DID of 2C11h.

• Device 3: Integrated Memory Controller . Device 3, Function 0 contains the general registers for the Integrated Memory Controller and resides at DID of 2C18h. Device 3, Function 1 contains the Target Address Decode registers for the Integrated Memory Controller and resides at DID of 2C19h. Device 3, Function 2 contains the RAS registers for the Integrated Memory Controller and resides at DID of 2C1Ah. Device 3, Function 4 contains the test registers for the Integrated Memory Controller and resides at DID of 2C1Ch. Function 2 only applies to processors supporting registered DIMMs.

• Device 4: Integrated Memory Controller Channel 0. Device 4, Function 0 contains the control registers for Integrated Memory Controller Channel 0 and resides at DID of 2C20h. Device 4, Function 1 contains the address registers for Integrated Memory Controller Channel 0 and resides at DID of 2C21h. Device 4, Function 2 contains the rank registers for Integrated Memory Controller Channel 0 and resides

QuickPath

16 Datasheet

at DID of 2C22h. Device 4, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2C23h.

• Device 5: Integrated Memory Controller Channel 1. Device 5, Function 0 contains the control registers for Integrated Memory Controller Channel 1 and resides at DID of 2C28h. Device 5, Function 1 contains the address registers for Integrated Memory Controller Channel 1 and resides at DID of 2C29h. Device 5, Function 2 contains the rank registers for Integrated Memory Controller Channel 1 and resides at DID of 2C2Ah. Device 5, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 1 and resides at DID of 2C2Bh.

• Device 6: Integrated Memory Controller Channel 2. Device 6, Function 0 contains the control registers for Integrated Memory Controller Channel 2 and resides at DID of 2C30h. Device 6, Function 1 contains the address registers for Integrated Memory Controller Channel 2 and resides at DID of 2C31h. Device 6, Function 2 contains the rank registers for Integrated Memory Controller Channel 2 and resides at DID of 2C32h. Device 6, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 2 and resides at DID of 2C33h.

2.3 Device Mapping

Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number, Device Number , and Function Number. Device configuration is based on the PCI T ype 0 configur ation conventions. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number.

Table 2-1. Functions Specifically Handled by the Processor

Component Register Group DID Device Function

Intel QuickPath Architecture Generic Non-core Registers Intel QuickPath Architect ure System Address Decoder Intel QPI Link 0 Intel QPI Physical 0 Integrated Memory Controller Registers Integrated Memory Controller Target Address Decoder Integrated Memory Controller RAS Registers Integrated Memory Controller Test Registers Integrated Memory Controller Channel 0 Control

Processor

Integrated Memory Controller Channel 0 Address Integrated Memory Controller Channel 0 Rank Integrated Memory Controller Channel 0 Thermal Control Integrated Memory Controller Channel 1 Control Integrated Memory Controller Channel 1 Address Integrated Memory Controller Channel 1 Rank Integrated Memory Controller Channel 1 Thermal Control Integrated Memory Controller Channel 2 Control Integrated Memory Controller Channel 2 Address Integrated Memory Controller Channel 2 Rank Integrated Memory Controller Channel 2 Thermal Control

2C41h 2C01h 1 2C10h

2C11 1 2C18h 2C19h 1 2C1Ah 2 2C1Ch 4 2C20h 2C21h 1 2C22h 2 2C23h 3 2C28h 2C29h 1 2C2Ah 2 2C2Bh 3 2C30h 2C31h 1 2C32h 2 2C33h 3

Notes:

1. Applies only to processors supporting sparing, mirroring, and scrubbing RAS features.

Datasheet 17

2.4 Detailed Configuration Space Maps

Table 2-2. Device 0, Function 0: Generic Non-core Registers

DID VID 00h 80h

PCISTS PCICMD 04h

CCR RID 08h HDR 0Ch 8Ch

10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh

84h 88h

ACh

18 Datasheet

Table 2-3. Device 0, Function 1: System Address Decoder Registers

DID VID 00h SAD_DRAM_RULE_0 80h

PCISTS PCICMD 04h SAD_DRAM_RULE_1 84h

CCR RID 08h SAD_DRAM_RULE_2 88h HDR 0Ch SAD_DRAM_RULE_3 8Ch

10h SAD_DRAM_RULE_4 90h 14h SAD_DRAM_RULE_5 94h 18h SAD_DRAM_RULE_6 98h 1Ch SAD_DRAM_RULE_7 9Ch 20h A0h 24h A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh

SAD_PAM0123 40h SAD_INTERLEAVE_LIST_0 C0h

SAD_PAM456 44h SAD_INTERLEAVE_LIST_1 C4h

SAD_HEN 48h SAD_INTERLEAVE_LIST_2 C8h

SAD_SMRAM 4Ch SAD_INTERLEAVE_LIST_3 CCh

SAD_PCIEXBAR 50h SAD_INTERLEAVE_LIST_4 D0h

54h SAD_INTERLEAVE_LIST_5 D4h 58h SAD_INTERLEAVE_LIST_6 D8h 5Ch SAD_INTERLEAVE_LIST_7 DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh

ACh

Datasheet 19

Table 2-4. Device 2, Function 0: Intel QPI Link 0 Registers

DID VID 00h 80h

PCISTS PCICMD 04h

CCR RID 08h HDR 0Ch 8Ch

10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h

QPI_QPILCL_L0 48h C8h

4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh

84h 88h

ACh

20 Datasheet

Table 2-5. Device 2, Function 1: Intel QPI Physical 0 Registers

DID VID 00h 80h

PCISTS PCICMD 04h

CCR RID 08h HDR 0Ch 8Ch

10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh

84h 88h

ACh

Datasheet 21

Table 2-6. Device 3, Function 0: Integrated Memory Controller Registers

DID VID 00h 80h

PCISTS PCICMD 04h

CCR RID 08h HDR 0Ch 8Ch

10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h

MC_CONTROL 48h

MC_STATUS 4Ch

MC_SMI_SPARE_DIMM_ERROR_STATUS 50h

MC_SMI_SPARE_CNTRL 54h

58h D8h

MC_RESET_CONTROL 5Ch

MC_CHANNEL_MAPPER 60h

MC_MAX_DOD 64h

68h E8h 6Ch ECh

MC_RD_CRDT_INIT 70h MC_CRDT_WR_THLD 74h MC_SCRUBADDR_LO 78h MC_SCRUBADDR_HI 7Ch

84h 88h

ACh

C8h CCh D0h D4h

DCh

E0h E4h

F0h F4h F8h FCh

22 Datasheet

Table 2-7. Device 3, Function 1: Target Address Decoder Registers

DID VID 00h TAD_DRAM_RULE_0 80h

PCISTS PCICMD 04h TAD_DRAM_RULE_1 84h

CCR RID 08h TAD_DRAM_RULE_2 88h HDR 0Ch TAD_DRAM_RULE_3 8Ch

10h TAD_DRAM_RULE_4 90h 14h TAD_DRAM_RULE_5 94h 18h TAD_DRAM_RULE_6 98h 1Ch TAD_DRAM_RULE_7 9Ch 20h A0h 24h A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh 40h TAD_INTERLEAVE_LIST_0 C0h 44h TAD_INTERLEAVE_LIST_1 C4h 48h TAD_INTERLEAVE_LIST_2 C8h 4Ch TAD_INTERLEAVE_LIST_3 CCh 50h TAD_INTERLEAVE_LIST_4 D0h 54h TAD_INTERLEAVE_LIST_5 D4h 58h TAD_INTERLEAVE_LIST_6 D8h 5Ch TAD_INTERLEAVE_LIST_7 DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh

ACh

Datasheet 23

Table 2-8. Device 4, Function 0: Integrated Memory Controller Channel 0

Control Registers

DID VID 00h MC_CHANNEL_0_RANK_TIMING_A 80h

PCISTS PCICMD 04h MC_CHANNEL_0_RANK_TIMING_B 84h

CCR RID 08h MC_CHANNEL_0_BANK_TIMING 88h HDR 0Ch MC_CHANNEL_0_REFRESH_TIMING 8Ch

10h MC_CHANNEL_0_CKE_TIMING 90h 14h MC_CHANNEL_0_ZQ_TIMING 94h 18h MC_CHANNEL_0_RCOMP_PARAMS 98h 1Ch MC_CHANNEL_0_ODT_PARAMS1 9Ch 20h MC_CHANNEL_0_ODT_PARAMS2 A0h 24h MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD A4h 28h MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD A8h

SID SVID 2Ch MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR ACh

30h MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR B0h 34h MC_CHANNEL_0_WAQ_PARAMS B4h 38h MC_CHANNEL_0_SCHEDULER_PARAMS B8h 3Ch MC_CHANNEL_0_MAINTENANCE_OPS BCh 40h MC_CHANNEL_0_TX_BG_SETTINGS C0h 44h C4h 48h MC_CHANNEL_0_RX_BGF_SETTINGS C8h 4Ch MC_CHANNEL_0_EW_BGF_SETTINGS CCh

MC_CHANNEL_0_DIMM_RESET_CMD 50h MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS D0h

MC_CHANNEL_0_DIMM_INIT_CMD 54h MC_CHANNEL_0_ROUND_TRIP_LATENCY D4h

MC_CHANNEL_0_DIMM_INIT_PARAMS 58h MC_CHANNEL_0_PAGETABLE_PARAMS1 D8h

MC_CHANNEL_0_DIMM_INIT_STATUS 5Ch MC_CHANNEL_0_PAGETABLE_PARAMS2 DCh

MC_CHANNEL_0_DDR3CMD 60h MC_TX_BG_CMD_DATA_RATIO_SETTING_CH0 E0h

64h MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 E4h

MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT 68h MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 E8h

6Ch ECh

MC_CHANNEL_0_MRS_VALUE_0_1 70h MC_CHANNEL_0_ADDR_MATCH F0h

MC_CHANNEL_0_MRS_VALUE_2 74h F4h

78h MC_CHANNEL_0_ECC_ERROR_MASK F8h

MC_CHANNEL_0_RANK_PRESENT 7Ch MC_CHANNEL_0_ECC_ERROR_INJECT FCh

24 Datasheet

Table 2-9. Devic e 4, Function 1: Integrated Memory Controller Channel 0

Address Registers

DID VID 00h MC_SAG_CH0_0 80h

PCISTS PCICMD 04h MC_SAG_CH0_1 84h

CCR RID 08h MC_SAG_CH0_2 88h HDR 0Ch MC_SAG_CH0_3 8Ch

10h MC_SAG_CH0_4 90h 14h MC_SAG_CH0_5 94h 18h MC_SAG_CH0_6 98h 1Ch MC_SAG_CH0_7 9Ch 20h A0h 24h A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h

44h C4h MC_DOD_CH0_0 48h MC_DOD_CH0_1 4Ch MC_DOD_CH0_2 50h

54h D4h

58h D8h

5Ch DCh

60h E0h

64h E4h

68h E8h

6Ch ECh

70h F0h

74h F4h

78h F8h

7Ch FCh

ACh

C8h CCh D0h

Datasheet 25

Table 2-10. Device 4, Function 2: Integrated Memory Controller Channel 0

Rank Registers

DID VID 00h MC_RIR_WAY_CH0_0 80h

PCISTS PCICMD 04h MC_RIR_WAY_CH0_1 84h

CCR RID 08h MC_RIR_WAY_CH0_2 88h HDR 0Ch MC_RIR_WAY_CH0_3 8Ch

10h MC_RIR_WAY_CH0_4 90h 14h MC_RIR_WAY_CH0_5 94h 18h MC_RIR_WAY_CH0_6 98h 1Ch MC_RIR_WAY_CH0_7 9Ch 20h MC_RIR_WAY_CH0_8 A0h 24h MC_RIR_WAY_CH0_9 A4h 28h MC_RIR_WAY_CH0_10 A8h

SID SVID 2Ch MC_RIR_WAY_CH0_11 ACh

30h MC_RIR_WAY_CH0_12 B0h 34h MC_RIR_WAY_CH0_13 B4h 38h MC_RIR_WAY_CH0_14 B8h

3Ch MC_RIR_WAY_CH0_15 BCh MC_RIR_LIMIT_CH0_0 40h MC_RIR_WAY_CH0_16 C0h MC_RIR_LIMIT_CH0_1 44h MC_RIR_WAY_CH0_17 C4h MC_RIR_LIMIT_CH0_2 48h MC_RIR_WAY_CH0_18 C8h MC_RIR_LIMIT_CH0_3 4Ch MC_RIR_WAY_CH0_19 CCh MC_RIR_LIMIT_CH0_4 50h MC_RIR_WAY_CH0_20 D0h MC_RIR_LIMIT_CH0_5 54h MC_RIR_WAY_CH0_21 D4h MC_RIR_LIMIT_CH0_6 58h MC_RIR_WAY_CH0_22 D8h MC_RIR_LIMIT_CH0_7 5Ch MC_RIR_WAY_CH0_23 DCh

60h MC_RIR_WAY_CH0_24 E0h

64h MC_RIR_WAY_CH0_25 E4h

68h MC_RIR_WAY_CH0_26 E8h

6Ch MC_RIR_WAY_CH0_27 ECh

70h MC_RIR_WAY_CH0_28 F0h

74h MC_RIR_WAY_CH0_29 F4h

78h MC_RIR_WAY_CH0_30 F8h

7Ch MC_RIR_WAY_CH0_31 FCh

26 Datasheet

Table 2-11. Device 4, Function 3: Integrated Memory Controller Channel 0

Thermal Control Registers

DID VID 00h MC_COOLING_COEF0 80h

PCISTS PCICMD 04h MC_CLOSED_LOOP0 84h

CCR RID 08h MC_THROTTLE_OFFSET0 88h HDR 0Ch 8Ch

10h 90h 14h 94h 18h MC_RANK_VIRTUAL_TEMP0 98h 1Ch MC_DDR_THERM_COMMAND0 9Ch 20h A0h 24h MC_DDR_THERM_STATUS0 A4h 28h A8h

SID SVID 2Ch

30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h

MC_THERMAL_CONTROL0 48h

MC_THERMAL_STATUS0 4Ch

MC_THERMAL_DEFEATURE0 50h

54h D4h 58h D8h

5Ch DCh MC_THERMAL_PARAMS_A0 60h MC_THERMAL_PARAMS_B0 64h

68h E8h

6Ch ECh

70h F0h

74h F4h

78h F8h

7Ch FCh

ACh

C8h CCh D0h

E0h E4h

Datasheet 27

Table 2-12. Device 5, Function 0: Integrated Memory Controller Channel 1

Control Registers

DID VID 00h MC_CHANNEL_1_RANK_TIMING_A 80h

PCISTS PCICMD 04h MC_CHANNEL_1_RANK_TIMING_B 84h

CCR RID 08h MC_CHANNEL_1_BANK_TIMING 88h HDR 0Ch MC_CHANNEL_1_REFRESH_TIMING 8Ch

10h MC_CHANNEL_1_CKE_TIMING 90h 14h MC_CHANNEL_1_ZQ_TIMING 94h 18h MC_CHANNEL_1_RCOMP_PARAMS 98h 1Ch MC_CHANNEL_1_ODT_PARAMS1 9Ch 20h MC_CHANNEL_1_ODT_PARAMS2 A0h 24h MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD A4h 28h MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD A8h

SID SVID 2Ch MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR ACh

30h MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR B0h 34h MC_CHANNEL_1_WAQ_PARAMS B4h 38h MC_CHANNEL_1_SCHEDULER_PARAMS B8h 3Ch MC_CHANNEL_1_MAINTENANCE_OPS BCh 40h MC_CHANNEL_1_TX_BG_SETTINGS C0h 44h C4h 48h MC_CHANNEL_1_RX_BGF_SETTINGS C8h 4Ch MC_CHANNEL_1_EW_BGF_SETTINGS CCh

MC_CHANNEL_1_DIMM_RESET_CMD 50h MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS D0h

MC_CHANNEL_1_DIMM_INIT_CMD 54h MC_CHANNEL_1_ROUND_TRIP_LATENCY D4h

MC_CHANNEL_1_DIMM_INIT_PARAMS 58h MC_CHANNEL_1_PAGETABLE_PARAMS1 D8h

MC_CHANNEL_1_DIMM_INIT_STATUS 5Ch MC_CHANNEL_1_PAGETABLE_PARAMS2 DCh

MC_CHANNEL_1_DDR3CMD 60h MC_TX_BG_CMD_DATA_RATIO_SETTING_CH1 E0h

64h MC_TX_BG_CMD_OFFSET_SETTINGS_CH1 E4h

MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT 68h MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 E8h

6Ch ECh

MC_CHANNEL_1_MRS_VALUE_0_1 70h MC_CHANNEL_1_ADDR_MATCH F0h

MC_CHANNEL_1_MRS_VALUE_2 74h

78h MC_CHANNEL_1_ECC_ERROR_MASK F8h

MC_CHANNEL_1_RANK_PRESENT 7Ch MC_CHANNEL_1_ECC_ERROR_INJECT FCh

F4h

28 Datasheet

Table 2-13. Device 5, Function 1: Integrated Memory Controller Channel 1

Address Registers

DID VID 00h MC_SAG_CH1_0 80h

PCISTS PCICMD 04h MC_SAG_CH1_1 84h

CCR RID 08h MC_SAG_CH1_2 88h HDR 0Ch MC_SAG_CH1_3 8Ch

10h MC_SAG_CH1_4 90h

14h MC_SAG_CH1_5 94h

18h MC_SAG_CH1_6 98h

1Ch MC_SAG_CH1_7 9Ch

20h A0h

24h A4h

28h A8h

SID SVID 2Ch

30h B0h

34h B4h

38h B8h

3Ch BCh

40h C0h

44h C4h

MC_DOD_CH1_0 48h MC_DOD_CH1_1 4Ch MC_DOD_CH1_2 50h

54h D4h

58h D8h

5Ch DCh

60h E0h

64h E4h

68h E8h

6Ch ECh

70h F0h

74h F4h

78h F8h

7Ch FCh

ACh

C8h CCh D0h

Datasheet 29

Table 2-14. Device 5, Function 2: Integrated Memory Controller Channel 1

Rank Registers

DID VID 00h MC_RIR_WAY_CH1_0 80h

PCISTS PCICMD 04h MC_RIR_WAY_CH1_1 84h

CCR RID 08h MC_RIR_WAY_CH1_2 88h HDR 0Ch MC_RIR_WAY_CH1_3 8Ch

10h MC_RIR_WAY_CH1_4 90h 14h MC_RIR_WAY_CH1_5 94h 18h MC_RIR_WAY_CH1_6 98h 1Ch MC_RIR_WAY_CH1_7 9Ch 20h MC_RIR_WAY_CH1_8 A0h 24h MC_RIR_WAY_CH1_9 A4h 28h MC_RIR_WAY_CH1_10 A8h

SID SVID 2Ch MC_RIR_WAY_CH1_11 ACh

30h MC_RIR_WAY_CH1_12 B0h 34h MC_RIR_WAY_CH1_13 B4h 38h MC_RIR_WAY_CH1_14 B8h

3Ch MC_RIR_WAY_CH1_15 BCh MC_RIR_LIMIT_CH1_0 40h MC_RIR_WAY_CH1_16 C0h MC_RIR_LIMIT_CH1_1 44h MC_RIR_WAY_CH1_17 C4h MC_RIR_LIMIT_CH1_2 48h MC_RIR_WAY_CH1_18 C8h MC_RIR_LIMIT_CH1_3 4Ch MC_RIR_WAY_CH1_19 CCh MC_RIR_LIMIT_CH1_4 50h MC_RIR_WAY_CH1_20 D0h MC_RIR_LIMIT_CH1_5 54h MC_RIR_WAY_CH1_21 D4h MC_RIR_LIMIT_CH1_6 58h MC_RIR_WAY_CH1_22 D8h MC_RIR_LIMIT_CH1_7 5Ch MC_RIR_WAY_CH1_23 DCh

60h MC_RIR_WAY_CH1_24 E0h

64h MC_RIR_WAY_CH1_25 E4h

68h MC_RIR_WAY_CH1_26 E8h

6Ch MC_RIR_WAY_CH1_27 ECh

70h MC_RIR_WAY_CH1_28 F0h

74h MC_RIR_WAY_CH1_29 F4h

78h MC_RIR_WAY_CH1_30 F8h

7Ch MC_RIR_WAY_CH1_31 FCh

30 Datasheet

+ 68 hidden pages

Intel BX80605I7870 - Core i7 2.93 GHz Processor, Core i7 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Terminology

1.1.1 Processor Terminology

1.2 References

2 Register Description

2.1 Register Terminology

2.2 Platform Configuration Structure

2.3 Device Mapping

2.4 Detailed Configuration Space Maps