Intel BX80571E5300 - Pentium 2.6 GHz Processor, Pentium Dual-Core E5000 Series Datasheet

Intel® Pentium® Dual-Core

Processor E5000

Datasheet

December 2008

Series

Document Number: 320467-002

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reserves these for future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future changes to them.

The Intel Pentium product to deviate from published specifications.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.

Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and softw are configurati ons. See http://developer.intel.com/technology/intel64/ for more information including details on which processors support Intel 64 or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information.

dual-core processor E5000 series may contain design defects or errors known as errata which may cause the

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

2 Datasheet

1 Introduction ................................................................................................ 9

1.1 Terminology .......................................................................................................9

1.1.1 Processor Terminology Definitions ............................................................10

1.2 References.......................................................................................................11

2 Electrical Specifications ............................................................................. 13

2.1 Power and Ground Lands....................................................................................13

2.2 Decoupling Guidelines ........................................................................................13

2.2.1 VCC Decoupling .....................................................................................13

2.2.2 VTT Decoupling......................................................................................13

2.2.3 FSB Decoupling......................................................................................14

2.3 Voltage Identification.........................................................................................14

2.4 Reserved, Unused, and TESTHI Signals ................................................................16

2.5 Power Segment Identifier (PSID).........................................................................16

2.6 Voltage and Current Specification........................................................................17

2.6.1 Absolute Maximum and Minimum Ratings ..................................................17

2.6.2 DC Voltage and Current Specification.................................................... .. ..18

2.6.3 VCC Overshoot ......................................................................................20

2.6.4 Die Voltage Validation............................................................... ..............21

2.7 Signaling Specifications............................................ .. ........................................21

2.7.1 FSB Signal Groups..................................................................................22

2.7.2 CMOS and Open Drain Signals .................................................................23

2.7.3 Processor DC Specifications .....................................................................24

2.7.3.1 Platform Environment Control Interface (PECI) DC

2.7.3.2 GTL+ Front Side Bus Specifications.............................................26

2.8 Clock Specifications...........................................................................................27

2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................27

2.8.2 FSB Frequency Select Signals (BSEL[2:0]).................................................28

2.8.3 Phase Lock Loop (PLL) and Filter..............................................................29

2.8.4 BCLK[1:0] Specifications.........................................................................29

3 Package Mechanical Specifications.................................................................... 33

3.1 Package Mechanical Drawing...................... .........................................................33

3.2 Processor Component Keep-Out Zones............................. ............................ .. .. ....37

3.3 Package Loading Specifications .......................................... .. .. ........................... ..37

3.4 Package Handling Guidelines............................. .. .. .. ........................... ... ..............37

3.5 Package Insertion Specifications................................................... .. .. .. ... ..............38

3.6 Processor Mass Specification...............................................................................38

3.7 Processor Materials............................................................................................38

3.8 Processor Markings............................................................................................38

3.9 Processor Land Coordinates................................................................................39

4 Land Listing and Signal Descriptions ................................................................. 41

4.1 Processor Land Assignments...............................................................................41

4.2 Alphabetical Signals Reference............................................................................64

5 Thermal Specifications and Design Considerations ............................................... 75

5.1 Processor Thermal Specifications.........................................................................75

5.1.1 Thermal Specifications............................................................................75

5.1.2 Thermal Metrology .................................................................................78

5.2 Processor Thermal Features................................................................................78

Specifications...........................................................................25

Datasheet 3

5.2.1 Thermal Monitor.......................... .. .. .......................... .. ......................... ..78

5.2.2 Thermal Monitor 2 ...................................... ......................... .. .. ...............79

5.2.3 On-Demand Mode...................................................................................80

5.2.4 PROCHOT# Signal ............................................ .. .. .......................... .. .. ....80

5.2.5 THERMTRIP# Signal................................................................................81

5.3 Platform Environment Control Interface (PECI)......................................................81

5.3.1 Introduction...........................................................................................81

5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems..................82

5.3.2 PECI Specifications .................................................................................82

5.3.2.1 PECI Device Address............................ .. .......................... .. ........82

5.3.2.2 PECI Command Support......................... .. .......................... .. ......82

5.3.2.3 PECI Fault Handling Requirements...............................................83

5.3.2.4 PECI GetTemp0() Error Code Support ......................... .. ...............83

6 Features..................................................................................................... 85

6.1 Power-On Configuration Options..........................................................................85

6.2 Clock Control and Low Power States........................... .. .. ............................ ..........85

6.2.1 Normal State .........................................................................................86

6.2.2 HALT and Extended HALT Powerdown States..............................................86

6.2.2.1 HALT Powerdown State.................................................. .. .. ........86

6.2.2.2 Extended HALT Powerdown State ................................................87

6.2.3 Stop Grant and Extended Stop Grant States...............................................87

6.2.3.1 Stop-Grant State................................. .. ............................ .. ......87

6.2.3.2 Extended Stop Grant State.........................................................88

6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended

Stop Grant Snoop State, and Stop Grant Snoop State..................................88

6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................88

6.2.4.2 Extended HALT Snoop State, Extended Stop Grant

Snoop State .............................................................................88

6.2.5 Sleep State............................................................................................88

6.2.6 Deep Sleep State....................................................................................89

6.2.7 Deeper Sleep State.................................................................................89

6.2.8 Enhanced Intel SpeedStep

Technology .......................................... ..........90

6.3 Processor Power Status Indicator (PSI) Signal .......................................................90

7 Boxed Processor Specifications........................................................................ 91

7.1 Introduction......................................................................................................91

7.2 Mechanical Specifications....................................................................................92

7.2.1 Boxed Processor Cooling Solution Dimensions.............................................92

7.2.2 Boxed Processor Fan Heatsink Weight .......................................................93

7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach

Clip Assembly.........................................................................................93

7.3 Electrical Requirements ....................... .. .. ................................................... .. .. .. ..93

7.3.1 Fan Heatsink Power Supply.................................. .. ... .. ........................... ..93

7.4 Thermal Specifications........................... ........................... ..................................95

7.4.1 Boxed Processor Cooling Requirements......................................................95

7.4.2 Variable Speed Fan............................ .......................... .. .........................97

8 Debug Tools Specifications.............................................................................. 99

8.1 Logic Analyzer Interface (LAI) .............................................................................99

8.1.1 Mechanical Considerations .......................................................................99

8.1.2 Electrical Considerations..........................................................................99

4 Datasheet

Figures

1 Processor VCC Static and Transient Tolerance...............................................................20

3 Differential Clock Waveform .......................................... .. .. ............................ ............30

4 Measurement Points for Differential Clock Waveforms ...................................................31

5 Processor Package Assembly Sketch...........................................................................33

6 Processor Package Drawing Sheet 1 of 3........................................ ........................... ..34

7 Processor Package Drawing Sheet 2 of 3........................................ ........................... ..35

8 Processor Package Drawing Sheet 3 of 3........................................ ........................... ..36

9 Processor Top-Side Markings Example ........................................................................38

10 Processor Land Coordinates and Quadrants, Top View...................................................39

11 land-out Diagram (Top View – Left Side).....................................................................42

12 land-out Diagram (Top View – Right Side)...................................................................43

13 Processor Series Thermal Profile ................................................................................77

14 Case Temperature (TC) Measurement Location ............................................................78

15 Thermal Monitor 2 Frequency and Voltage Ordering......................................................80

16 Conceptual Fan Control Diagram on PECI-Based Platforms.............................................82

17 Processor Low Power State Machine ...........................................................................86

18 Mechanical Representation of the Boxed Processor .......................................................91

19 Space Requirements for the Boxed Processor (Side View)..............................................92

20 Space Requirements for the Boxed Processor (Top View)...............................................92

21 Overall View Space Requirements for the Boxed Processor.............................................93

22 Boxed Processor Fan Heatsink Power Cable Connector Description....................... ........... 94

23 Baseboard Power Header Placement Relative to Processor Socket...................................95

24 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ................... 96

25 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) ................... 96

26 Boxed Processor Fan Heatsink Set Points.....................................................................97

Overshoot Example Waveform.............................................................................21

Datasheet 5

Tables

1 References ..............................................................................................................11

2 Voltage Identification Definition..................................................................................15

3 Absolute Maximum and Minimum Ratings ....................................................................17

4 Voltage and Current Specifications..............................................................................18

5 Processor V

6VCC Overshoot Specifications................... .. .. .. ........................... ............................ .. ....20

7 FSB Signal Groups....................................................................................................22

8 Signal Characteristics.............................................. .. ........................... .. ...................23

9 Signal Reference Voltages ...................... .. .. ..................................................... ..........23

10 GTL+ Signal Group DC Specifications..........................................................................24

11 Open Drain and TAP Output Signal Group DC Specifications ...........................................24

12 CMOS Signal Group DC Specifications..........................................................................25

13 PECI DC Electrical Limits ...........................................................................................26

14 GTL+ Bus Voltage Definitions.....................................................................................27

15 Core Frequency to FSB Multiplier Configuration.............................................................28

16 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................29

17 Front Side Bus Differential BCLK Specifications.............................................................29

18 FSB Differential Clock Specifications (800 MHz FSB)......................................................30

19 Processor Loading Specifications.................................................................................37

20 Package Handling Guidelines........................................ .. .. ..........................................37

21 Processor Materials. ..................................................................................................38

22 Alphabetical Land Assignments...................................................................................44

23 Numerical Land Assignment.......................................................................................54

24 Signal Description............. .. ......................... .. ......................... ... ......................... .. ....64

25 Processor Thermal Specifications................................................................................76

26 Processor Thermal Profile ..........................................................................................77

27 GetTemp0() Error Codes ...........................................................................................83

28 Power-On Configuration Option Signals .......................................................................85

29 Fan Heatsink Power and Signal Specifications...............................................................94

30 Fan Heatsink Power and Signal Specifications...............................................................98

Static and Transient Tolerance ...............................................................19

6 Datasheet

Intel® Pentium® Dual-Core Processor E5000 Series Features

• Available at 2.66 GHz, 2.50 GHz

• Enhanced Intel Speedstep® Technology

•Supports Intel

64Φ architecture

• Supports Execute Disable Bit capability

• FSB frequency at 800 MHz

• Binary compatible with applications running on previous members of the Intel microprocessor line

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• Optimized for 32-bit applications running on advanced 32-bit operating systems

•Intel

Advanced Smart Cache

• 2 MB Level 2 cache

•Intel

Advanced Digital Media Boost

• Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved cache hit rate on load/store operations

• 775-land Package

The Intel® Pentium® dual-core processor E5000 series is based on the Enhanced Intel® Core™ microarchitecture. The Enhanced Intel

Core™ microarchitecture combines the performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.

Intel

64Φ architecture enables the processor to execute operating systems and applications written

to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep

technology, allows tradeoffs to be made between performance and power consumption.

The Intel Pentium

dual-core processor E5000 series also includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable.

Datasheet 7

Revision History

Revision

Number

-001 • Initial release

-002

•Intel® Pentium® dual-core processor E5300 December 2008

Description Revision Date

August 2008

§ §

8 Datasheet

Introduction

1 Introduction

The Intel® Pentium® dual-core processor E5000 series is based on the Enhanced

Intel

Core™ microarchitecture. The Intel Enhanced Core™ microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller , quieter systems. The Intel® Pentium® dual-core processor E5000 series are 64-bit processors that maintain compatibility with IA-32 software.

Note: In this document, the Intel

referred to as "the processor."

Note: In this document, unless otherwise specified, the Intel

E5000 series refers to the Intel The processors use Flip-Chip Land Grid Array (FC-LGA8) package technology, and plugs

into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket.

The processor is based on 45 nm process technology. The processors feature the Intel® Advanced Smart Cache, a shared multi-core optimized cache that significantly reduces latency to frequently used data. The processor features an 800 MHz front side bus (FSB) and 2 MB of L2 cache. The processor supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Supplemental Streaming SIMD Extension 3 (SSSE3). The processor supports several Advanced Technologies: Execute Disable Bit, Intel SpeedStep

The processor's front side bus (FSB) use a split-transaction, deferred reply protocol. The FSB uses Source-Synchronous Transfer of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GB/s.

Intel has enabled support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

Technology.

Pentium® dual-core processor E5000 series may be

Pentium® dual-core processor E5200 and E5300.

64 architecture, and Enhanced Intel

Pentium® dual-core processor

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

Datasheet 9

1.1.1 Processor Terminology Definitions

Commonly used terms are explained here for clarification:

• Intel the FC-LGA8 package with a 2 MB L2 cache.

• Processor — For this document, the term processor is the generic form of the Intel

• Voltage Regulator Design Guide — For this document “Voltage R egulator Design Guide” may be used in place of:

• Enhanced Intel architecture-based desktop, mobile and mainstream server multi-core processors. For additional information refer to: http://www.intel.com/technology/architecture/

coremicro/

• Keep-out zone — The area on or near the processor that system design can not use.

• Processor core — Processor die with integrated L2 cache.

• LGA775 socket — The processors mate with the system board through a surface mount, 775-land, LGA socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.

• FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.

• Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray , or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

• Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.

• Execute Disable Bit — Execute Disable Bit allows memory to be marked as executable or non-executable , when combined with a supporting o perating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel for more detailed information.

• Intel® 64 Architecture— An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology

Pentium® dual-core processor E5000 series — Dual core processor in

Pentium® dual-core processor E5000 series.

— Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design

Guidelines For Desktop LGA775 Socket

Core™ microarchitecture — A new foundation for Intel®

Architecture Software Developer's Manual

Introduction

10 Datasheet

Introduction

Software Developer Guide at http://developer.intel.com/technology/ 64bitextensions/.

• Enhanced Intel SpeedStep® Technology — Enhanced Intel SpeedStep Technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).

• Platform Environment Control Int erf ace (P ECI) — A proprietary one-wire bus interface that provides a communication channel between the processor and chipset components to external monitoring devices.

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.

Table 1. References

Pentium® Dual-Core Processor E5000 Series Specification

Intel Update

Intel

Core™2 Duo processor E8000 and E7000 Series, and Intel® Pentium Mechanical Design Guidelines

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket

LGA775 Socket Mechanical Design Guide

Intel Manuals

Dual-Core Processor E5000 Series Thermal and

64 and IA-32 Intel Architecture Software Developer's

Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide, Part 1 Volume 3B: System Programming Guide, Part 2

Document Location

http://download.intel.com/

design/processor/

specupdt/320467.pdf

www.intel.com/design/

processor/designex/

318734.htm

http://www.intel.com/

design/processor/

applnots/313214.htm

http://intel.com/design/

Pentium4/guides/

302666.htm

http://www.intel.com/

products/processor/

manuals/

Datasheet 11

Introduction

12 Datasheet

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands.

The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the V

specifications outlined in Table 4.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (C current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4. Failure to do so can result in timing violations or reduced lifetime of the component.

), such as electrolytic or aluminum-polymer capacitors, supply

BULK

, while all VSS lands must be

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further information. Contact your Intel field representative

for additional information.

2.2.2 VTT Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.

Datasheet 13

2.2.3 FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage

to be delivered to the processor VCC lands (see Chapter 2.6.3 for V specifications). Refer to Table 12 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 4.

Electrical Specifications

overshoot

Note: To support the D eeper Sleep State the platform must use a VRD 11.1 compliant

solution. The Deeper Sleep State also requires additional platform support. Individual processor VID values may be calibrated during manufacturing such that two

devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel

Pentium®

dual-core Processor E5000 Series Specification Update for further details on specific

valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep

technology, or Extended HALT State).

The processor uses eight voltage identification signals, VID[7:0], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself.

The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V line. It should be noted that a low-to-high or high-to-low voltage state change may

). This will represent a DC shift in the load

result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 4 includes VID step sizes and DC shift ranges. Minimum and maximum v oltages must be maintained as shown in

Table 5, and Figure 1, as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 4 and Table 5 . Refer to the Voltage Regulator Design Guide for further details.

14 Datasheet

Electrical Specifications

Table 2. Voltage Identification Definition

VID7VID6VID5VID4VID3VID2VID1VID

Voltage

00000000 OFF 010111001.0375 00000010 1.6 01011110 1.025

000001001.5875 011000001.0125 00000110 1.575 01100010 1

000010001.5625 011001000.9875 00001010 1.55 01100110 0.975

000011001.5375 011010000.9625 00001110 1.525 01101010 0.95

000100001.5125 011011000.9375 00010010 1.5 01101110 0.925

000101001.4875 011100000.9125 00010110 1.475 01110010 0.9

000110001.4625 011101000.8875 00011010 1.45 01110110 0.875

000111001.4375 011110000.8625 00011110 1.425 01111010 0.85

001000001.4125 011111000.8375 00100010 1.4 01111110 0.825

001001001.3875 100000000.8125 00100110 1.375 10000010 0.8

001010001.3625 100001000.7875 00101010 1.35 10000110 0.775

001011001.3375 100010000.7625 00101110 1.325 10001010 0.75

001100001.3125 100011000.7375 00110010 1.3 10001110 0.725

001101001.2875 100100000.7125 00110110 1.275 10010010 0.7

001110001.2625 100101000.6875 00111010 1.25 10010110 0.675

001111001.2375 100110000.6625 00111110 1.225 10011010 0.65

010000001.2125 100111000.6375 01000010 1.2 10011110 0.625

010001001.1875 101000000.6125 01000110 1.175 10100010 0.6

010010001.1625 101001000.5875 01001010 1.15 10100110 0.575

010011001.1375 101010000.5625 01001110 1.125 10101010 0.55

010100001.1125 101011000.5375 01010010 1.1 10101110 0.525

010101001.0875 101100000.5125 01010110 1.075 10110010 0.5

010110001.0625 11111110 OFF 01011010 1.05

VID7VID6VID5VID4VID3VID2VID1VID

Voltage

Datasheet 15

2.4 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,

or to any other signal (including each other) can result in component malfunction

TT ,

or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 7 for details on GTL+ signals that do not include on-die termination.

Electrical Specifications

Unused active high inputs, should be connected through a resistor to ground (V Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R

TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.

All TESTHI[12,10:0] lands should be individually connected to V which matches the nominal trace impedance.

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

•TESTHI[1:0]

•TESTHI[7:2]

• TESTHI8/FC42 – cannot be grouped with other TESTHI signals

• TESTHI9/FC43 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI12/FC44 – cannot be grouped with other TESTHI signals

). For details see Table 14.

via a pull-up resistor

Terminating multiple TESTHI pins together with a single pull-up resistor is not recommended for designs supporting boundary scan for proper Boundary Scan testing of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for TESTHI[12,10:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is

Ω, then a value between 40 Ω and 60 Ω should be used.

2.5 Power Segment Identifier (PSID)

Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched power requirement situations. The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator (VR) is capable of supplying. For example, a 130 W TDP processor installed in a board with a 65 W or 95 W TDP capable VR may draw too much power and cause a potential VR issue.

16 Datasheet

Electrical Specifications

2.6 Voltage and Current Specification

2.6.1 Absolute Maximum and Minimum Ratings

Table 3 specifies absolute maximum and minimum ratings only and lie outside the

functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Table 3. Absolute Maximum and Minimum Ratings

Symbol Parameter Min Max Unit Notes

CASE

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to

3. Storage temperature is applicable to storage conditions only. In this scenario, the

4. This rating applies to the processor and does not include any tray or packaging.

5. Failure to adhere to this specification can affect the long term reliability of the processor.

Core voltage with respect to V

FSB termination voltage with respect to V

Processor case temperature See Section 5

Processor storage temperature

specifications must be satisfied.

the processor.

processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reli ability of the device. For functional operation, refer to the processor case temperature specifications.

–0.3 1.45 V -

See

Section 5

–40 85 °C 3, 4, 5

°C -

1, 2

Datasheet 17

Electrical Specifications

2.6.2 DC Voltage and Current Specification

Table 4. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID Range VID 0.8500 — 1.3625 V 1

Core V

CC_BOOT

CCPLL

VTT_OUT_LEFT and VTT_OUT_RIGHT I

CC_VCCPLL

CC_GTLREF

NOTES:

1. Each processor is programmed with a maximum valid voltage identification value (VID),

2. Unless otherwise noted, all specifications in this table are based on estimates and

3. These voltages are targets only. A variable voltage source should exist on systems in the

4. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE

5. Refer to Table 5 and Figure 1, for the minimum, typical, and maximum V

6. I

Processor Number (2 MB Cache):

E5200

E5300 Default VCC voltage for initial power up — 1.10 — V PLL V

Processor Number (2 MB Cache):

E5200

E5300 FSB termination

voltage (DC + AC

specifications)

DC Current that may be drawn from VTT_OUT_LEFT and VTT_OUT_RIGHT per land

ICC for VTT supply before VCC stable

for VTT supply after VCC stable

ICC for PLL land ——130mA ICC for GTLREF — — 200 µA

which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep

technology, or Extended HALT State).

simulations or empirical data. These specificatio ns will be updated with characteriz ed data from silicon measurements at a later date.

event that a different voltage is required. See Section 2.3 and Table 2 for more information.

lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

given current. The processor should not be subjected to any V wherein V

CC_MAX

exceeds V

specification is based on V

for

775_VR_CONFIG_06:

2.50 GHz

2.66 GHz

VCC for 775_VR_CONFIG_06:

2.50 GHz

2.66 GHz

on Intel 3 series Chipset family boards

on Intel 4 series Chipset family boards

for a given current.

CC_MAX

Refe r to Table 5, Figure 1 V3, 4, 5

- 5% 1.50 + 5% V

——

1.045 1.1 1.155 V7, 8

1.14 1.2 1.26

——580mA

——

4.5

4.6

and ICC combination

allowed for a

loadline. Refer to Figure 1 for details.

2, 10

18 Datasheet

Electrical Specifications

7. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land.

8. Baseboard bandwidth is limited to 20 MHz.

9. This is the maximum total current drawn from the V specification does not include the current coming from on-board termination (R through the signal line. Refer to the Voltage Regulator Design Guide to determine the total I

drawn by the system. This parameter is based on design characterization and is not

tested.

10. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.

Table 5. Processor VCC Static and Transient Tolerance

Voltage Deviation from VID Setting (V)

ICC (A)

0 0.000 -0.019 -0.038

5 -0.008 -0.028 -0.047 10 -0.017 -0.036 -0.056 15 -0.025 -0.045 -0.065 20 -0.033 -0.054 -0.074 25 -0.041 -0.062 -0.083 30 -0.050 -0.071 -0.092 35 -0.058 -0.079 -0.101 40 -0.066 -0.088 -0.110 45 -0.074 -0.097 -0.119 50 -0.083 -0.105 -0.128 55 -0.091 -0.114 -0.137 60 -0.099 -0.123 -0.146 65 -0.107 -0.131 -0.155 70 -0.116 -0.140 -0.164 75 -0.124 -0.148 -0.173

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.6.3.

2. This table is intended to aid in reading discrete points on Figure 1.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details.

4. Adherence to this loadline specification is required to ensure reliable processor operation.

Maximum Voltage

1.65 mΩ

Typical Voltage

1.73 mΩ

plane by only the processor. This

1, 2, 3, 4

Minimum Voltage

1.80 mΩ

Datasheet 19

Electrical Specifications

Figure 1. Processor V

VID - 0.000

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

VID - 0.088

VID - 0.100

Vcc [V]

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

VID - 0.175

VID - 0.188

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.6.3.

2. This loadline specification shows the deviation from the VID set point.

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75

Static and Transient Tolerance

Vcc Typical

Vcc Minimum

Icc [A]

Vcc Maximum

2.6.3 VCC Overshoot

The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V The time duration of the overshoot event must not exceed T

OS_MAX

maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 6. VCC Overshoot Specifications

Symbol Parameter Min Max Unit Figure Notes

OS_MAX

NOTES:

1. Adherence to these specifications is required to ensure reliable processor operation.

20 Datasheet

Magnitude of VCC overshoot above VID

Time duration of VCC overshoot above VID

is the maximum allowable overshoot voltage).

OS_MAX

—50mV2

—25µs 2

is the

Electrical Specifications

Figure 2. V

Overshoot Example Waveform

VID + 0.050

Voltage [V]

VID - 0.000

0 5 10 15 20 25

NOTES:

1. V

2. T

is measured overshoot voltage.

is measured time duration above VID.

Example Overshoot Waveform

Time [us]

TOS: Overshoot time above VID V

: Overshoot above VID

2.6.4 Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit.

2.7 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as V separate power planes for each processor (and chipset), separate V are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (R GTL+ signals are provided on the processor silicon and are terminated to V chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

. Because platforms implement

and V

supplies

. Intel

) for

Datasheet 21

2.7.1 FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 7 identifies which signals are common clock, source synchronous, and asynchronous.

Table 7. FSB Signal Groups

Signal Group Type Signals

GTL+ Common Clock Input

GTL+ Common Clock I/O

Synchronous to BCLK[1:0]

Electrical Specifications

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[5:0]#, BR0#

HIT#, HITM#, LOCK#

, DBSY#, DRDY#,

Signals Associated Strobe

REQ[4:0]#, A[16:3]#

GTL+ Source Synchronous I/O

GTL+ Strobes

CMOS

Open Drain Output FERR#/PBE#, IERR#, THERMTRIP#, TDO Open Drain Input/

Output FSB Clock C lock BCLK[1:0], ITP_CLK[1:0]

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where no debug port is implemented on the system board, these

signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

Synchronous to assoc. strobe

Synchronous to BCLK[1:0]

A[35:17]# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3#

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPRSTP#. DPSLP#, IGNNE#, INIT#, LINT0/

INTR , LINT1/NMI, SMI# TCK, TDI, TMS, TRST#, BSEL[2:0], VID[7:0], PSI#

PROCHOT#

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[12,10:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR# VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]

ADSTB0# ADSTB1#

, STPCLK#, PWRGOOD, SLP#,

, VTT_OUT_LEFT,

22 Datasheet

Electrical Specifications

3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.

4. PROCHOT# signal type is open drain output and CMOS input.

Table 8. Signal Characteristics

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY#

Open Drain Signals

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#, TDO, FCx

NOTES:

1. Signals that do not have R

Table 9. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3: 0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY#

NOTE:

1. See Table 11 for more information.

Signals with No R

A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0], COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/ NMI, MSID[1:0], PWRGOOD, RESET#, SMI#, STPCLK#, TDO, TESTHI[12,10:0], THERMTRIP#, VID[7:0], GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL

, nor are actively driven to their high-voltage level.

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD TDI

, SMI#, STPCLK#, TCK1,

, TMS1, TRST#

2.7.2 CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states.

Datasheet 23

2.7.3 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.

Table 10. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

Electrical Specifications

Input Low Voltage -0.10 GTLREF – 0.10 V 2, 5

Input High Voltage GTLREF + 0.10 V

Output High Voltage V

Output Low Current N/A

Input Leakage

Current Output Leakage

Current Buffer On Resistance 7.49 9.16 Ω

– 0.10 V

[(R

TT_MIN

N/A ± 100 µA 6

N/A ± 100 µA 7

+ 0.10 V 3, 4, 5

V ) + (2 * R

TT_MAX

ON_MIN

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. V

is defined as the voltage range at a receiving agent that will be interpret ed as a l ogical

low value.

3. V

4. V

5. The V

6. Leakage to V

7. Leakage to V

is defined as the voltage range at a receiving agent that will be int erpreted as a logic al

high value.

and VOH may experience excursions above VTT.

referred to in these specifications is the instantaneous VTT.

with land held at VTT.

with land held at 300 mV.

Table 11. Open Drain and TAP Output Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

I I

Output Low Voltage 0 0.20 V -

Output Low Current 16 50 mA 2

Output Leakage Current N/A ± 200 µA 3

V4, 5

A-

)]

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Measured at V

3. For Vin between 0 and V

24 Datasheet

* 0.2 V.

Electrical Specifications

Table 12. CMOS Signal Group DC Specifications

Symb

Input Low Voltage -0.10 VTT * 0.30 V 3, 6 Input High Voltage VTT * 0.70 V Output Low Voltage -0.10 VTT * 0.10 V 6 Output High Voltage 0.90 * V Output Low Current VTT * 0.10 / 67 VTT * 0.10 / 27 A 6, 7 Output Low Current VTT * 0.10 / 67 VTT * 0.10 / 27 A 6, 7 Input Leakage Current N/A ± 100 µA 8 Output Leakage Current N/A ± 100 µA 9

Parameter Min Max Unit Notes

+ 0.10 V 4, 5, 6

+ 0.10 V 2, 5, 6

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

3. V

is defined as the voltage range at a receiving agent that will be interpreted as a logical

low value.

4. V

5. V

6. The V

7. I

is defined as the voltage r ange at a rec eiving age nt that will be interpreted as a logical

high value.

and VOH may experience excursions above VTT.

referred to in these specifications refers to instantaneous VTT.

is measured at 0.10 * V

is measured at 0.90 * V

TT. IOH

TT .

8. Leakage to VSS with land held at VTT.

9. Leakage to V

with land held at 300 mV.

2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI)

Specification.

Datasheet 25

Table 13. PECI DC Electrical Limits

Symbol Definition and Conditions M in Max Units Notes

hysteresis

V V

source

sink

leak+

leak-

noise

NOTES:

1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer to Table 4 for V

2. The leakage specification applies to powered devices on the PECI bus.

3. The input buffers use a Schmitt-triggered input design for improved noise immunity.

4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes.

Input Voltage Range -0.15 V

Hysteresis 0.1 * V Negative-edge threshold voltage 0.275 * VTT0.500 * V

Positive-edge threshold voltage 0.550 * VTT0.725 * V

High level output source

= 0.75 * V

TT)

Low level output sink

= 0.25 * VTT)

High impedance state leakage to V High impedance leakage to GND N/A 10 µA 3 Bus capacitance per node N/A 10 pF 4

bus

Signal noise immunity above 300 MHz

specifications.

Electrical Specifications

—V

TT TT

-6.0 N/A mA

0.5 1.0 mA

N/A 50 µA

0.1 * V

—V

V V

p-p

2.7.3.2 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination.

Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.

26 Datasheet

Electrical Specifications

Table 14. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_PU

GTLREF_PD

COMP[3:0] COMP Resistance 49.40 49.90 50.40 Ω 4 COMP8 COMP Resistance 24.65 24.90 25.15 Ω 4

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. GTLREF is to be generated from V GTLREF circuit is used on the board (for Quad-Core processors compatibility) the two GTLREF lands connected to the Adjustable GTLREF circuit require the following: GTLREF_PU = 50 Ω, GTLREF_PD = 100 Ω.

3. R

4. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and COMP8 resistors are to V

GTLREF pull up on Intel 3 Series Chipset family boards

GTLREF pull down on

Intel

3 Series Chipset

family boards Termination Resistance 45 50 55 Ω 3

is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.

57.6 * 0.99 57.6 57.6 * 1.01 Ω 2

100 * 0.99 100 100 * 1.01 Ω 2

by a voltage divider of 1% resistors. If an Adjustable

2.8 Clock Specifications

2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus r atio multiplier will be set at its default ratio during manufacturing. The processor supports Half Ratios between 7.5 and 13.5, refer to Table 15 for the processor supported ratios.

The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative.

Datasheet 27

Table 15. C ore Fr eque ncy to FSB Multiplier Configuration

Electrical Specifications

Multiplication of System Core

Frequency to FSB Frequency

1/6 1/7

1/7.5

1/8

1/8.5

1/9

1/9.5

1/10

1/10.5

1/11

1/11.5

1/12 2.4 GHz -

1/12.5 2.5 GHz -

1/13

1/13.5

1/14 1/15

NOTES:

1. In dividual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

(200 MHz BCLK/800 MHz FSB)

Core Frequency

1.20 GHz

1.40 GHz

1.5 GHz

1.60 GHz

1.70 GHz

1.80 GHz

1.90 GHz 2 GHz

2.1 GHz

2.2 GHz

2.3 GHz

2.6 GHz

2.7 GHz

2.8 GHz 3 GHz

Notes

1, 2

2.8.2 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.

The processor operates at a 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency.

For more information about these signals, refer to Section 4.2.

28 Datasheet

Electrical Specifications

Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

LL L Rerserved LL H Rerserved LH H Rerserved

L H L 200 MHz HH L Rerserved HH H Rerserved HL H Rerserved HL L Rerserved

2.8.3 Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 4 for DC specifications.

2.8.4 BCLK[1:0] Specifications

Table 17. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

V V

CROSS(abs)

ΔV

CROSS

SWING

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of

3. “Steady state” voltage, not including overshoot or undershoot.

4. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined

5. Measurement taken from differential waveform.

Input Low Voltage -0.30 N/A N/A V 3

Input High Voltage N/A N/A 1.15 V 3 Absolute Crossing Point 0.300 N/A 0.550 V 3 2 Range of Crossing Points N/A N/A 0.140 V 3 - Overshoot N/A N/A 1.4 V 3 3 Undershoot -0.300 N/A N/A V 3 3 Differential Output Swing 0.300 N/A N/A V 4 4

BCLK0 equals the falling edge of BCLK1.

as the absolute value of the minimum voltage.

Datasheet 29

Table 18. FSB Differential Clock Specifications (800 MHz FSB)

T# Parameter Min Nom Max Unit Figure Notes

BCLK[1:0] Frequency 198.980 — 200.020 MHz - T1: BCLK[1:0] Period 4.99950 — 5.00050 ns 3 T2: BCLK[1:0] Period Stability — — 150 ps 3 T5: BCLK[1:0] Rise and Fall Slew Rate 2.5 — 8 V/nS 3 T6: Slew Rate Matching N/A N/A 20 %

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies

based on a 200 MHz BCLK[1:0].

2. Duty Cycle (High time/Period) must be between 40 and 60%.

3. The period specified here is the average period. A giv e n pe riod may vary from this specificat ion

as governed by the period stability specification (T2). Min period specifi cation is based on 300 PPM deviation from a 5 ns period. Max period specification is based on the summation of +300 PPM deviation from a 5 ns period and a +0.5% maximum variance due to spread spectrum clocking.

4. In this context, period stability is defined as the worst case timing difference between successive

crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability.

5. Measurement taken from differential waveform.

6. Matchin g applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured

using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Slew rate matching is a single ended measurement.

Electrical Specifications

2 3 4 5 6

Figure 3. Differential Clock Waveform

BCLK1

Threshold

Region

BCLK0

Tp = T 1 : B CLK[1 :0] perio d T2: BCLK[1:0] period stability (not shown) Tph = T3: BCLK[1:0] pulse high time Tpl = T 4 : B CLK[1:0] puls e low time T5: BCLK[1 :0 ] rise time th r o ugh th e th reshold r e g io n T6: BCLK[1 :0 ] fa ll time thro u gh the th re s h o l d re gion

Tph

CROSS (ABS

Overshoot

Rising Edge

Ringback

)

CROSS (ABS

Tpl

Margin

Ringback

Falling Edg e

Ringback

Undershoot

30 Datasheet

+ 70 hidden pages

Intel BX80571E5300 - Pentium 2.6 GHz Processor, Pentium Dual-Core E5000 Series Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Figures

Tables

Intel® Pentium® Dual-Core Processor E5000 Series Features

Revision History

1 Introduction

1.1 Terminology

1.1.1 Processor Terminology Definitions

1.2 References

Table 1. References

2 Electrical Specifications

2.1 Power and Ground Lands

2.2 Decoupling Guidelines

2.2.1 VCC Decoupling

2.2.2 VTT Decoupling

2.2.3 FSB Decoupling

2.3 Voltage Identification

Table 2. Voltage Identification Definition

2.4 Reserved, Unused, and TESTHI Signals

2.5 Power Segment Identifier (PSID)

2.6 Voltage and Current Specification

2.6.1 Absolute Maximum and Minimum Ratings

Table 3. Absolute Maximum and Minimum Ratings

2.6.2 DC Voltage and Current Specification

Table 4. Voltage and Current Specifications

Table 5. Processor VCC Static and Transient Tolerance

2.6.3 VCC Overshoot

Table 6. VCC Overshoot Specifications

2.6.4 Die Voltage Validation

2.7 Signaling Specifications

2.7.1 FSB Signal Groups

Table 7. FSB Signal Groups

Table 8. Signal Characteristics

Table 9. Signal Reference Voltages

2.7.2 CMOS and Open Drain Signals

2.7.3 Processor DC Specifications

Table 10. GTL+ Signal Group DC Specifications

Table 11. Open Drain and TAP Output Signal Group DC Specifications

Table 12. CMOS Signal Group DC Specifications

2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications

Table 13. PECI DC Electrical Limits

2.7.3.2 GTL+ Front Side Bus Specifications

Table 14. GTL+ Bus Voltage Definitions

2.8 Clock Specifications

2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

Table 15. C ore Fr eque ncy to FSB Multiplier Configuration

2.8.2 FSB Frequency Select Signals (BSEL[2:0])

Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

2.8.3 Phase Lock Loop (PLL) and Filter

2.8.4 BCLK[1:0] Specifications

Table 17. Front Side Bus Differential BCLK Specifications

Table 18. FSB Differential Clock Specifications (800 MHz FSB)

Figure 3. Differential Clock Waveform