– For the Intel® 82955X Memory Controller Hub (MCH)
April 2005
Document Number: 307012-001
R
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The Intel
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
∆
different processor families. See www.intel.com/products/processor_number
Intel, Pentium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
As the complexity of computer systems increases, so do the power dissipation requirements. Care
must be taken to ensure that the additional power is properly dissipated. Typical methods to
improve heat dissipation include selective use of ducting, and/or passive heatsinks.
The goals of this document are to:
®
• Outline the thermal and mechanical operating limits and specifications for the Intel
Express Chipset Memory Controller Hub (MCH).
• Describe a reference thermal solution that meets the specification of the 82955X MCH.
Properly designed thermal solutions provide adequate cooling to maintain the MCH die
temperatures at or below thermal specifications. This is accomplished by providing a low localambient temperature, ensuring adequate local airflow, and minimizing the die to local-ambient
thermal resistance. By maintaining the MCH die temperature at or below the specified limits, a
system designer can ensure the proper functionality, performance, and reliability of the chipset.
Operation outside the functional limits can degrade system performance and may cause
permanent changes in the operating characteristics of the component.
82955X
The simplest and most cost effective method to improve the inherent system cooling
characteristics is through careful design and placement of fans, vents, and ducts. When additional
cooling is required, component thermal solutions may be implemented in conjunction with system
thermal solutions. The size of the fan or heatsink can be varied to balance size and space
constraints with acoustic noise.
This document addresses thermal design and specifications for the 82955X MCH component
only. For thermal design information on other chipset components, refer to the respective
component datasheet. For the ICH7, refer to the Intel
®
I/O Controller Hub 7 (ICH7) Thermal
Design Guidelines.
Note: Unless otherwise specified, the term MCH refers to the Intel
BGA Ball grid array. A package type, defined by a resin-fiber substrate, onto which a die is
mounted, bonded and encapsulated in molding compound. The primary electrical interface is
an array of solder balls attached to the substrate opposite the die and molding compound.
BLT Bond line thickness. Final settled thickness of the thermal interface material after installation
additional functionality compared to previous ICH components. The I/O Controller Hub
component that contains the primary PCI interface, LPC interface, USB2, ATA-100, and
other I/O functions. It communicates with the MCH over a proprietary interconnect called
DMI.
MCH Memory Controller Hub. The chipset component that contains the processor interface, the
memory interface, and the DMI.
T
case_max
T
case_min
TDP Thermal design power. Thermal solutions should be designed to dissipate this target power
Maximum die temperature allowed. This temperature is measured at the geometric center of
the top of the package die.
Minimum die temperature allowed. This temperature is measured at the geometric center of
the top of the package die.
level. TDP is not the maximum power that the chipset can dissipate.
R
1.2 Reference Documents
The reader of this specification should also be familiar with material and concepts presented in
the following documents:
The 955X Express chipset consists of two individual components: the MCH and the ICH7. The
MCH component uses a 34 mm squared, 6-layer flip chip ball grid array (FC-BGA) package (see
Figure 2-1 through Figure 2-3). For information on the ICH7 package, refer to the IntelController Hub 7 (ICH7) Thermal Design Guidelines.
Figure 2-1. MCH Package Dimensions (Top View)
®
I/O
Capaci tor Area,
Handling Exclusion
Zone
3.1
15.349.14
3.1
Handling Area
Figure 2-2. MCH Package Dimensions (Side View)
2.355 ± 0.082 mm
Substrate
1.92 ± 0.078 mm
0.84 ± 0.05 mm
Decoup
Cap
19.38
10.67
MCH
Die
6.17
2.54
34.00
Die
0. 7 mm Max
2.30
2.0
3.0
Ø5.20mm
Die
Keepout
Area
34.00
955X_Pkg_TopView
0.20 See note 4.
0.435 ± 0.025 mm
See note 3
Notes:
1. Primary datum -C- and seating plan are defined by the spherical crow ns of the solder balls (shown before motherboard attach)
2. All dimensions and tolerances conf orm to ANSI Y14.5M-1994
3. BGA has a pre-SMT height of 0.5mm and post-SMT height of 0.41-0.46mm
4. Shown before motherboard attach; FCBGA has a convex (dome shaped) orientation before reflow and is expected to have a slightly concave (bow l
shaped) orientation after reflow
2. All dimensions and tolerances conform to ANSI Y14.5M-1994.
2.1 Package Mechanical Requirements
The MCH package has an exposed bare die that is capable of sustaining a maximum static normal
load of 10-lbf. The package is NOT capable of sustaining a dynamic or static compressive load
applied to any edge of the bare die. These mechanical load limits must not be exceeded during
heatsink installation, mechanical stress testing, standard shipping conditions and/or any other use
condition.
Note:
1. The heatsink attach solutions must not result in continuous stress onto the chipset package
with the exception of a uniform load to maintain the heatsink-to-package thermal interface.
2. These specifications apply to uniform compressive loading in a direction perpendicular to the
bare die top surface.
3. These specifications are based on limited testing for design characterization. Loading limits
Analysis indicates that real applications are unlikely to cause the chipset MCH to consume
maximum power dissipation for sustained time periods. Therefore, to arrive at a more realistic
power level for thermal design purposes, Intel characterizes power consumption based on known
platform benchmark applications. The resulting power consumption is referred to as the Thermal
Design Power (TDP). TDP is the target power level that the thermal solutions should be designed
to. TDP is not the maximum power that the chipset can dissipate.
For TDP specifications, see Table 3-1 for the 955X Express chipset MCH. FC-BGA packages
have limited heat transfer capability into the board and have minimal thermal capability without a
thermal solution. Intel recommends that system designers plan for one or more heatsinks when
using the 955X Express chipset.
3.2 Die Case Temperature Specifications
To ensure proper operation and reliability of the MCH, the die temperatures must be at or
between the maximum/minimum operating range as specified in Table 3-1 for the 82955X MCH.
System and/or component level thermal solutions are required to maintain these temperature
specifications. Refer to Chapter 5 for guidelines on accurately measuring package die
temperatures.
Table 3-1. MCH Thermal Specifications
Parameter Value Notes
T
105 °C —
case_max
T
5 °C —
case_min
TDP
NOTE: These specifications are based on silicon characterization; however, they may be updated as further