Intel 945GME User Manual

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Intel® I/O Controller Hub 7 (ICH7) Family

Datasheet

— For the Intel® 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,

82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O Controller Hubs

April 2007

Document Number: 307013-003

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® I/O Controller Hub 7 (ICH7) Family chipset component may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.

Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

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Contents

1 Introduction ............................................................................................................ 39

1.1 Overview ......................................................................................................... 42

1.2 Intel® ICH7 Family High-Level Component Differences ........................................... 50

2 Signal Description ................................................................................................... 51

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 55

2.2 PCI Express* (Desktop and Mobile Only) .............................................................. 55

2.3 Platform LAN Connect Interface (Desktop and Mobile Only)..................................... 56

2.4 EEPROM Interface (Desktop and Mobile Only)........................................................ 56

2.5 Firmware Hub Interface (Desktop and Mobile Only)................................................ 56

2.6 PCI Interface .................................................................................................... 57

2.7 Serial ATA Interface (Desktop and Mobile Only) ..................................................... 59

2.8 IDE Interface.................................................................................................... 60

2.9 LPC Interface.................................................................................................... 62

2.10 Interrupt Interface ............................................................................................ 62

2.11 USB Interface ................................................................................................... 63

2.12 Power Management Interface.............................................................................. 64

2.13 Processor Interface............................................................................................ 66

2.14 SMBus Interface................................................................................................ 68

2.15 System Management Interface............................................................................ 68

2.16 Real Time Clock Interface................................................................................... 69

2.17 Other Clocks..................................................................................................... 69

2.18 Miscellaneous Signals ........................................................................................ 70

2.19 AC ’97/Intel® High Definition Audio Link............................................................... 71

2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................... 72

2.21 Intel® Quick Resume Technology (Intel® ICH7DH Only) ......................................... 72

2.22 General Purpose I/O Signals ............................................................................... 72

2.23 Power and Ground............................................................................................. 74

2.24 Pin Straps ........................................................................................................ 76

2.24.1 Functional Straps ................................................................................... 76

2.24.2 External RTC Circuitry ............................................................................. 78

3 Intel® ICH7 Pin States.............................................................................................79

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 79

3.2 IDE Integrated Series Termination Resistors.......................................................... 80

3.3 Output and I/O Signals Planes and States............................................................. 81

3.4 Power Planes for Input Signals ............................................................................ 90

4 Intel® ICH7 and System Clock Domains................................................................... 95

5 Functional Description............................................................................................. 99

5.1 PCI-to-PCI Bridge (D30:F0) ................................................................................ 99

5.1.1 PCI Bus Interface ................................................................................... 99

5.1.2 PCI Bridge As an Initiator ........................................................................ 99

5.1.2.1 Memory Reads and Writes.......................................................... 99

5.1.2.2 I/O Reads and Writes .............................................................. 100

5.1.2.3 Configuration Reads and Writes ................................................ 100

5.1.2.4 Locked Cycles......................................................................... 100

5.1.2.5 Target / Master Aborts............................................................. 100

5.1.2.6 Secondary Master Latency Timer............................................... 100

5.1.2.7 Dual Address Cycle (DAC) ........................................................ 100

5.1.2.8 Memory and I/O Decode to PCI................................................. 101

5.1.3 Parity Error Detection and Generation ..................................................... 101

5.1.4 PCIRST#............................................................................................. 101

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5.1.5 Peer Cycles ..........................................................................................102

5.1.6 PCI-to-PCI Bridge Model ........................................................................102

5.1.7 IDSEL to Device Number Mapping...........................................................103

5.1.8 Standard PCI Bus Configuration Mechanism..............................................103

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) ..........103

5.2.1 Interrupt Generation .............................................................................103

5.2.2 Power Management...............................................................................104

5.2.2.1 S3/S4/S5 Support ...................................................................104

5.2.2.2 Resuming from Suspended State ...............................................104

5.2.2.3 Device Initiated PM_PME Message ............................................. 104

5.2.2.4 SMI/SCI Generation.................................................................105

5.2.3 SERR# Generation ................................................................................105

5.2.4 Hot-Plug..............................................................................................106

5.2.4.1 Presence Detection ..................................................................106

5.2.4.2 Message Generation ................................................................106

5.2.4.3 Attention Button Detection .......................................................107

5.2.4.4 SMI/SCI Generation.................................................................107

5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile Only) ..........................................108

5.3.1 LAN Controller PCI Bus Interface.............................................................108

5.3.1.1 Bus Slave Operation ................................................................109

5.3.1.2 CLKRUN# Signal (Mobile Only)..................................................110

5.3.1.3 PCI Power Management ...........................................................110

5.3.1.4 PCI Reset Signal......................................................................110

5.3.1.5 Wake-Up Events......................................................................111

5.3.1.6 Wake on LAN* (Preboot Wake-Up).............................................112

5.3.2 Serial EEPROM Interface ........................................................................112

5.3.3 CSMA/CD Unit......................................................................................113

5.3.3.1 Full Duplex.............................................................................113

5.3.3.2 Flow Control ...........................................................................113

5.3.3.3 VLAN Support .........................................................................113

5.3.4 Media Management Interface .................................................................113

5.3.5 TCO Functionality .................................................................................114

5.3.5.1 Advanced TCO Mode ................................................................114

5.4 Alert Standard Format (ASF) (Desktop and Mobile Only) .......................................115

5.4.1 ASF Management Solution Features/Capabilities .......................................116

5.4.2 ASF Hardware Support ..........................................................................117

5.4.2.1 Intel® 82562EM/EX .................................................................117

5.4.2.2 EEPROM (256x16, 1 MHz) ........................................................117

5.4.2.3 Legacy Sensor SMBus Devices ..................................................117

5.4.2.4 Remote Control SMBus Devices.................................................117

5.4.2.5 ASF Sensor SMBus Devices.......................................................117

5.4.3 ASF Software Support ...........................................................................118

5.5 LPC Bridge (w/ System and Management Functions) (D31:F0) ...............................118

5.5.1 LPC Interface .......................................................................................118

5.5.1.1 LPC Cycle Types ......................................................................119

5.5.1.2 Start Field Definition................................................................119

5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR).....................................120

5.5.1.4 SIZE......................................................................................120

5.5.1.5 SYNC.....................................................................................121

5.5.1.6 SYNC Time-Out.......................................................................121

5.5.1.7 SYNC Error Indication ..............................................................121

5.5.1.8 LFRAME# Usage......................................................................122

5.5.1.9 I/O Cycles .............................................................................. 122

5.5.1.10 Bus Master Cycles ...................................................................122

5.5.1.11 LPC Power Management ...........................................................122

5.5.1.12 Configuration and Intel® ICH7 Implications.................................123

5.5.2 SERR# Generation ................................................................................123

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5.6 DMA Operation (D31:F0).................................................................................. 124

5.6.1 Channel Priority ................................................................................... 124

5.6.1.1 Fixed Priority.......................................................................... 125

5.6.1.2 Rotating Priority ..................................................................... 125

5.6.2 Address Compatibility Mode................................................................... 125

5.6.3 Summary of DMA Transfer Sizes............................................................. 125

5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by

Words ................................................................................... 126

5.6.4 Autoinitialize........................................................................................ 126

5.6.5 Software Commands............................................................................. 126

5.7 LPC DMA (Desktop and Mobile Only) .................................................................. 127

5.7.1 Asserting DMA Requests........................................................................ 127

5.7.2 Abandoning DMA Requests .................................................................... 127

5.7.3 General Flow of DMA Transfers ............................................................... 128

5.7.4 Terminal Count .................................................................................... 128

5.7.5 Verify Mode ......................................................................................... 128

5.7.6 DMA Request Deassertion...................................................................... 129

5.7.7 SYNC Field / LDRQ# Rules..................................................................... 129

5.8 8254 Timers (D31:F0) ..................................................................................... 130

5.8.1 Timer Programming.............................................................................. 131

5.8.2 Reading from the Interval Timer............................................................. 132

5.8.2.1 Simple Read........................................................................... 132

5.8.2.2 Counter Latch Command.......................................................... 132

5.8.2.3 Read Back Command .............................................................. 132

5.9 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 133

5.9.1 Interrupt Handling................................................................................ 134

5.9.1.1 Generating Interrupts.............................................................. 134

5.9.1.2 Acknowledging Interrupts ........................................................ 134

5.9.1.3 Hardware/Software Interrupt Sequence ..................................... 135

5.9.2 Initialization Command Words (ICWx) ..................................................... 135

5.9.2.1 ICW1 .................................................................................... 135

5.9.2.2 ICW2 .................................................................................... 136

5.9.2.3 ICW3 .................................................................................... 136

5.9.2.4 ICW4 .................................................................................... 136

5.9.3 Operation Command Words (OCW) ......................................................... 136

5.9.4 Modes of Operation .............................................................................. 136

5.9.4.1 Fully Nested Mode................................................................... 136

5.9.4.2 Special Fully-Nested Mode........................................................ 137

5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 137

5.9.4.4 Specific Rotation Mode (Specific Priority).................................... 137

5.9.4.5 Poll Mode............................................................................... 137

5.9.4.6 Cascade Mode ........................................................................ 138

5.9.4.7 Edge and Level Triggered Mode................................................. 138

5.9.4.8 End of Interrupt (EOI) Operations ............................................. 138

5.9.4.9 Normal End of Interrupt........................................................... 138

5.9.4.10 Automatic End of Interrupt Mode .............................................. 138

5.9.5 Masking Interrupts ............................................................................... 139

5.9.5.1 Masking on an Individual Interrupt Request................................ 139

5.9.5.2 Special Mask Mode.................................................................. 139

5.9.6 Steering PCI Interrupts ......................................................................... 139

5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140

5.10.1 Interrupt Handling................................................................................ 140

5.10.2 Interrupt Mapping ................................................................................ 140

5.10.3 PCI / PCI Express* Message-Based Interrupts.......................................... 141

5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141

5.10.4.1 Edge-Triggered Operation......................................................... 142

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5.10.4.2 Level-Triggered Operation.........................................................142

5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery ..........142

5.10.4.4 Interrupt Message Format ........................................................142

5.11 Serial Interrupt (D31:F0)..................................................................................143

5.11.1 Start Frame .........................................................................................143

5.11.2 Data Frames ........................................................................................144

5.11.3 Stop Frame..........................................................................................144

5.11.4 Specific Interrupts Not Supported via SERIRQ...........................................144

5.11.5 Data Frame Format...............................................................................145

5.12 Real Time Clock (D31:F0) ................................................................................. 146

5.12.1 Update Cycles ......................................................................................146

5.12.2 Interrupts............................................................................................ 147

5.12.3 Lockable RAM Ranges............................................................................147

5.12.4 Century Rollover...................................................................................147

5.12.5 Clearing Battery-Backed RTC RAM...........................................................147

5.13 Processor Interface (D31:F0) ............................................................................149

5.13.1 Processor Interface Signals ....................................................................149

5.13.1.1 A20M# (Mask A20)..................................................................149

5.13.1.2 INIT# (Initialization)................................................................150

5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric

Error) ....................................................................................150

5.13.1.4 NMI (Non-Maskable Interrupt) ..................................................151

5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#) ........151

5.13.1.6 CPU Power Good (CPUPWRGOOD) .............................................151

5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only) ......................151

5.13.2 Dual-Processor Issues (Desktop Only) .....................................................152

5.13.2.1 Signal Differences ...................................................................152

5.13.2.2 Power Management .................................................................152

5.14 Power Management (D31:F0) ............................................................................153

5.14.1 Features..............................................................................................153

5.14.2 Intel® ICH7 and System Power States .....................................................153

5.14.3 System Power Planes ............................................................................156

5.14.4 SMI#/SCI Generation............................................................................156

5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) ..............................159

5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) .......................159

5.14.5 Dynamic Processor Clock Control ............................................................159

5.14.5.1 Transition Rules among S0/Cx and Throttling States.....................160

5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) .................................161

5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) ..................161

5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only).............161

5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)................................161

5.14.6.1 Conditions for Checking the PCI Clock ........................................162

5.14.6.2 Conditions for Maintaining the PCI Clock.....................................162

5.14.6.3 Conditions for Stopping the PCI Clock ........................................162

5.14.6.4 Conditions for Re-Starting the PCI Clock..................................... 162

5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only) ............162

5.14.7 Sleep States ........................................................................................163

5.14.7.1 Sleep State Overview...............................................................163

5.14.7.2 Initiating Sleep State ...............................................................163

5.14.7.3 Exiting Sleep States................................................................. 163

5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (

Desktop and Mobile only) .........................................................165

5.14.7.5 Sx-G3-Sx, Handling Power Failures ............................................165

5.14.8 Thermal Management............................................................................166

5.14.8.1 THRM# Signal.........................................................................166

5.14.8.2 Processor Initiated Passive Cooling ............................................ 166

5.14.8.3 THRM# Override Software Bit ...................................................167

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5.14.8.4 Active Cooling ........................................................................ 167

5.14.9 Event Input Signals and Their Usage....................................................... 167

5.14.9.1 PWRBTN# (Power Button)........................................................ 167

5.14.9.2 RI# (Ring Indicator)................................................................ 168

5.14.9.3 PME# (PCI Power Management Event)....................................... 169

5.14.9.4 SYS_RESET# Signal................................................................ 169

5.14.9.5 THRMTRIP# Signal.................................................................. 169

5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only) ....................................... 170

5.14.10ALT Access Mode.................................................................................. 170

5.14.10.1Write Only Registers with Read Paths in ALT Access Mode............. 171

5.14.10.2PIC Reserved Bits ................................................................... 173

5.14.10.3Read Only Registers with Write Paths in ALT Access Mode............. 173

5.14.11System Power Supplies, Planes, and Signals ............................................ 173

5.14.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 173

5.14.11.2SLP_S4# and Suspend-To-RAM Sequencing................................ 174

5.14.11.3PWROK Signal ........................................................................ 174

5.14.11.4CPUPWRGD Signal .................................................................. 175

5.14.11.5VRMPWRGD Signal.................................................................. 175

5.14.11.6BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)..................... 175

5.14.11.7Controlling Leakage and Power Consumption during Low-Power

States ................................................................................... 175

5.14.12Clock Generators.................................................................................. 176

5.14.12.1Clock Control Signals from Intel® ICH7 to Clock

Synthesizer (Mobile/Ultra Mobile Only)....................................... 176

5.14.13Legacy Power Management Theory of Operation ....................................... 177

5.14.13.1APM Power Management (Desktop Only).................................... 177

5.14.13.2Mobile APM Power Management (Mobile/Ultra Mobile Only)........... 177

5.15 System Management (D31:F0).......................................................................... 178

5.15.1 Theory of Operation.............................................................................. 178

5.15.1.1 Detecting a System Lockup ...................................................... 178

5.15.1.2 Handling an Intruder ............................................................... 178

5.15.1.3 Detecting Improper Firmware Hub Programming......................... 179

5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and Mobile Only) ......... 179

5.16 IDE Controller (D31:F1) ................................................................................... 183

5.16.1 PIO Transfers....................................................................................... 183

5.16.1.1 PIO IDE Timing Modes............................................................. 184

5.16.1.2 IORDY Masking....................................................................... 184

5.16.1.3 PIO 32-Bit IDE Data Port Accesses ............................................ 184

5.16.1.4 PIO IDE Data Port Prefetching and Posting ................................. 185

5.16.2 Bus Master Function ............................................................................. 185

5.16.2.1 Physical Region Descriptor Format............................................. 185

5.16.2.2 Bus Master IDE Timings........................................................... 186

5.16.2.3 Interrupts.............................................................................. 186

5.16.2.4 Bus Master IDE Operation ........................................................ 187

5.16.2.5 Error Conditions...................................................................... 188

5.16.3 Ultra ATA/100/66/33 Protocol................................................................. 188

5.16.3.1 Operation .............................................................................. 189

5.16.4 Ultra ATA/33/66/100 Timing .................................................................. 190

5.16.5 ATA Swap Bay...................................................................................... 190

5.16.6 SMI Trapping ....................................................................................... 190

5.17 SATA Host Controller (D31:F2) (Desktop and Mobile Only) .................................... 191

5.17.1 Theory of Operation.............................................................................. 192

5.17.1.1 Standard ATA Emulation .......................................................... 192

5.17.1.2 48-Bit LBA Operation............................................................... 192

5.17.2 SATA Swap Bay Support........................................................................ 193

5.17.3 Intel® Matrix Storage Technology Configuration (Intel® ICH7R, ICH7DH,

and ICH7-M DH Only) ........................................................................... 193

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5.17.3.1 Intel® Matrix Storage Manager RAID Option ROM ........................194

5.17.4 Power Management Operation ................................................................194

5.17.4.1 Power State Mappings..............................................................194

5.17.4.2 Power State Transitions ............................................................195

5.17.4.3 SMI Trapping (APM).................................................................196

5.17.5 SATA LED ............................................................................................196

5.17.6 AHCI Operation (Intel® ICH7R, ICH7DH, and Mobile Only) .........................196

5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) .................197

5.18 High Precision Event Timers ..............................................................................197

5.18.1 Timer Accuracy.....................................................................................197

5.18.2 Interrupt Mapping.................................................................................198

5.18.3 Periodic vs. Non-Periodic Modes.............................................................. 198

5.18.4 Enabling the Timers ..............................................................................199

5.18.5 Interrupt Levels....................................................................................199

5.18.6 Handling Interrupts...............................................................................199

5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors ..............................200

5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3) ............................................200

5.19.1 Data Structures in Main Memory............................................................. 200

5.19.2 Data Transfers to/from Main Memory.......................................................200

5.19.3 Data Encoding and Bit Stuffing ...............................................................200

5.19.4 Bus Protocol.........................................................................................200

5.19.4.1 Bit Ordering............................................................................200

5.19.4.2 SYNC Field .............................................................................201

5.19.4.3 Packet Field Formats................................................................201

5.19.4.4 Address Fields.........................................................................201

5.19.4.5 Frame Number Field ................................................................201

5.19.4.6 Data Field ..............................................................................201

5.19.4.7 Cyclic Redundancy Check (CRC) ................................................201

5.19.5 Packet Formats.....................................................................................201

5.19.6 USB Interrupts .....................................................................................201

5.19.6.1 Transaction-Based Interrupts ....................................................202

5.19.6.2 Non-Transaction Based Interrupts..............................................203

5.19.7 USB Power Management ........................................................................204

5.19.8 USB Legacy Keyboard Operation .............................................................204

5.20 USB EHCI Host Controller (D29:F7)....................................................................207

5.20.1 EHC Initialization ..................................................................................207

5.20.1.1 BIOS Initialization ...................................................................207

5.20.1.2 Driver Initialization ..................................................................207

5.20.1.3 EHC Resets.............................................................................208

5.20.2 Data Structures in Main Memory............................................................. 208

5.20.3 USB 2.0 Enhanced Host Controller DMA ...................................................208

5.20.4 Data Encoding and Bit Stuffing ...............................................................208

5.20.5 Packet Formats.....................................................................................208

5.20.6 USB 2.0 Interrupts and Error Conditions ..................................................209

5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads.................................209

5.20.7 USB 2.0 Power Management ..................................................................210

5.20.7.1 Pause Feature.........................................................................210

5.20.7.2 Suspend Feature .....................................................................210

5.20.7.3 ACPI Device States..................................................................210

5.20.7.4 ACPI System States.................................................................211

5.20.7.5 Mobile/Ultra Mobile Only Considerations .....................................211

5.20.8 Interaction with UHCI Host Controllers.....................................................211

5.20.8.1 Port-Routing Logic ...................................................................211

5.20.8.2 Device Connects .....................................................................213

5.20.8.3 Device Disconnects..................................................................213

5.20.8.4 Effect of Resets on Port-Routing Logic ........................................214

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5.20.9 USB 2.0 Legacy Keyboard Operation ....................................................... 214

5.20.10USB 2.0 Based Debug Port .................................................................... 214

5.20.10.1 Theory of Operation ............................................................... 215

5.21 SMBus Controller (D31:F3)............................................................................... 219

5.21.1 Host Controller..................................................................................... 220

5.21.1.1 Command Protocols ................................................................ 220

5.21.2 Bus Arbitration..................................................................................... 224

5.21.3 Bus Timing .......................................................................................... 224

5.21.3.1 Clock Stretching ..................................................................... 224

5.21.3.2 Bus Time Out (Intel® ICH7 as SMBus Master)............................. 224

5.21.4 Interrupts / SMI#................................................................................. 225

5.21.5 SMBALERT# ........................................................................................ 226

5.21.6 SMBus CRC Generation and Checking...................................................... 226

5.21.7 SMBus Slave Interface .......................................................................... 226

5.21.7.1 Format of Slave Write Cycle ..................................................... 227

5.21.7.2 Format of Read Command........................................................ 229

5.21.7.3 Format of Host Notify Command ............................................... 231

5.22 AC ’97 Controller (Audio D30:F2, Modem D30:F3) (Desktop and Mobile Only) ......... 232

5.22.1 PCI Power Management ........................................................................ 234

5.22.2 AC-Link Overview................................................................................. 234

5.22.2.1 Register Access ...................................................................... 236

5.22.3 AC-Link Low Power Mode....................................................................... 237

5.22.3.1 External Wake Event ............................................................... 238

5.22.4 AC ’97 Cold Reset................................................................................. 239

5.22.5 AC ’97 Warm Reset............................................................................... 239

5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec.......................... 239

5.23 Intel

High Definition Audio Overview................................................................ 240

5.23.1 Intel® High Definition Audio Docking (Mobile Only) ................................... 240

5.23.1.1 Dock Sequence....................................................................... 240

5.23.1.2 Exiting D3/CRST# when Docked ............................................... 241

5.23.1.3 Cold Boot/Resume from S3 When Docked .................................. 242

5.23.1.4 Undock Sequence ................................................................... 242

5.23.1.5 Interaction Between Dock/Undock and Power Management

States ................................................................................... 243

5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST# .................. 243

5.24 Intel® Active Management Technology (Intel® AMT) (Desktop and Mobile Only)....... 244

5.24.1 Intel® AMT Features ............................................................................. 244

5.24.2 Intel® AMT Requirements...................................................................... 244

5.25 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................. 245

5.25.1 SPI Arbitration between Intel® ICH7 and Intel PRO 82573E ....................... 245

5.25.2 Flash Device Configurations ................................................................... 245

5.25.3 SPI Device Compatibility Requirements ................................................... 246

5.25.3.1 Intel® ICH7 SPI Based BIOS Only Configuration Requirements

(Non-Shared Flash Configuration) ............................................. 246

5.25.3.2 Intel® ICH7 with Intel® PRO 82573E with Intel AMT Firmware

Configuration Requirements (Shared Flash Configuration) ............ 246

5.25.4 Intel® ICH7 Compatible Command Set.................................................... 247

5.25.4.1 Required Command Set for Inter Operability............................... 247

5.25.4.2 Recommended Standard Commands.......................................... 247

5.25.4.3 Multiple Page Write Usage Model............................................... 248

5.25.5 Flash Protection ................................................................................... 248

5.25.5.1 BIOS Range Write Protection .................................................... 248

5.25.5.2 SMI# Based Global Write Protection .......................................... 249

5.25.5.3 Shared Flash Address Range Protection...................................... 249

5.26 Intel® Quick Resume Technology (Digital Home Only) .......................................... 249

5.26.1 Visual Off............................................................................................ 249

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5.26.2 CE-like On/Off......................................................................................249

5.26.3 Intel® Quick Resume Technology Signals (ICH7DH Only)............................250

5.26.4 Power Button Sequence (ICH7DH Only) ...................................................250

5.27 Feature Capability Mechanism ...........................................................................251

6 Register and Memory Mapping ...............................................................................253

6.1 PCI Devices and Functions ................................................................................254

6.2 PCI Configuration Map ...................................................................................... 255

6.3 I/O Map..........................................................................................................255

6.3.1 Fixed I/O Address Ranges ......................................................................255

6.3.2 Variable I/O Decode Ranges ...................................................................258

6.4 Memory Map...................................................................................................259

6.4.1 Boot-Block Update Scheme ....................................................................261

7 Chipset Configuration Registers .............................................................................263

7.1 Chipset Configuration Registers (Memory Space)..................................................263

7.1.1 VCH—Virtual Channel Capability Header Register ......................................265

7.1.2 VCAP1—Virtual Channel Capability #1 Register .........................................265

7.1.3 VCAP2—Virtual Channel Capability #2 Register .........................................266

7.1.4 PVC—Port Virtual Channel Control Register...............................................266

7.1.5 PVS—Port Virtual Channel Status Register................................................266

7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register..............................267

7.1.7 V0CTL—Virtual Channel 0 Resource Control Register..................................267

7.1.8 V0STS—Virtual Channel 0 Resource Status Register...................................268

7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register..............................268

7.1.10 V1CTL—Virtual Channel 1 Resource Control Register..................................269

7.1.11 V1STS—Virtual Channel 1 Resource Status Register...................................269

7.1.12 RCTCL—Root Complex Topology Capabilities List Register ...........................270

7.1.13 ESD—Element Self Description Register ...................................................270

7.1.14 ULD—Upstream Link Descriptor Register ..................................................270

7.1.15 ULBA—Upstream Link Base Address Register ............................................271

7.1.16 RP1D—Root Port 1 Descriptor Register.....................................................271

7.1.17 RP1BA—Root Port 1 Base Address Register...............................................271

7.1.18 RP2D—Root Port 2 Descriptor Register.....................................................272

7.1.19 RP2BA—Root Port 2 Base Address Register...............................................272

7.1.20 RP3D—Root Port 3 Descriptor Register.....................................................272

7.1.21 RP3BA—Root Port 3 Base Address Register...............................................273

7.1.22 RP4D—Root Port 4 Descriptor Register.....................................................273

7.1.23 RP4BA—Root Port 4 Base Address Register...............................................273

7.1.24 HDD—Intel® High Definition Audio Descriptor Register...............................274

7.1.25 HDBA—Intel® High Definition Audio Base Address Register.........................274

7.1.26 RP5D—Root Port 5 Descriptor Register.....................................................274

7.1.27 RP5BA—Root Port 5 Base Address Register...............................................275

7.1.28 RP6D—Root Port 6 Descriptor Register.....................................................275

7.1.29 RP6BA—Root Port 6 Base Address Register...............................................275

7.1.30 ILCL—Internal Link Capabilities List Register.............................................276

7.1.31 LCAP—Link Capabilities Register .............................................................276

7.1.32 LCTL—Link Control Register....................................................................277

7.1.33 LSTS—Link Status Register ....................................................................277

7.1.34 RPC—Root Port Configuration Register .....................................................278

7.1.35 RPFN—Root Port Function Number for PCI Express Root Ports

(Desktop and Mobile only) .....................................................................279

7.1.36 TRSR—Trap Status Register....................................................................280

7.1.37 TRCR—Trapped Cycle Register ................................................................280

7.1.38 TWDR—Trapped Write Data Register ........................................................280

7.1.39 IOTRn — I/O Trap Register (0-3).............................................................281

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7.1.40 TCTL—TCO Configuration Register........................................................... 282

7.1.41 D31IP—Device 31 Interrupt Pin Register.................................................. 283

7.1.42 D30IP—Device 30 Interrupt Pin Register.................................................. 284

7.1.43 D29IP—Device 29 Interrupt Pin Register.................................................. 285

7.1.44 D28IP—Device 28 Interrupt Pin Register (Desktop and Mobile Only)............ 286

7.1.45 D27IP—Device 27 Interrupt Pin Register.................................................. 287

7.1.46 D31IR—Device 31 Interrupt Route Register.............................................. 287

7.1.47 D30IR—Device 30 Interrupt Route Register.............................................. 289

7.1.48 D29IR—Device 29 Interrupt Route Register.............................................. 290

7.1.49 D28IR—Device 28 Interrupt Route Register.............................................. 292

7.1.50 D27IR—Device 27 Interrupt Route Register.............................................. 293

7.1.51 OIC—Other Interrupt Control Register ..................................................... 294

7.1.52 RC—RTC Configuration Register.............................................................. 295

7.1.53 HPTC—High Precision Timer Configuration Register ................................... 295

7.1.54 GCS—General Control and Status Register............................................... 296

7.1.55 BUC—Backed Up Control Register ........................................................... 298

7.1.56 FD—Function Disable Register................................................................ 299

7.1.57 CG—Clock Gating (Mobile/Ultra Mobile Only)............................................ 301

8 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) ........................... 303

8.1 PCI Configuration Registers (LAN Controller—B1:D8:F0)....................................... 303

8.1.1 VID—Vendor Identification Register (LAN Controller—B1:D8:F0) ................. 304

8.1.2 DID—Device Identification Register (LAN Controller—B1:D8:F0) ................. 304

8.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0) .................... 305

8.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) .......................... 306

8.1.5 RID—Revision Identification Register (LAN Controller—B1:D8:F0) ............... 307

8.1.6 SCC—Sub Class Code Register (LAN Controller—B1:D8:F0)........................ 307

8.1.7 BCC—Base-Class Code Register (LAN Controller—B1:D8:F0) ...................... 307

8.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0)........................ 308

8.1.9 PMLT—Primary Master Latency Timer Register (LAN Controller—B1:D8:F0)... 308

8.1.10 HEADTYP—Header Type Register (LAN Controller—B1:D8:F0)..................... 308

8.1.11 CSR_MEM_BASE — CSR Memory-Mapped Base

Address Register (LAN Controller—B1:D8:F0)........................................... 309

8.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register

(LAN Controller—B1:D8:F0)................................................................... 309

8.1.13 SVID — Subsystem Vendor Identification (LAN Controller—B1:D8:F0) ......... 309

8.1.14 SID — Subsystem Identification (LAN Controller—B1:D8:F0)...................... 310

8.1.15 CAP_PTR — Capabilities Pointer (LAN Controller—B1:D8:F0) ...................... 310

8.1.16 INT_LN — Interrupt Line Register (LAN Controller—B1:D8:F0).................... 310

8.1.17 INT_PN — Interrupt Pin Register (LAN Controller—B1:D8:F0)..................... 311

8.1.18 MIN_GNT — Minimum Grant Register (LAN Controller—B1:D8:F0) .............. 311

8.1.19 MAX_LAT — Maximum Latency Register (LAN Controller—B1:D8:F0) ........... 311

8.1.20 CAP_ID — Capability Identification Register (LAN Controller—B1:D8:F0)...... 311

8.1.21 NXT_PTR — Next Item Pointer (LAN Controller—B1:D8:F0)........................ 312

8.1.22 PM_CAP — Power Management Capabilities (LAN Controller—B1:D8:F0)...... 312

8.1.23 PMCSR — Power Management Control/

Status Register (LAN Controller—B1:D8:F0)............................................. 313

8.1.24 PCIDATA — PCI Power Management Data Register

(LAN Controller—B1:D8:F0)................................................................... 314

8.2 LAN Control / Status Registers (CSR) (LAN Controller—B1:D8:F0).......................... 315

8.2.1 SCB_STA—System Control Block Status Word Register

(LAN Controller—B1:D8:F0)................................................................... 316

8.2.2 SCB_CMD—System Control Block Command Word

8.2.3 SCB_GENPNT—System Control Block General Pointer

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8.2.4 PORT—PORT Interface Register (LAN Controller—B1:D8:F0) .......................319

8.2.5 EEPROM_CNTL—EEPROM Control Register (LAN Controller—B1:D8:F0).........321

8.2.6 MDI_CNTL—Management Data Interface (MDI) Control

8.2.7 REC_DMA_BC—Receive DMA Byte Count Register

(LAN Controller—B1:D8:F0) ...................................................................322

8.2.8 EREC_INTR—Early Receive Interrupt Register

(LAN Controller—B1:D8:F0) ...................................................................323

8.2.9 FLOW_CNTL—Flow Control Register (LAN Controller—B1:D8:F0) .................323

8.2.10 PMDR—Power Management Driver Register (LAN Controller—B1:D8:F0).......324

8.2.11 GENCNTL—General Control Register (LAN Controller—B1:D8:F0).................325

8.2.12 GENSTA—General Status Register (LAN Controller—B1:D8:F0).................... 326

8.2.13 SMB_PCI—SMB via PCI Register (LAN Controller—B1:D8:F0)......................326

8.2.14 Statistical Counters (LAN Controller—B1:D8:F0) ....................................... 327

8.3 ASF Configuration Registers (LAN Controller—B1:D8:F0)....................................... 329

8.3.1 ASF_RID—ASF Revision Identification Register (LAN Controller—B1:D8:F0) ..330

8.3.2 SMB_CNTL—SMBus Control Register (LAN Controller—B1:D8:F0) ................330

8.3.3 ASF_CNTL—ASF Control Register (LAN Controller—B1:D8:F0) .....................331

8.3.4 ASF_CNTL_EN—ASF Control Enable Register (ASF Controller—B1:D8:F0) .....332

8.3.5 ENABLE—Enable Register (ASF Controller—B1:D8:F0) ...............................333

8.3.6 APM—APM Register (ASF Controller—B1:D8:F0)........................................334

8.3.7 WTIM_CONF—Watchdog Timer Configuration Register

(ASF Controller—B1:D8:F0) ...................................................................334

8.3.8 HEART_TIM—Heartbeat Timer Register (ASF Controller—B1:D8:F0).............335

8.3.9 RETRAN_INT—Retransmission Interval Register

(ASF Controller—B1:D8:F0) ...................................................................335

8.3.10 RETRAN_PCL—Retransmission Packet Count Limit

8.3.11 ASF_WTIM1—ASF Watchdog Timer 1 Register

(ASF Controller—B1:D8:F0) ...................................................................336

8.3.12 ASF_WTIM2—ASF Watchdog Timer 2 Register

(ASF Controller—B1:D8:F0) ...................................................................336

8.3.13 PET_SEQ1—PET Sequence 1 Register (ASF Controller—B1:D8:F0)...............337

8.3.14 PET_SEQ2—PET Sequence 2 Register (ASF Controller—B1:D8:F0)...............337

8.3.15 STA—Status Register (ASF Controller—B1:D8:F0) ..................................... 338

8.3.16 FOR_ACT—Forced Actions Register (ASF Controller—B1:D8:F0)...................339

8.3.17 RMCP_SNUM—RMCP Sequence Number Register

(ASF Controller—B1:D8:F0) ...................................................................340

8.3.18 SP_MODE—Special Modes Register (ASF Controller—B1:D8:F0) ..................340

8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register

(ASF Controller—B1:D8:F0) ...................................................................340

8.3.20 PHIST_CLR—Poll History Clear Register (ASF Controller—B1:D8:F0) ............341

8.3.21 PMSK1—Polling Mask 1 Register (ASF Controller—B1:D8:F0) ......................341

8.3.22 PMSK2—Polling Mask 2 Register (ASF Controller—B1:D8:F0) ......................342

8.3.23 PMSK3—Polling Mask 3 Register (ASF Controller—B1:D8:F0) ......................342

8.3.24 PMSK4—Polling Mask 4 Register (ASF Controller—B1:D8:F0) ......................342

8.3.25 PMSK5—Polling Mask 5 Register (ASF Controller—B1:D8:F0) ......................343

8.3.26 PMSK6—Polling Mask 6 Register (ASF Controller—B1:D8:F0) ......................343

8.3.27 PMSK7—Polling Mask 7 Register (ASF Controller—B1:D8:F0) ......................343

8.3.28 PMSK8—Polling Mask 8 Register (ASF Controller—B1:D8:F0) ......................344

9 PCI-to-PCI Bridge Registers (D30:F0)....................................................................345

9.1 PCI Configuration Registers (D30:F0) .................................................................345

9.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0).............................346

9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) .............................346

9.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0) .............................................346

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9.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0).......................................... 347

9.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................ 349

9.1.6 CC—Class Code Register (PCI-PCI—D30:F0) ............................................ 349

9.1.7 PMLT—Primary Master Latency Timer Register (PCI-PCI—D30:F0) ............... 350

9.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) ................................. 350

9.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)...................................... 350

9.1.10 SMLT—Secondary Master Latency Timer Register (PCI-PCI—D30:F0) ........... 351

9.1.11 IOBASE_LIMIT—I/O Base and Limit Register (PCI-PCI—D30:F0) ................. 351

9.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................ 352

9.1.13 MEMBASE_LIMIT—Memory Base and Limit Register (PCI-PCI—D30:F0)........ 353

9.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0) ..................................................... 353

9.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits

9.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits

9.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .......................... 354

9.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0) ........................... 354

9.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)................................... 355

9.1.20 SPDH—Secondary PCI Device Hiding Register (PCI-PCI—D30:F0)................ 356

9.1.21 DTC—Delayed Transaction Control Register (PCI-PCI—D30:F0) ................... 357

9.1.22 BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0) ....................... 359

9.1.23 BPC—Bridge Policy Configuration Register (PCI-PCI—D30:F0)..................... 360

9.1.24 SVCAP—Subsystem Vendor Capability Register (PCI-PCI—D30:F0).............. 361

9.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)......................... 361

10 LPC Interface Bridge Registers (D31:F0) ............................................................... 363

10.1 PCI Configuration Registers (LPC I/F—D31:F0).................................................... 363

10.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) .............................. 364

10.1.2 DID—Device Identification Register (LPC I/F—D31:F0) .............................. 364

10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ................................ 365

10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ....................................... 365

10.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 366

10.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 366

10.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)..................................... 367

10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0).................................... 367

10.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ............................ 367

10.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0).................................. 367

10.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0)............................. 368

10.1.12CAPP—Capability List Pointer (LPC I/F—D31:F0) ....................................... 368

10.1.13PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .......................... 368

10.1.14ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ............................. 369

10.1.15GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0)..................... 369

10.1.16GC—GPIO Control Register (LPC I/F — D31:F0) ........................................ 370

10.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) (Desktop and Mobile Only).......................................... 370

10.1.18SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) ....................... 371

10.1.19PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)................................................................................ 372

10.1.20LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0) .................. 373

10.1.21LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)................................ 374

10.1.22GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0).... 375

10.1.23GEN2_DEC—LPC I/F Generic Decode Range 2Register (LPC I/F—D31:F0)..... 375

10.1.24GEN3_DEC—LPC I/F Generic Decode Range 3Register (LPC I/F—D31:F0)..... 376

10.1.25GEN4_DEC—LPC I/F Generic Decode Range 4Register (LPC I/F—D31:F0)..... 376

10.1.26FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0) ................. 377

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10.1.27FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0)..................378

10.1.28FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) ..378

10.1.29BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) ..............................381

10.1.30FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0) ........................382

10.1.31FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0) .................. 382

10.1.32FDVER—Feature Detection Version (LPC I/F—D31:F0)................................382

10.1.33FDVCT—Feature Vector Register (LPC I/F—D31:F0) ...................................383

10.1.34RCBA—Root Complex Base Address Register (LPC I/F—D31:F0) ..................384

10.2 DMA I/O Registers (LPC I/F—D31:F0).................................................................385

10.2.1 DMABASE_CA—DMA Base and Current Address

Registers (LPC I/F—D31:F0)...................................................................386

10.2.2 DMABASE_CC—DMA Base and Current Count Registers (LPC I/F—D31:F0) ...387

10.2.3 DMAMEM_LP—DMA Memory Low Page Registers (LPC I/F—D31:F0).............387

10.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) ..............................388

10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0).....................................388

10.2.6 DMA_WRSMSK—DMA Write Single Mask Register (LPC I/F—D31:F0)............ 389

10.2.7 DMACH_MODE—DMA Channel Mode Register (LPC I/F—D31:F0) .................390

10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)...................................391

10.2.9 DMA Master Clear Register (LPC I/F—D31:F0) ..........................................391

10.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................391

10.2.11DMA_WRMSK—DMA Write All Mask Register (LPC I/F—D31:F0)...................392

10.3 Timer I/O Registers (LPC I/F—D31:F0) ...............................................................392

10.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) ...............................393

10.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register

(LPC I/F—D31:F0) ................................................................................395

10.3.3 Counter Access Ports Register (LPC I/F—D31:F0)......................................396

10.4 8259 Interrupt Controller (PIC) Registers (LPC I/F—D31:F0) .................................396

10.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0)........................................396

10.4.2 ICW1—Initialization Command Word 1 Register (LPC I/F—D31:F0)..............397

10.4.3 ICW2—Initialization Command Word 2 Register (LPC I/F—D31:F0)..............398

10.4.4 ICW3—Master Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0) .........................................................398

10.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0) .........................................................399

10.4.6 ICW4—Initialization Command Word 4 Register (LPC I/F—D31:F0)..............399

10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

10.4.8 OCW2—Operational Control Word 2 Register (LPC I/F—D31:F0) ..................400

10.4.9 OCW3—Operational Control Word 3 Register (LPC I/F—D31:F0) ..................401

10.4.10ELCR1—Master Controller Edge/Level Triggered Register (LPC I/F—D31:F0)..402

10.4.11ELCR2—Slave Controller Edge/Level Triggered Register (LPC I/F—D31:F0) ...403

10.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................404

10.5.1 APIC Register Map (LPC I/F—D31:F0)......................................................404

10.5.2 IND—Index Register (LPC I/F—D31:F0) ...................................................404

10.5.3 DAT—Data Register (LPC I/F—D31:F0) ....................................................405

10.5.4 EOIR—EOI Register (LPC I/F—D31:F0) ....................................................405

10.5.5 ID—Identification Register (LPC I/F—D31:F0) ...........................................406

10.5.6 VER—Version Register (LPC I/F—D31:F0).................................................406

10.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)......................................407

10.6 Real Time Clock Registers (LPC I/F—D31:F0).......................................................409

10.6.1 I/O Register Address Map (LPC I/F—D31:F0) ............................................409

10.6.2 Indexed Registers (LPC I/F—D31:F0) ......................................................410

10.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0) ..................................411

10.6.2.2 RTC_REGB—Register B (General Configuration) (LPC I/F—D31:F0).412

10.6.2.3 RTC_REGC—Register C (Flag Register) (LPC I/F—D31:F0).............413

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10.6.2.4 RTC_REGD—Register D (Flag Register) (LPC I/F—D31:F0)............ 414

10.7 Processor Interface Registers (LPC I/F—D31:F0) ................................................. 415

10.7.1 NMI_SC—NMI Status and Control Register (LPC I/F—D31:F0) .................... 415

10.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

10.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0) ............................. 416

10.7.4 COPROC_ERR—Coprocessor Error Register (LPC I/F—D31:F0) .................... 417

10.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0)................................. 417

10.8 Power Management Registers (PM—D31:F0) ....................................................... 418

10.8.1 Power Management PCI Configuration Registers (PM—D31:F0) ................... 418

10.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) ........................................................................ 419

10.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) ........................................................................ 420

10.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0) ........................................................................ 422

10.8.1.4 Cx-STATE_CNF—Cx State Configuration Register

(PM—D31:F0) (Mobile/Ultra Mobile Only) ................................... 424

10.8.1.5 C4-TIMING_CNT—C4 Timing Control Register

(PM—D31:F0) (Mobile/Ultra Mobile Only) ................................... 425

10.8.1.6 BM_BREAK_EN Register (PM—D31:F0) (Mobile/Ultra Mobile Only) . 426

10.8.1.7 MSC_FUN—Miscellaneous Functionality Register (PM—D31:F0)...... 427

10.8.1.8 EL_STS—Intel® Quick Resume Technology Status Register

(PM—D31:F0) (ICH7DH Only)................................................... 427

10.8.1.9 EL_CNT1—Intel® Quick Resume Technology Control 1 Register

(PM—D31:F0) (ICH7DH Only)................................................... 428

10.8.1.10EL_CNT2—Intel® Quick Resume Technology Control 2 Register

(PM—D31:F0) (ICH7DH Only)................................................... 429

10.8.1.11GPIO_ROUT—GPIO Routing Control Register (PM—D31:F0) .......... 429

10.8.2 APM I/O Decode................................................................................... 430

10.8.2.1 APM_CNT—Advanced Power Management Control Port Register..... 430

10.8.2.2 APM_STS—Advanced Power Management Status Port Register ...... 430

10.8.3 Power Management I/O Registers ........................................................... 431

10.8.3.1 PM1_STS—Power Management 1 Status Register ........................ 432

10.8.3.2 PM1_EN—Power Management 1 Enable Register.......................... 435

10.8.3.3 PM1_CNT—Power Management 1 Control ................................... 436

10.8.3.4 PM1_TMR—Power Management 1 Timer Register......................... 437

10.8.3.5 PROC_CNT—Processor Control Register...................................... 437

10.8.3.6 LV2 — Level 2 Register (Mobile/Ultra Mobile Only)....................... 439

10.8.3.7 LV3—Level 3 Register (Mobile/Ultra Mobile Only)......................... 439

10.8.3.8 LV4—Level 4 Register (Mobile/Ultra Mobile Only)......................... 439

10.8.3.9 PM2_CNT—Power Management 2 Control Register

(Mobile/Ultra Mobile Only)........................................................ 440

10.8.3.10GPE0_STS—General Purpose Event 0 Status Register .................. 440

10.8.3.11GPE0_EN—General Purpose Event 0 Enables Register .................. 444

10.8.3.12SMI_EN—SMI Control and Enable Register ................................. 447

10.8.3.13SMI_STS—SMI Status Register ................................................. 449

10.8.3.14ALT_GP_SMI_EN—Alternate GPI SMI Enable Register................... 452

10.8.3.15ALT_GP_SMI_STS—Alternate GPI SMI Status Register.................. 452

10.8.3.16GPE_CNTL— General Purpose Control Register............................ 453

10.8.3.17DEVACT_STS — Device Activity Status Register .......................... 454

10.8.3.18SS_CNT— Intel SpeedStep® Technology

Control Register (Mobile/Ultra Mobile Only) ................................ 455

10.8.3.19C3_RES— C3 Residency Register (Mobile/Ultra Mobile Only) ......... 455

10.9 System Management TCO Registers (D31:F0) ..................................................... 456

10.9.1 TCO_RLD—TCO Timer Reload and Current Value Register........................... 456

10.9.2 TCO_DAT_IN—TCO Data In Register........................................................ 457

10.9.3 TCO_DAT_OUT—TCO Data Out Register ................................................... 457

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10.9.4 TCO1_STS—TCO1 Status Register ...........................................................457

10.9.5 TCO2_STS—TCO2 Status Register ...........................................................459

10.9.6 TCO1_CNT—TCO1 Control Register..........................................................460

10.9.7 TCO2_CNT—TCO2 Control Register..........................................................461

10.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers........................................461

10.9.9 TCO_WDCNT—TCO Watchdog Control Register ..........................................462

10.9.10SW_IRQ_GEN—Software IRQ Generation Register .....................................462

10.9.11TCO_TMR—TCO Timer Initial Value Register..............................................462

10.10 General Purpose I/O Registers (D31:F0) .............................................................463

10.10.1GPIO_USE_SEL—GPIO Use Select Register ...............................................464

10.10.2GP_IO_SEL—GPIO Input/Output Select Register........................................464

10.10.3GP_LVL—GPIO Level for Input or Output Register ......................................465

10.10.4GPO_BLINK—GPO Blink Enable Register...................................................465

10.10.5GPI_INV—GPIO Signal Invert Register .....................................................466

10.10.6GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]................................466

10.10.7GP_IO_SEL2—GPIO Input/Output Select 2 Register[63:32] ........................ 467

10.10.8GP_LVL2—GPIO Level for Input or Output 2 Register[63:32]....................... 467

11 UHCI Controllers Registers ....................................................................................469

11.1 PCI Configuration Registers (USB—D29:F0/F1/F2/F3) ........................................... 469

11.1.1 VID—Vendor Identification Register (USB—D29:F0/F1/F2/F3).....................470

11.1.2 DID—Device Identification Register (USB—D29:F0/F1/F2/F3) ..................... 470

11.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2/F3) ........................470

11.1.4 PCISTS—PCI Status Register (USB—D29:F0/F1/F2/F3) ..............................471

11.1.5 RID—Revision Identification Register (USB—D29:F0/F1/F2/F3) ...................471

11.1.6 PI—Programming Interface Register (USB—D29:F0/F1/F2/F3) ....................472

11.1.7 SCC—Sub Class Code Register (USB—D29:F0/F1/F2/F3) ............................472

11.1.8 BCC—Base Class Code Register (USB—D29:F0/F1/F2/F3)...........................472

11.1.9 MLT—Master Latency Timer Register (USB—D29:F0/F1/F2/F3) ....................473

11.1.10HEADTYP—Header Type Register (USB—D29:F0/F1/F2/F3) ......................... 473

11.1.11BASE—Base Address Register (USB—D29:F0/F1/F2/F3) ............................. 474

11.1.12SVID — Subsystem Vendor Identification Register (USB—D29:F0/F1/F2/F3) .474

11.1.13SID — Subsystem Identification Register (USB—D29:F0/F1/F2/F3) .............474

11.1.14INT_LN—Interrupt Line Register (USB—D29:F0/F1/F2/F3)..........................475

11.1.15INT_PN—Interrupt Pin Register (USB—D29:F0/F1/F2/F3)...........................475

11.1.16USB_RELNUM—Serial Bus Release Number Register

(USB—D29:F0/F1/F2/F3).......................................................................475

11.1.17USB_LEGKEY—USB Legacy Keyboard/Mouse Control

11.1.18USB_RES—USB Resume Enable Register (USB—D29:F0/F1/F2/F3)..............478

11.1.19CWP—Core Well Policy Register (USB—D29:F0/F1/F2/F3)...........................478

11.2 USB I/O Registers............................................................................................479

11.2.1 USBCMD—USB Command Register.......................................................... 480

11.2.2 USBSTS—USB Status Register ................................................................483

11.2.3 USBINTR—USB Interrupt Enable Register .................................................484

11.2.4 FRNUM—Frame Number Register ............................................................484

11.2.5 FRBASEADD—Frame List Base Address Register........................................485

11.2.6 SOFMOD—Start of Frame Modify Register ................................................486

11.2.7 PORTSC[0,1]—Port Status and Control Register ........................................487

12 SATA Controller Registers (D31:F2) (Desktop and Mobile Only)............................. 489

12.1 PCI Configuration Registers (SATA–D31:F2).........................................................489

12.1.1 VID—Vendor Identification Register (SATA—D31:F2)..................................491

12.1.2 DID—Device Identification Register (SATA—D31:F2)..................................491

12.1.3 PCICMD—PCI Command Register (SATA–D31:F2)......................................491

12.1.4 PCISTS — PCI Status Register (SATA–D31:F2)..........................................492

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12.1.5 RID—Revision Identification Register (SATA—D31:F2) ............................... 493

12.1.6 PI—Programming Interface Register (SATA–D31:F2) ................................. 493

12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h........... 493

12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h........... 494

12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h........... 494

12.1.7 SCC—Sub Class Code Register (SATA–D31:F2)......................................... 495

12.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2)..................... 495

12.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2).................... 495

12.1.10PCMD_BAR—Primary Command Block Base Address

12.1.11PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2) .................................................................................... 496

12.1.12SCMD_BAR—Secondary Command Block Base Address

12.1.13SCNL_BAR—Secondary Control Block Base Address

12.1.14BAR — Legacy Bus Master Base Address Register (SATA–D31:F2) ............... 497

12.1.15ABAR — AHCI Base Address Register (SATA–D31:F2)................................ 497

12.1.15.1Non AHCI Capable (Intel® ICH7 Feature Supported

Components Only) .................................................................. 497

12.1.15.2AHCI Capable (Intel® ICH7R, ICH7DH, and Mobile Only).............. 498

12.1.16SVID—Subsystem Vendor Identification Register (SATA–D31:F2) ................ 498

12.1.17SID—Subsystem Identification Register (SATA–D31:F2)............................. 498

12.1.18CAP—Capabilities Pointer Register (SATA–D31:F2) .................................... 499

12.1.19INT_LN—Interrupt Line Register (SATA–D31:F2)....................................... 499

12.1.20INT_PN—Interrupt Pin Register (SATA–D31:F2) ........................................ 499

12.1.21IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2).......................... 499

12.1.22IDE_TIMS — Slave IDE Timing Register (SATA–D31:F2)............................. 501

12.1.23SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2)................. 502

12.1.24SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2).................. 503

12.1.25IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2) .................... 504

12.1.26PID—PCI Power Management Capability Identification

12.1.27PC—PCI Power Management Capabilities Register (SATA–D31:F2)............... 506

12.1.28PMCS—PCI Power Management Control and Status

12.1.29MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 507

12.1.30MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2)......... 507

12.1.31MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2) ....... 508

12.1.32MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............ 509

12.1.33MAP—Address Map Register (SATA–D31:F2)............................................. 509

12.1.34PCS—Port Control and Status Register (SATA–D31:F2) .............................. 510

12.1.35SIR—SATA Initialization Register............................................................. 511

12.1.36SIRI—SATA Indexed Registers Index....................................................... 512

12.1.37STRD—SATA Indexed Register Data ........................................................ 512

12.1.37.1STTT1—SATA Indexed Registers Index 00h

(SATA TX Termination Test Register 1) ....................................... 513

12.1.37.2STME—SATA Indexed Registers Index C1h

(SATA Test Mode Enable Register) ............................................. 513

12.1.37.3STTT2 — SATA Indexed Registers Index 74h

(SATA TX Termination Test Register 2) ....................................... 514

12.1.38SCAP0—SATA Capability Register 0 (SATA–D31:F2)................................... 514

12.1.39SCAP1—SATA Capability Register 1 (SATA–D31:F2)................................... 515

12.1.40ATC—APM Trapping Control Register (SATA–D31:F2) ................................. 516

12.1.41ATS—APM Trapping Status Register (SATA–D31:F2) .................................. 516

12.1.42SP — Scratch Pad Register (SATA–D31:F2) .............................................. 516

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12.1.43BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ............................517

12.1.44BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ......................... 518

12.1.45BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ......................... 519

12.2 Bus Master IDE I/O Registers (D31:F2)...............................................................519

12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)...........................520

12.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ................................521

12.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2)........522

12.2.4 AIR—AHCI Index Register (D31:F2).........................................................522

12.2.5 AIDR—AHCI Index Data Register (D31:F2) ...............................................522

12.3 AHCI Registers (D31:F2) (Intel® ICH7R, ICH7DH, ICH7-M, and ICH7-M DH Only) .... 523

12.3.1 AHCI Generic Host Control Registers (D31:F2)..........................................524

12.3.1.1 CAP—Host Capabilities Register (D31:F2) ...................................524

12.3.1.2 GHC—Global ICH7 Control Register (D31:F2) ..............................526

12.3.1.3 IS—Interrupt Status Register (D31:F2) ......................................527

12.3.1.4 PI—Ports Implemented Register (D31:F2)...................................528

12.3.1.5 VS—AHCI Version (D31:F2) ......................................................528

12.3.2 Port Registers (D31:F2) .........................................................................529

12.3.2.1 PxCLB—Port [3:0] Command List Base Address Register (D31:F2) .531

12.3.2.2 PxCLBU—Port [3:0] Command List Base Address Upper

32-Bits Register (D31:F2).........................................................531

12.3.2.3 PxFB—Port [3:0] FIS Base Address Register (D31:F2) ..................531

12.3.2.4 PxFBU—Port [3:0] FIS Base Address Upper 32-Bits

12.3.2.5 PxIS—Port [3:0] Interrupt Status Register (D31:F2) ....................532

12.3.2.6 PxIE—Port [3:0] Interrupt Enable Register (D31:F2) ....................533

12.3.2.7 PxCMD—Port [3:0] Command Register (D31:F2) .........................535

12.3.2.8 PxTFD—Port [3:0] Task File Data Register (D31:F2) .....................538

12.3.2.9 PxSIG—Port [3:0] Signature Register (D31:F2) ...........................538

12.3.2.10PxSSTS—Port [3:0] Serial ATA Status Register (D31:F2)...............539

12.3.2.11PxSCTL — Port [3:0] Serial ATA Control Register (D31:F2)............540

12.3.2.12PxSERR—Port [3:0] Serial ATA Error Register (D31:F2).................541

12.3.2.13PxSACT—Port [3:0] Serial ATA Active (D31:F2) ...........................542

12.3.2.14PxCI—Port [3:0] Command Issue Register (D31:F2) ....................543

13 EHCI Controller Registers (D29:F7) ....................................................................... 545

13.1 USB EHCI Configuration Registers

(USB EHCI—D29:F7)........................................................................................545

13.1.1 VID—Vendor Identification Register (USB EHCI—D29:F7)...........................546

13.1.2 DID—Device Identification Register (USB EHCI—D29:F7) ...........................546

13.1.3 PCICMD—PCI Command Register (USB EHCI—D29:F7) ..............................547

13.1.4 PCISTS—PCI Status Register (USB EHCI—D29:F7) ....................................548

13.1.5 RID—Revision Identification Register (USB EHCI—D29:F7) .........................549

13.1.6 PI—Programming Interface Register (USB EHCI—D29:F7) ..........................549

13.1.7 SCC—Sub Class Code Register (USB EHCI—D29:F7)..................................549

13.1.8 BCC—Base Class Code Register (USB EHCI—D29:F7) ................................549

13.1.9 PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F7).............550

13.1.10MEM_BASE—Memory Base Address Register (USB EHCI—D29:F7)...............550

13.1.11SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F7) .........550

13.1.12SID—USB EHCI Subsystem ID Register (USB EHCI—D29:F7)......................551

13.1.13CAP_PTR—Capabilities Pointer Register (USB EHCI—D29:F7) ......................551

13.1.14INT_LN—Interrupt Line Register (USB EHCI—D29:F7) ...............................551

13.1.15INT_PN—Interrupt Pin Register (USB EHCI—D29:F7).................................551

13.1.16PWR_CAPID—PCI Power Management Capability ID

13.1.17NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—D29:F7).................552

13.1.18PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F7).............................................................................552

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13.1.19PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F7) ...................................................... 553

13.1.20DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F7)...... 554

13.1.21NXT_PTR2—Next Item Pointer #2 Register (USB EHCI—D29:F7) ................ 554

13.1.22DEBUG_BASE—Debug Port Base Offset Register (USB EHCI—D29:F7) ......... 554

13.1.23USB_RELNUM—USB Release Number Register (USB EHCI—D29:F7)............ 555

13.1.24FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F7) .............. 555

13.1.25PWAKE_CAP—Port Wake Capability Register (USB EHCI—D29:F7)............... 556

13.1.26LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F7).................................................. 556

13.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F7) ......................................... 557

13.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7) ..... 559

13.1.29ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7) .................... 560

13.2 Memory-Mapped I/O Registers .......................................................................... 561

13.2.1 Host Controller Capability Registers ........................................................ 561

13.2.1.1 CAPLENGTH—Capability Registers Length Register....................... 561

13.2.1.2 HCIVERSION—Host Controller Interface Version Number

13.2.1.3 HCSPARAMS—Host Controller Structural Parameters.................... 562

13.2.1.4 HCCPARAMS—Host Controller Capability Parameters Register........ 563

13.2.2 Host Controller Operational Registers...................................................... 564

13.2.2.1 USB2.0_CMD—USB 2.0 Command Register ................................ 565

13.2.2.2 USB2.0_STS—USB 2.0 Status Register ...................................... 568

13.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register ....................... 570

13.2.2.4 FRINDEX—Frame Index Register ............................................... 571

13.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register........ 572

13.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address Register.... 572

13.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address Register ..... 573

13.2.2.8 CONFIGFLAG—Configure Flag Register....................................... 573

13.2.2.9 PORTSC—Port N Status and Control Register .............................. 573

13.2.3 USB 2.0-Based Debug Port Register ........................................................ 577

13.2.3.1 CNTL_STS—Control/Status Register .......................................... 577

13.2.3.2 USBPID—USB PIDs Register ..................................................... 580

13.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ......................... 581

13.2.3.4 CONFIG—Configuration Register ............................................... 581

14 SMBus Controller Registers (D31:F3) .................................................................... 583

14.1 PCI Configuration Registers (SMBUS—D31:F3) .................................................... 583

14.1.1 VID—Vendor Identification Register (SMBUS—D31:F3) .............................. 583

14.1.2 DID—Device Identification Register (SMBUS—D31:F3) .............................. 584

14.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3) ................................. 584

14.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3) ....................................... 585

14.1.5 RID—Revision Identification Register (SMBUS—D31:F3) ............................ 585

14.1.6 PI—Programming Interface Register (SMBUS—D31:F3) ............................. 586

14.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3)..................................... 586

14.1.8 BCC—Base Class Code Register (SMBUS—D31:F3).................................... 586

14.1.9 SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3) ................... 586

14.1.10SVID — Subsystem Vendor Identification Register (SMBUS—D31:F2/F4) ..... 587

14.1.11SID — Subsystem Identification Register (SMBUS—D31:F2/F4) .................. 587

14.1.12INT_LN—Interrupt Line Register (SMBUS—D31:F3)................................... 587

14.1.13INT_PN—Interrupt Pin Register (SMBUS—D31:F3) .................................... 587

14.1.14HOSTC—Host Configuration Register (SMBUS—D31:F3)............................. 588

14.2 SMBus I/O Registers........................................................................................ 588

14.2.1 HST_STS—Host Status Register (SMBUS—D31:F3) ................................... 589

14.2.2 HST_CNT—Host Control Register (SMBUS—D31:F3).................................. 591

14.2.3 HST_CMD—Host Command Register (SMBUS—D31:F3)............................. 593

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14.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBUS—D31:F3).................593

14.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3).....................................593

14.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3).....................................593

14.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBUS—D31:F3) ............594

14.2.8 PEC—Packet Error Check (PEC) Register (SMBUS—D31:F3) ........................594

14.2.9 RCV_SLVA—Receive Slave Address Register (SMBUS—D31:F3) ...................595

14.2.10SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3)........................595

14.2.11AUX_STS—Auxiliary Status Register (SMBUS—D31:F3)..............................595

14.2.12AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3) .............................596

14.2.13SMLINK_PIN_CTL—SMLink Pin Control Register (SMBUS—D31:F3) ..............596

14.2.14SMBUS_PIN_CTL—SMBUS Pin Control Register (SMBUS—D31:F3) ...............597

14.2.15SLV_STS—Slave Status Register (SMBUS—D31:F3)...................................597

14.2.16SLV_CMD—Slave Command Register (SMBUS—D31:F3).............................598

14.2.17NOTIFY_DADDR—Notify Device Address Register (SMBUS—D31:F3) ............598

14.2.18NOTIFY_DLOW—Notify Data Low Byte Register (SMBUS—D31:F3)...............599

14.2.19NOTIFY_DHIGH—Notify Data High Byte Register (SMBUS—D31:F3).............599

15 IDE Controller Registers (D31:F1)..........................................................................601

15.1 PCI Configuration Registers (IDE—D31:F1) .........................................................601

15.1.1 VID—Vendor Identification Register (IDE—D31:F1)....................................602

15.1.2 DID—Device Identification Register (IDE—D31:F1)....................................602

15.1.3 PCICMD—PCI Command Register (IDE—D31:F1).......................................602

15.1.4 PCISTS — PCI Status Register (IDE—D31:F1)........................................... 603

15.1.5 RID—Revision Identification Register (IDE—D31:F1)..................................603

15.1.6 PI—Programming Interface Register (IDE—D31:F1)...................................604

15.1.7 SCC—Sub Class Code Register (IDE—D31:F1) ..........................................604

15.1.8 BCC—Base Class Code Register (IDE—D31:F1) .........................................604

15.1.9 CLS—Cache Line Size Register (IDE—D31:F1) ..........................................604

15.1.10PMLT—Primary Master Latency Timer Register (IDE—D31:F1) .....................605

15.1.11PCMD_BAR—Primary Command Block Base Address

15.1.12PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) .....605

15.1.13SCMD_BAR—Secondary Command Block Base Address

15.1.14SCNL_BAR—Secondary Control Block Base Address

15.1.15BM_BASE — Bus Master Base Address Register (IDE—D31:F1) ...................607

15.1.16IDE_SVID — Subsystem Vendor Identification (IDE—D31:F1) .....................607

15.1.17IDE_SID — Subsystem Identification Register (IDE—D31:F1) .....................607

15.1.18INTR_LN—Interrupt Line Register (IDE—D31:F1) ...................................... 608

15.1.19INTR_PN—Interrupt Pin Register (IDE—D31:F1)........................................ 608

15.1.20IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1)........................... 608

15.1.21IDE_TIMS — IDE Secondary Timing Register (IDE—D31:F1).......................610

15.1.22SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1) (Desktop and Mobile Only) ...............................................610

15.1.23SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1)..................611

15.1.24SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1)...................611

15.1.25IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)......................612

15.1.26ATC—APM Trapping Control Register (IDE—D31:F1)...................................614

15.1.27ATS—APM Trapping Status Register (IDE—D31:F1).................................... 614

15.2 Bus Master IDE I/O Registers (IDE—D31:F1).......................................................615

15.2.1 BMICP—Bus Master IDE Command Register (IDE—D31:F1) ........................615

15.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1) .............................616

15.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register (IDE—D31:F1) ..... 617

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16 AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)................. 619

16.1 AC ’97 Audio PCI Configuration Space (Audio—D30:F2)........................................ 619

16.1.1 VID—Vendor Identification Register (Audio—D30:F2) ................................ 620

16.1.2 DID—Device Identification Register (Audio—D30:F2)................................. 620

16.1.3 PCICMD—PCI Command Register (Audio—D30:F2) ................................... 621

16.1.4 PCISTS—PCI Status Register (Audio—D30:F2) ......................................... 622

16.1.5 RID—Revision Identification Register (Audio—D30:F2) .............................. 622

16.1.6 PI—Programming Interface Register (Audio—D30:F2) ............................... 623

16.1.7 SCC—Sub Class Code Register (Audio—D30:F2) ....................................... 623

16.1.8 BCC—Base Class Code Register (Audio—D30:F2)...................................... 623

16.1.9 HEADTYP—Header Type Register (Audio—D30:F2) .................................... 623

16.1.10NAMBAR—Native Audio Mixer Base Address Register (Audio—D30:F2) ......... 624

16.1.11NABMBAR—Native Audio Bus Mastering Base Address

16.1.12MMBAR—Mixer Base Address Register (Audio—D30:F2)............................. 625

16.1.13MBBAR—Bus Master Base Address Register (Audio—D30:F2)...................... 626

16.1.14SVID—Subsystem Vendor Identification Register (Audio—D30:F2) .............. 626

16.1.15SID—Subsystem Identification Register (Audio—D30:F2)........................... 627

16.1.16CAP_PTR—Capabilities Pointer Register (Audio—D30:F2) ........................... 627

16.1.17INT_LN—Interrupt Line Register (Audio—D30:F2)..................................... 627

16.1.18INT_PN—Interrupt Pin Register (Audio—D30:F2) ...................................... 628

16.1.19PCID—Programmable Codec Identification Register (Audio—D30:F2)........... 628

16.1.20CFG—Configuration Register (Audio—D30:F2) .......................................... 628

16.1.21PID—PCI Power Management Capability Identification

16.1.22PC—Power Management Capabilities Register (Audio—D30:F2)................... 629

16.1.23PCS—Power Management Control and Status Register (Audio—D30:F2)....... 630

16.2 AC ’97 Audio I/O Space (D30:F2) ...................................................................... 631

16.2.1 x_BDBAR—Buffer Descriptor Base Address Register (Audio—D30:F2) .......... 635

16.2.2 x_CIV—Current Index Value Register (Audio—D30:F2) .............................. 635

16.2.3 x_LVI—Last Valid Index Register (Audio—D30:F2) .................................... 636

16.2.4 x_SR—Status Register (Audio—D30:F2) .................................................. 636

16.2.5 x_PICB—Position In Current Buffer Register (Audio—D30:F2)..................... 638

16.2.6 x_PIV—Prefetched Index Value Register (Audio—D30:F2) .......................... 638

16.2.7 x_CR—Control Register (Audio—D30:F2) ................................................. 639

16.2.8 GLOB_CNT—Global Control Register (Audio—D30:F2)................................ 640

16.2.9 GLOB_STA—Global Status Register (Audio—D30:F2) ................................. 642

16.2.10CAS—Codec Access Semaphore Register (Audio—D30:F2) ......................... 644

16.2.11SDM—SDATA_IN Map Register (Audio—D30:F2) ....................................... 645

17 AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)............... 647

17.1 AC ’97 Modem PCI Configuration Space (D30:F3) ................................................ 647

17.1.1 VID—Vendor Identification Register (Modem—D30:F3) .............................. 648

17.1.2 DID—Device Identification Register (Modem—D30:F3) .............................. 648

17.1.3 PCICMD—PCI Command Register (Modem—D30:F3) ................................. 648

17.1.4 PCISTS—PCI Status Register (Modem—D30:F3) ....................................... 649

17.1.5 RID—Revision Identification Register (Modem—D30:F3) ............................ 650

17.1.6 PI—Programming Interface Register (Modem—D30:F3) ............................. 650

17.1.7 SCC—Sub Class Code Register (Modem—D30:F3) ..................................... 650

17.1.8 BCC—Base Class Code Register (Modem—D30:F3).................................... 650

17.1.9 HEADTYP—Header Type Register (Modem—D30:F3) .................................. 650

17.1.10MMBAR—Modem Mixer Base Address Register (Modem—D30:F3)................ 651

17.1.11MBAR—Modem Base Address Register (Modem—D30:F3)........................... 651

17.1.12SVID—Subsystem Vendor Identification Register (Modem—D30:F3) ............ 652

17.1.13SID—Subsystem Identification Register (Modem—D30:F3) ........................ 652

Intel ® ICH7 Family Datasheet 21

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17.1.14CAP_PTR—Capabilities Pointer Register (Modem—D30:F3)..........................652

17.1.15INT_LN—Interrupt Line Register (Modem—D30:F3) ...................................653

17.1.16INT_PIN—Interrupt Pin Register (Modem—D30:F3) ...................................653

17.1.17PID—PCI Power Management Capability Identification

17.1.18PC—Power Management Capabilities Register (Modem—D30:F3) .................654

17.1.19PCS—Power Management Control and Status Register (Modem—D30:F3).....654

17.2 AC ’97 Modem I/O Space (D30:F3) ....................................................................655

17.2.1 x_BDBAR—Buffer Descriptor List Base Address Register (Modem—D30:F3)...657

17.2.2 x_CIV—Current Index Value Register (Modem—D30:F3) ............................657

17.2.3 x_LVI—Last Valid Index Register (Modem—D30:F3)...................................657

17.2.4 x_SR—Status Register (Modem—D30:F3).................................................658

17.2.5 x_PICB—Position in Current Buffer Register (Modem—D30:F3) ...................659

17.2.6 x_PIV—Prefetch Index Value Register (Modem—D30:F3)............................659

17.2.7 x_CR—Control Register (Modem—D30:F3) ...............................................660

17.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3)..............................661

17.2.9 GLOB_STA—Global Status Register (Modem—D30:F3) ...............................662

17.2.10CAS—Codec Access Semaphore Register (Modem—D30:F3) .......................664

18 PCI Express* Configuration Registers (Desktop and Mobile Only)..........................665

18.1 PCI Express* Configuration Registers

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ..............................................................665

18.1.1 VID—Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................667

18.1.2 DID—Device Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................667

18.1.3 PCICMD—PCI Command Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................667

18.1.4 PCISTS—PCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................668

18.1.5 RID—Revision Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................669

18.1.6 PI—Programming Interface Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................669

18.1.7 SCC—Sub Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................669

18.1.8 BCC—Base Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................670

18.1.9 CLS—Cache Line Size Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................670

18.1.10PLT—Primary Latency Timer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................670

18.1.11HEADTYP—Header Type Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................670

18.1.12BNUM—Bus Number Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................671

18.1.13IOBL—I/O Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................671

18.1.14SSTS—Secondary Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................672

18.1.15MBL—Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................673

18.1.16PMBL—Prefetchable Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................673

18.1.17PMBU32—Prefetchable Memory Base Upper 32 Bits

22 Intel ® ICH7 Family Datasheet

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18.1.18PMLU32—Prefetchable Memory Limit Upper 32 Bits

18.1.19CAPP—Capabilities List Pointer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 674

18.1.20INTR—Interrupt Information Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 675

18.1.21BCTRL—Bridge Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 676

18.1.22CLIST—Capabilities List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 677

18.1.23XCAP—PCI Express* Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 677

18.1.24DCAP—Device Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 678

18.1.25DCTL—Device Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 679

18.1.26DSTS—Device Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 680

18.1.27LCAP—Link Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 681

18.1.28LCTL—Link Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 682

18.1.29LSTS—Link Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ............ 683

18.1.30SLCAP—Slot Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 684

18.1.31SLCTL—Slot Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5).......... 685

18.1.32SLSTS—Slot Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)........... 686

18.1.33RCTL—Root Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)........... 687

18.1.34RSTS—Root Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ........... 687

18.1.35MID—Message Signaled Interrupt Identifiers Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 688

18.1.36MC—Message Signaled Interrupt Message Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 688

18.1.37MA—Message Signaled Interrupt Message Address

18.1.38MD—Message Signaled Interrupt Message Data Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.39SVCAP—Subsystem Vendor Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.40SVID—Subsystem Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.41PMCAP—Power Management Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.42PMC—PCI Power Management Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 690

18.1.43PMCS—PCI Power Management Control and Status

18.1.44MPC—Miscellaneous Port Configuration Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 691

18.1.45SMSCS—SMI/SCI Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ... 693

18.1.46RPDCGEN - Root Port Dynamic Clock Gating Enable

(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)................................. 694

18.1.47IPWS—Intel® PRO/Wireless 3945ABG Status

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Mobile Only) ............................... 694

18.1.48VCH—Virtual Channel Capability Header Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 695

Intel ® ICH7 Family Datasheet 23

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18.1.49VCAP2—Virtual Channel Capability 2 Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................695

18.1.50PVC—Port Virtual Channel Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................695

18.1.51PVS — Port Virtual Channel Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................696

18.1.52V0CAP — Virtual Channel 0 Resource Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................696

18.1.53V0CTL — Virtual Channel 0 Resource Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................697

18.1.54V0STS — Virtual Channel 0 Resource Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................697

18.1.55UES — Uncorrectable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................698

18.1.56UEM — Uncorrectable Error Mask

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................699

18.1.57UEV — Uncorrectable Error Severity

Q(PCI Express—D28:F0/F1/F2/F3/F4/F5).................................................700

18.1.58CES — Correctable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................701

18.1.59CEM — Correctable Error Mask Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................701

18.1.60AECC — Advanced Error Capabilities and Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................702

18.1.61RES — Root Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................702

18.1.62RCTCL — Root Complex Topology Capability List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................703

18.1.63ESD — Element Self Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................703

18.1.64ULD — Upstream Link Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................704

18.1.65ULBA — Upstream Link Base Address Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................704

18.1.66PEETM — PCI Express Extended Test Mode Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................................704

19 Intel® High Definition Audio Controller Registers (D27:F0)....................................705

19.1 Intel® High Definition Audio PCI Configuration Space (Intel® High Definition

Audio— D27:F0)..............................................................................................705

19.1.1 VID—Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0) .....................................707

19.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0) .....................................707

19.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0) .....................................708

19.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................709

19.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0) .....................................709

19.1.6 PI—Programming Interface Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

19.1.7 SCC—Sub Class Code Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

19.1.8 BCC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

19.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

24 Intel ® ICH7 Family Datasheet

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19.1.10LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 710

19.1.11HEADTYP—Header Type Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 711

19.1.12HDBARL—Intel® High Definition Audio Lower Base Address Register

(Intel® High Definition Audio—D27:F0) ................................................... 711

19.1.13HDBARU—Intel® High Definition Audio Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 711

19.1.14SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 712

19.1.15SID—Subsystem Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 712

19.1.16CAPPTR—Capabilities Pointer Register (Audio—D30:F2) ............................. 713

19.1.17INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 713

19.1.18INTPN—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 713

19.1.19HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 714

19.1.20TCSEL—Traffic Class Select Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 715

19.1.21DCKCTL—Docking Control Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0)..................................... 715

19.1.22DCKSTS—Docking Status Register

(Intel® High Definition Audio Controller—D27:F0) (Mobile Only) ................. 716

19.1.23PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 716

19.1.24PC—Power Management Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 716

19.1.25PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 717

19.1.26MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.27MMC—MSI Message Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.28MMLA—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.29MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.30MMD—MSI Message Data Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 719

19.1.31PXID—PCI Express* Capability ID Register (Intel® High Definition Audio Controller—D27:F0) (Desktop and Mobile Only)719

19.1.32PXC—PCI Express* Capabilities Register (Desktop and Mobile Only)

(Intel® High Definition Audio Controller—D27:F0)..................................... 719

19.1.33DEVCAP—Device Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 720

19.1.34DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 721

19.1.35DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 721

19.1.36VCCAP—Virtual Channel Enhanced Capability Header (Intel® High Definition Audio Controller—D27:F0)

(Desktop and Mobile Only) .................................................................... 722

19.1.37PVCCAP1—Port VC Capability Register 1 (Intel

High Definition Audio Controller—D27:F0)

(Desktop and Mobile Only) .................................................................... 722

Intel ® ICH7 Family Datasheet 25

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19.1.38PVCCAP2 — Port VC Capability Register 2

(Intel® High Definition Audio Controller—D27:F0) .....................................722

19.1.39PVCCTL — Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................723

19.1.40PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................723

19.1.41VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .....................................723

19.1.42VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................724

19.1.43VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................724

19.1.44VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .....................................725

19.1.45VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................725

19.1.46VCiSTS—VCi Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................726

19.1.47RCCAP—Root Complex Link Declaration Enhanced Capability Header Register (Intel® High Definition Audio

Controller—D27:F0) (Desktop and Mobile Only) ........................................726

19.1.48ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0) .....................................726

19.1.49L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0) .....................................727

19.1.50L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0) .....................................727

19.1.51L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0) .....................................727

19.2 Intel® High Definition Audio Memory-Mapped Configuration Registers

(Intel® High Definition Audio— D27:F0)..............................................................728

19.2.1 GCAP—Global Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .....................................732

19.2.2 VMIN—Minor Version Register

(Intel® High Definition Audio Controller—D27:F0) .....................................732

19.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0) .....................................732

19.2.4 OUTPAY—Output Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0) .....................................733

19.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0) .....................................733

19.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................734

19.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0) .....................................735

19.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................735

19.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................736

19.2.10ECAP—Extended Capabilities

(Intel® High Definition Audio Controller—D27:F0) .....................................737

19.2.11OUTSTRMPAY—Output Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0) .....................................737

19.2.12INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0) .....................................738

19.2.13INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................739

26 Intel ® ICH7 Family Datasheet

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19.2.14INTSTS—Interrupt Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 740

19.2.15WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 741

19.2.16SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 741

19.2.17CORBLBASE—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 742

19.2.18CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 742

19.2.19CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 742

19.2.20CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 743

19.2.21CORBCTL—CORB Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 743

19.2.22CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 744

19.2.23CORBSIZE—CORB Size Register

Intel® High Definition Audio Controller—D27:F0) ...................................... 744

19.2.24RIRBLBASE—RIRB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 744

19.2.25RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 745

19.2.26RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 745

19.2.27RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 746

19.2.28RIRBCTL—RIRB Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 746

19.2.29RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 747

19.2.30RIRBSIZE—RIRB Size Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 747

19.2.31IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 747

19.2.32IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 748

19.2.33IRS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 748

19.2.34DPLBASE—DMA Position Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 749

19.2.35DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 749

19.2.36SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 750

19.2.37SDSTS—Stream Descriptor Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 752

19.2.38SDLPIB—Stream Descriptor Link Position in Buffer

19.2.39SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 753

19.2.40SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 754

19.2.41SDFIFOW—Stream Descriptor FIFO Watermark Register (Intel

High Definition Audio Controller—D27:F0)..................................... 754

Intel ® ICH7 Family Datasheet 27

Page 28

19.2.42SDFIFOS—Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0) .....................................755

19.2.43SDFMT—Stream Descriptor Format Register

(Intel® High Definition Audio Controller—D27:F0) .....................................756

19.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base

Address Register (Intel® High Definition Audio Controller—D27:F0) ............. 757

19.2.45SDBDPU—Stream Descriptor Buffer Descriptor List PointerUpper Base

Address Register (Intel® High Definition Audio Controller—D27:F0) ............. 757

20 High Precision Event Timer Registers.....................................................................759

20.1 Memory Mapped Registers ................................................................................759

20.1.1 GCAP_ID—General Capabilities and Identification Register..........................760

20.1.2 GEN_CONF—General Configuration Register .............................................761

20.1.3 GINTR_STA—General Interrupt Status Register.........................................761

20.1.4 MAIN_CNT—Main Counter Value Register .................................................762

20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register......................762

20.1.6 TIMn_COMP—Timer n Comparator Value Register......................................764

21 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................765

21.1 Serial Peripheral Interface Memory Mapped Configuration Registers........................765

21.1.1 SPIS—SPI Status Register (SPI Memory Mapped Configuration

Registers)............................................................................................767

21.1.2 SPIC—SPI Control Register (SPI Memory Mapped Configuration

Registers)............................................................................................768

21.1.3 SPIA—SPI Address Register (SPI Memory Mapped Configuration

Registers)............................................................................................769

21.1.4 SPID[N] —SPI Data N Register (SPI Memory Mapped Configuration

Registers)............................................................................................769

21.1.5 BBAR—BIOS Base Address Register

(SPI Memory Mapped Configuration Registers)..........................................770

21.1.6 PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Configuration Registers)..........................................770

21.1.7 OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Configuration Registers)..........................................771

21.1.8 OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Configuration Registers)..........................................772

21.1.9 PBR[N]—Protected BIOS Range [N]

(SPI Memory Mapped Configuration Registers)..........................................772

22 Ballout Definition ................................................................................................... 773

22.1 Desktop, Mobile, and Digital Home Component Ballout..........................................773

22.2 Ultra Mobile Component Ballout .........................................................................782

23 Electrical Characteristics........................................................................................789

23.1 Thermal Specifications......................................................................................789

23.2 Absolute Maximum Ratings ...............................................................................789

23.3 DC Characteristics ...........................................................................................790

23.4 AC Characteristics............................................................................................ 801

23.5 Timing Diagrams ............................................................................................. 817

24 Package Information .............................................................................................835

24.1 Desktop and Mobile Package Information ............................................................835

24.2 Ultra Mobile Package Information.......................................................................837

25 Testability (Desktop and Mobile Only)....................................................................839

25.1 XOR Chain Tables.............................................................................................841

28 Intel ® ICH7 Family Datasheet

Page 29

Figures

2-1 Interface Signals Block Diagram (Desktop Only)...........................................................52

2-2 Interface Signals Block Diagram (Mobile Only) ............................................................ 53

2-3 Interface Signals Block Diagram (Ultra Mobile Only) ..................................................... 54

2-4 Example External RTC Circuit..................................................................................... 78

4-1 Desktop Only Conceptual System Clock Diagram..........................................................96

4-2 Mobile Only Conceptual Clock Diagram........................................................................ 96

4-3 Ultra Mobile Only Conceptual Clock Diagram ................................................................ 97

5-1 Generation of SERR# to Platform ............................................................................. 105

5-2 64-Word EEPROM Read Instruction Waveform............................................................ 112

5-3 LPC Interface Diagram............................................................................................ 118

5-4 LPC Bridge SERR# Generation ................................................................................. 123

5-5 Intel® ICH7 DMA Controller..................................................................................... 124

5-6 DMA Request Assertion through LDRQ# .................................................................... 127

5-7 Coprocessor Error Timing Diagram ........................................................................... 151

5-8 Physical Region Descriptor Table Entry...................................................................... 186

5-9 SATA Power States................................................................................................. 195

5-10USB Legacy Keyboard Flow Diagram......................................................................... 205

5-11 Intel® ICH7-USB Port Connections .......................................................................... 212

5-12Intel® ICH7-Based Audio Codec ’97 Specification, Version 2.3...................................... 233

5-13AC ’97 2.3 Controller-Codec Connection .................................................................... 235

5-14AC-Link Protocol .................................................................................................... 236

5-15AC-Link Powerdown Timing ..................................................................................... 237

5-16SDIN Wake Signaling.............................................................................................. 238

22-1 Desktop and Mobile Component Ballout (Topview–Left Side)....................................... 774

22-2Desktop and Mobile Component Ballout (Topview–Right Side)...................................... 775

22-3Intel

22-4Intel® ICH7-U Ballout (top view, right side)............................................................... 783

23-1Clock Timing ......................................................................................................... 817

23-2Valid Delay from Rising Clock Edge........................................................................... 817

23-3Setup and Hold Times............................................................................................. 817

23-4Float Delay ........................................................................................................... 818

23-5Pulse Width........................................................................................................... 818

23-6Output Enable Delay............................................................................................... 818

23-7IDE PIO Mode........................................................................................................ 819

23-8IDE Multiword DMA ................................................................................................ 819

23-9Ultra ATA Mode (Drive Initiating a Burst Read)........................................................... 820

23-10Ultra ATA Mode (Sustained Burst) .......................................................................... 820

23-11Ultra ATA Mode (Pausing a DMA Burst).................................................................... 821

23-12Ultra ATA Mode (Terminating a DMA Burst).............................................................. 821

23-13USB Rise and Fall Times........................................................................................ 822

23-14USB Jitter............................................................................................................ 822

23-15USB EOP Width .................................................................................................... 822

23-16SMBus Transaction ............................................................................................... 823

23-17SMBus Timeout.................................................................................................... 823

23-18Power Sequencing and Reset Signal Timings (Desktop Only)...................................... 824

23-19Power Sequencing and Reset Signal Timings (Mobile/Ultra Mobile Only)....................... 825

23-20G3 (Mechanical Off) to S0 Timings (Desktop Only).................................................... 826

23-21G3 (Mechanical Off) to S0 Timings (Mobile/Ultra Mobile Only) .................................... 827

23-22S0 to S1 to S0 Timing (Desktop Only)..................................................................... 827

23-23S0 to S5 to S0 Timings, S3 23-24S0 to S5 to S0 Timings, S3 23-25S0 to S5 to S0 Timings, S3 23-26S0 to S5 to S0 Timings, S3

ICH7-U Ballout (top view, left side)................................................................. 782

(Desktop Only)........................................................ 828

COLD

(Desktop Only)......................................................... 829

HOT

(Mobile/Ultra Mobile Only) ........................................ 830

COLD

(Mobile/Ultra Mobile Only).......................................... 831

HOT

Intel ® ICH7 Family Datasheet 29

Page 30

23-27C0 to C2 to C0 Timings (Mobile/Ultra Mobile Only) ....................................................831

23-28C0 to C3 to C0 Timings (Mobile/Ultra Mobile Only) ....................................................832

23-29C0 to C4 to C0 Timings (Mobile/Ultra Mobile Only) ....................................................832

23-30AC ’97 Data Input and Output Timings (Desktop and Mobile Only)...............................833

23-31Intel

High Definition Audio Input and Output Timings ..............................................833

23-32SPI Timings (Desktop and Mobile Only) ...................................................................834

24-1Intel® ICH7 Package (Top View)...............................................................................835

24-2Intel® ICH7 Package (Bottom View)..........................................................................836

24-3Intel® ICH7 Package (Side View)..............................................................................836

24-4Intel ICH7-U Package Drawing .................................................................................837

25-1XOR Chain Test Mode Selection, Entry and Testing......................................................839

25-2Example XOR Chain Circuitry ...................................................................................840

Tables

1-1 Industry Specifications ..............................................................................................39

1-2 PCI Devices and Functions.........................................................................................43

1-3 Intel® ICH7 Desktop/Server Family ............................................................................50

1-4 Intel® ICH7-M Mobile and ICH7-U Ultra Mobile Components...........................................50

2-1 Direct Media Interface Signals....................................................................................55

2-2 PCI Express* Signals ................................................................................................55

2-3 Platform LAN Connect Interface Signals.......................................................................56

2-4 EEPROM Interface Signals..........................................................................................56

2-5 Firmware Hub Interface Signals..................................................................................56

2-6 PCI Interface Signals ................................................................................................57

2-7 Serial ATA Interface Signals.......................................................................................59

2-8 IDE Interface Signals ................................................................................................60

2-9 LPC Interface Signals ................................................................................................62

2-10Interrupt Signals......................................................................................................62

2-11USB Interface Signals ...............................................................................................63

2-12Power Management Interface Signals..........................................................................64

2-13Processor Interface Signals........................................................................................66

2-14SM Bus Interface Signals ...........................................................................................68

2-15System Management Interface Signals........................................................................68

2-16Real Time Clock Interface..........................................................................................69

2-17Other Clocks............................................................................................................69

2-18Miscellaneous Signals................................................................................................70

2-19AC ’97/Intel® High Definition Audio Link Signals ...........................................................71

2-20Serial Peripheral Interface (SPI) Signals ......................................................................72

2-21General Purpose I/O Signals ......................................................................................72

2-22Power and Ground Signals.........................................................................................74

2-23Functional Strap Definitions .......................................................................................76

3-1 Integrated Pull-Up and Pull-Down Resistors..................................................................79

3-2 IDE Series Termination Resistors ................................................................................80

3-3 Power Plane and States for Output and I/O Signals for Desktop Only Configurations..........81

3-4 Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only

Configurations .........................................................................................................86

3-5 Power Plane for Input Signals for Desktop Only Configurations .......................................90

3-6 Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations ........................92

4-1 Intel

5-1 PCI Bridge Initiator Cycle Types .................................................................................99

5-2 Type 1 Address Format ...........................................................................................102

5-3 MSI vs. PCI IRQ Actions ..........................................................................................104

5-4 Advanced TCO Functionality.....................................................................................114

5-5 LPC Cycle Types Supported...................................................................................... 119

ICH7 and System Clock Domains ......................................................................95

30 Intel ® ICH7 Family Datasheet

Page 31

5-6 Start Field Bit Definitions ........................................................................................ 119

5-7 Cycle Type Bit Definitions........................................................................................ 120

5-8 Transfer Size Bit Definition...................................................................................... 120

5-9 SYNC Bit Definition................................................................................................. 121

5-10DMA Transfer Size.................................................................................................. 126

5-11Address Shifting in 16-Bit I/O DMA Transfers............................................................. 126

5-12Counter Operating Modes........................................................................................ 131

5-13Interrupt Controller Core Connections....................................................................... 133

5-14Interrupt Status Registers....................................................................................... 134

5-15Content of Interrupt Vector Byte .............................................................................. 134

5-16APIC Interrupt Mapping .......................................................................................... 140

5-17Interrupt Message Address Format........................................................................... 142

5-18Interrupt Message Data Format ............................................................................... 143

5-19Stop Frame Explanation.......................................................................................... 144

5-20Data Frame Format ................................................................................................ 145

5-21Configuration Bits Reset by RTCRST# Assertion ......................................................... 148

5-22INIT# Going Active ................................................................................................ 150

5-23NMI Sources.......................................................................................................... 151

5-24DP Signal Differences ............................................................................................. 152

5-25General Power States for Systems Using Intel® ICH7.................................................. 153

5-26State Transition Rules for Intel® ICH7 ...................................................................... 155

5-27System Power Plane............................................................................................... 156

5-28Causes of SMI# and SCI ......................................................................................... 157

5-29Break Events (Mobile/Ultra Mobile Only).................................................................... 160

5-30Sleep Types .......................................................................................................... 163

5-31Causes of Wake Events........................................................................................... 164

5-32GPI Wake Events ................................................................................................... 165

5-33Transitions Due to Power Failure .............................................................................. 166

5-34Transitions Due to Power Button .............................................................................. 167

5-35Transitions Due to RI# Signal.................................................................................. 168

5-36Write Only Registers with Read Paths in ALT Access Mode ........................................... 171

5-37PIC Reserved Bits Return Values .............................................................................. 173

5-38Register Write Accesses in ALT Access Mode .............................................................. 173

5-39Intel® ICH7 Clock Inputs ........................................................................................ 176

5-40Heartbeat Message Data ......................................................................................... 182

5-41 IDE Transaction Timings (PCI Clocks) ...................................................................... 184

5-42Interrupt/Active Bit Interaction Definition.................................................................. 188

5-43SATA Features Support in Intel® ICH7 ...................................................................... 191

5-44SATA Feature Description........................................................................................ 192

5-45Legacy Replacement Routing................................................................................... 198

5-46Bits Maintained in Low Power States......................................................................... 204

5-47USB Legacy Keyboard State Transitions .................................................................... 205

5-48UHCI vs. EHCI ....................................................................................................... 207

5-49Debug Port Behavior .............................................................................................. 215

5-50I2C Block Read ...................................................................................................... 223

5-51Enable for SMBALERT# ........................................................................................... 225

5-52Enables for SMBus Slave Write and SMBus Host Events............................................... 225

5-53Enables for the Host Notify Command....................................................................... 226

5-54Slave Write Registers ............................................................................................. 227

5-55Command Types .................................................................................................... 228

5-56Read Cycle Format................................................................................................. 229

5-57Data Values for Slave Read Registers........................................................................ 229

5-58Host Notify Format................................................................................................. 231

5-59Features Supported by Intel

ICH7 .......................................................................... 232

5-60Output Tag Slot 0 .................................................................................................. 237

Intel ® ICH7 Family Datasheet 31

Page 32

5-61SPI Implementation Options ....................................................................................245

5-62Required Commands and Opcodes ............................................................................247

5-63Intel® ICH7 Standard SPI Commands .......................................................................247

5-64Flash Protection Mechanism Summary.......................................................................248

6-1 PCI Devices and Functions.......................................................................................254

6-2 Fixed I/O Ranges Decoded by Intel

ICH7 .................................................................256

6-3 Variable I/O Decode Ranges.....................................................................................258

6-4 Memory Decode Ranges from Processor Perspective....................................................259

7-1 Chipset Configuration Register Memory Map (Memory Space).......................................263

8-1 LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) ...........................303

8-2 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ..........................310

8-3 Data Register Structure...........................................................................................314

8-4 Intel® ICH7 Integrated LAN Controller CSR Space Register Address Map........................315

8-5 Self-Test Results Format .........................................................................................320

8-6 Statistical Counters.................................................................................................327

8-7 ASF Register Address Map .......................................................................................329

9-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0)...................................................345

10-1LPC Interface PCI Register Address Map (LPC I/F—D31:F0)..........................................363

10-2DMA Registers .......................................................................................................385

10-3PIC Registers (LPC I/F—D31:F0)...............................................................................396

10-4APIC Direct Registers (LPC I/F—D31:F0) ...................................................................404

10-5APIC Indirect Registers (LPC I/F—D31:F0) .................................................................404

10-6RTC I/O Registers (LPC I/F—D31:F0) ........................................................................409

10-7RTC (Standard) RAM Bank (LPC I/F—D31:F0) ............................................................410

10-8Processor Interface PCI Register Address Map (LPC I/F—D31:F0)..................................415

10-9Power Management PCI Register Address Map (PM—D31:F0) .......................................418

10-10APM Register Map.................................................................................................430

10-11ACPI and Legacy I/O Register Map ..........................................................................431

10-12TCO I/O Register Address Map ...............................................................................456

10-13Registers to Control GPIO Address Map....................................................................463

11-1UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3) .............................469

11-2USB I/O Registers ..................................................................................................479

11-3Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation..................482

12-1SATA Controller PCI Register Address Map (SATA–D31:F2) ..........................................489

12-2Bus Master IDE I/O Register Address Map..................................................................519

12-3AHCI Register Address Map...................................................................................... 523

12-4Generic Host Controller Register Address Map ............................................................524

12-5Port [3:0] DMA Register Address Map .......................................................................529

13-1USB EHCI PCI Register Address Map (USB EHCI—D29:F7) ...........................................545

13-2Enhanced Host Controller Capability Registers ............................................................561

13-3Enhanced Host Controller Operational Register Address Map ........................................564

13-4Debug Port Register Address Map .............................................................................577

14-1SMBus Controller PCI Register Address Map (SMBUS—D31:F3).....................................583

14-2SMBus I/O Register Address Map..............................................................................588

15-1IDE Controller PCI Register Address Map (IDE-D31:F1) ...............................................601

15-2Bus Master IDE I/O Registers...................................................................................615

16-1AC ‘97 Audio PCI Register Address Map (Audio—D30:F2) .............................................619

16-2Intel

ICH7 Audio Mixer Register Configuration..........................................................631

16-3Native Audio Bus Master Control Registers .................................................................633

17-1AC ‘97 Modem PCI Register Address Map (Modem—D30:F3) ........................................647

17-2Intel® ICH7 Modem Mixer Register Configuration........................................................655

17-3Modem Registers....................................................................................................656

18-1PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5).....................................................................665

32 Intel ® ICH7 Family Datasheet

Page 33

19-1Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)....................................................................... 705

19-2Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)....................................................................... 728

20-1Memory-Mapped Registers ...................................................................................... 759

21-1Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers)........................................................... 765

22-1 Desktop and Mobile Component Ballout by Signal Name............................................. 776

22-2Intel

ICH7-U Ballout by Signal Name ...................................................................... 784

23-1Intel® ICH7 Absolute Maximum Ratings .................................................................... 789

23-2DC Current Characteristics ...................................................................................... 790

23-3DC Current Characteristics (Mobile/Ultra Mobile Only) ................................................. 791

23-4DC Characteristic Input Signal Association................................................................. 792

23-5DC Input Characteristics ......................................................................................... 794

23-6DC Characteristic Output Signal Association............................................................... 796

23-7DC Output Characteristics ....................................................................................... 798

23-8Other DC Characteristics......................................................................................... 799

23-9Clock Timings........................................................................................................ 801

23-10PCI Interface Timing............................................................................................. 803

23-11IDE PIO Mode Timings .......................................................................................... 804

23-12IDE Multiword DMA Timings................................................................................... 804

23-13Ultra ATA Timing (Mode 0, Mode 1, Mode 2) ............................................................ 805

23-14Ultra ATA Timing (Mode 3, Mode 4, Mode 5) ............................................................ 807

23-15Universal Serial Bus Timing ................................................................................... 809

23-16SATA Interface Timings (Desktop and Mobile Only)................................................... 810

23-17SMBus Timing...................................................................................................... 810

23-19LPC Timing.......................................................................................................... 811

23-20Miscellaneous Timings........................................................................................... 811

23-18AC ’97 / Intel® High Definition Audio Timing ............................................................ 811

23-21SPI Timings (Desktop and Mobile Only)................................................................... 812

23-22(Power Sequencing and Reset Signal Timings........................................................... 812

23-23Power Management Timings .................................................................................. 814

25-1XOR Test Pattern Example ...................................................................................... 840

25-2XOR Chain 1 (REQ[4:1]# = 0000)............................................................................ 841

25-3XOR Chain 2 (REQ[4:1]# = 0001)............................................................................ 842

25-4XOR Chain 3 (REQ[4:1]# = 0010)............................................................................ 843

25-5XOR Chain 4-1 (REQ[4:1]# = 0011)......................................................................... 844

25-6XOR Chain 4-2 (REQ[4:1]# = 0011)......................................................................... 845

25-7XOR Chain 5 (REQ[4:1]# = 0100)............................................................................ 846

Intel ® ICH7 Family Datasheet 33

Page 34

Revision History

Revision Description Date

-001 • Initial release April 2005

-002 • Added specificaitons for ICH7DH, ICH7-M, and ICH7-M DH January 2006

-003

• Added specifications for the ICH7-U

• Added Documentation Changes/Specification Changes from Spec Update Revision -020.

April 2007

34 Intel ® ICH7 Family Datasheet

Page 35

Intel® ICH7 Family Features

Direct Media Interface

— 10 Gb/s each direction, full duplex — Transparent to software

PCI Express* (Desktop and Mobile Only)

— 4 PCI Express root ports — NEW: 2 Additional PCI Express root ports (ICH7R/

Digital Home only) configurable as x1 only — Supports PCI Express 1.0a — Ports 1-4 can be statically configured as 4x1, or 1x4. — Support for full 2.5 Gb/s bandwidth in each direction

per x1 lane — Module based Hot-Plug supported

(e.g., ExpressCard*) (Desktop and Mobile Only)

PCI Bus Interface

— Supports PCI Rev 2.3 Specification at 33 MHz — New: Six available PCI REQ/GNT pairs (3 pairs on

Ultra Mobile) — Support for 64-bit addressing on PCI using DAC

protocol

Integrated Serial ATA Host Controller (Desktop and Mobile Only)

— Four ports (desktop only) or two ports (Mobile only) — NEW: Data transfer rates up to 3.0 Gb/s

(300 MB/s) (Desktop Only) — Integrated AHCI controller

(RAID, Digital Home and Mobile only)

Intel® Matrix Storage Technology (RAID and Digital Home only)

— Configures the ICH7 SATA controller as a RAID

controller supporting RAID 0/1/10 (RAID and ICH7

DH only) — Configures the ICH7 SATA controller as a RAID

controller supporting RAID 0/1 (ICH7-M DH) — NEW: Support for RAID 5 (RAID and ICH7 DH only)

Integrated IDE Controller

— Independent timing of up to two drives (one drive on

Ultra Mobile) — Ultra ATA/100/66/33, BMIDE and PIO modes — Tri-state modes to enable swap bay — Supports ATA/ATAPI-7

Intel® High Definition Audio Interface

— PCI Express endpoint — Independent Bus Master logic for eight general purpose

streams: four input and four output — Support three external Codecs — Supports variable length stream slots — Supports multichannel, 32-bit sample depth and 192

kHz sample rate output — Provides mic array support — Allows for non-48 kHz sampling output — Support for ACPI Device States — NEW: Docking Support (Mobile Only) — NEW: Low Voltage Mode (Mobile/Ultra Mobile Only)

AC-Link for Audio and Telephony CODECs (Desktop and Mobile Only)

— Support for three AC ‘97 2.3 codecs. — Independent bus master logic for 8 channels (PCM In/

Out, PCM 2 In, Mic 1 Input, Mic 2 Input, Modem In/ Out, S/PDIF Out)

— Support for up to six channels of PCM audio output

(full AC3 decode)

— Supports wake-up events

USB 2.0

— Includes four UHCI Host Controllers, supporting eight

external ports

— Includes one EHCI Host Controller that supports all

eight ports — Includes one USB 2.0 High-speed Debug Port — Supports wake-up from sleeping states S1–S5 — Supports legacy Keyboard/Mouse software

Integrated LAN Controller (Desktop and Mobile Only)

— Integrated ASF Management Controller — Supports IEEE 802.3 — LAN Connect Interface (LCI) — 10/100 Mb/s Ethernet Support

NEW: Intel Active Management Technology (Desktop and Mobile Only) NEW: Intel® Quick Resume Technology Support (Digital Home Only) Power Management Logic

— Supports ACPI 3.0 — ACPI-defined power states (C1, S1, S3–S5 for Desktop

and C1–C4, S1, S3–S5 for Mobile/Ultra Mobile) — ACPI Power Management Timer — (Mobile/Ultra Mobile Only) Support for “Intel

SpeedStep® Technology” processor power control and

“Deeper Sleep” power state — PCI CLKRUN# and PME# support — SMI# generation — All registers readable/restorable for proper resume

from 0 V suspend states — Support for APM-based legacy power management for

non-ACPI Desktop and Mobile implementations

External Glue Integration

— Integrated Pull-up, Pull-down and Series Termination

resistors on IDE, processor interface — Integrated Pull-down and Series resistors on USB

Enhanced DMA Controller

— Two cascaded 8237 DMA controllers — Supports LPC DMA (Desktop and Mobile Only)

Intel ® ICH7 Family Datasheet 35

Page 36

SMBus

— Flexible SMBus/SMLink architecture to optimize

for ASF

— Provides independent manageability bus through

SMLink interface — Supports SMBus 2.0 Specification — Host interface allows processor to communicate

via SMBus — Slave interface allows an internal or external

Microcontroller to access system resources — Compatible with most two-wire components that

are also I2C compatible

High Precision Event Timers

— Advanced operating system interrupt scheduling

Timers Based on 82C54

— System timer, Refresh request, Speaker tone

output

Real-Time Clock

— 256-byte battery-backed CMOS RAM — Integrated oscillator components — Lower Power DC/DC Converter implementation

System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang — Timers to detect improper processor reset — Integrated processor frequency strap logic — Supports ability to disable external devices

Interrupt Controller

— Supports up to eight PCI interrupt pins — Supports PCI 2.3 Message Signaled Interrupts — Two cascaded 82C59 with 15 interrupts — Integrated I/O APIC capability with 24 interrupts — Supports Processor System Bus interrupt

delivery

1.05 V operation with 1.5 V and 3.3 V I/O — 5 V tolerant buffers on IDE, PCI, USB and

Legacy signals

NEW: 1.05 V Core Voltage Integrated 1.05 V Voltage Regulator (INTVR) for

the Suspend and LAN wells (Desktop and Mobile

Only)

Firmware Hub I/F supports BIOS Memory size up to 8 MBytes (Desktop and Mobile Only)

NEW: Serial Peripheral Interface (SPI) for Serial and Shared Flash (Desktop and Mobile Only)

Low Pin Count (LPC) I/F

— Supports two Master/DMA devices. — Support for Security Device (Trusted Platform

Module) connected to LPC.

GPIO

— TTL, Open-Drain, Inversion

NEW: Package 31 mm x 31 mm 652 mBGA (Desktop and Mobile Only)

New: Package 15 mm x 15 mm, 452 balls (Ultra Mobile only)

Desktop Configuration

(Supports 8 USB ports)

AC ’97/Intel® High

Intel® PCI Express

Gigabit Ethernet

PCI Express* x1

USB 2.0

IDE

SATA (4 ports)

Definition Audio

Codec(s)

LAN Connect

GPIO

Other ASICs

(Optional)

TPM

(Optional)

(To (G)MCH)

Intel

ICH7

LPC I/F

DMI

PCI Bus

S L

Super I/O

Firmware Hub

Power Management

Clock Generators

System Management

(TCO)

SMBus 2.0/I2C

SPI BIOS

S L

...

O T

36 Intel ® ICH7 Family Datasheet

Page 37

Mobile Configuration

DMI

(To (G)MCH)

USB 2.0

(Supports 8 USB ports)

IDE

SATA (2 ports)

AC’97/Intel® High

Definition Audio

Codec(s)

PCI Express x1

LAN Connect

GPIO

Ultra Mobile Configuration

Other ASICs

(Optional)

TPM

(Optional)

Intel

ICH7-M

LPC I/F

PCI Bus

Super I/O

Flash BIOS

DMI

(To GMCH)

Power Management

Clock Generators

System Management

(TCO)

SMBus 2.0/I2C

Docking

Cardbus

Controller (&

attached slots)

Bridge

SPI BIOS

USB 2.0

(Supports 8 USB ports)

IDE

Intel® High Definition

Audio Codec(s)

GPIO

Other ASICs

(Optional)

TPM

(Optional)

Intel

ICH7-U

LPC I/F

Super I/O

Flash BIOS

Power Management

Clock Generators

System Management

(TCO)

SMBus 2.0/I2C

PCI Bus

3 PCI

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Introduction

1 Introduction

This document is intended for Original Equipment Manufacturers and BIOS vendors creating Intel® I/O Controller Hub 7 (ICH7) Family based products. This document is the datasheet for the following:

• Intel® 82801GB ICH7 (ICH7)

• Intel® 82801GR ICH7 RAID (ICH7R)

• Intel® 82801GDH ICH7 Digital Home (ICH7DH)

• Intel® 82801GBM ICH7 Mobile (ICH7-M)

• Intel® 82801GHM ICH7 Mobile Digital Home (ICH7-M DH)

• Intel® 82801GU ICH7-U Ultra Mobile (ICH7-U)

Section 1.2 provides high-level feature differences for the ICH7 Family components.

Note: Throughout this datasheet, ICH7 is used as a general ICH7 term and refers to the

82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH, 82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U components, unless specifically noted otherwise.

Note: Throughout this datasheet, the term “Desktop” refers to any implementation, be it in a

desktop, server, workstation, etc., unless specifically noted otherwise.

Note: Throughout this datasheet, the terms “Desktop”, “Digital Home” “Mobile”, and “Ultra

Mobile” refer to the following components, unless specifically noted otherwise:

• Desktop refers to the 82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH.

• Digital Home refers to the 82801GDH ICH7DH and 82801GHM ICH7-M DH.

• Mobile refers to the 82801GBM ICH7-M, and 82801GHM ICH7-M DH.

• Ultra Mobile refers to the 82801GU ICH7-U.

Note: “Desktop and Mobile Only” refers to all components in this document except the

82801GU ICH7-U Ultra Mobile component. This datasheet assumes a working knowledge of the vocabulary and principles of PCI

Express*, USB, IDE, AHCI, SATA, Intel®High Definition Audio (Intel® HD Audio), AC ’97, SMBus, PCI, ACPI and LPC. Although some details of these features are described within this manual, refer to the individual industry specifications listed in

Table 1-1 for the complete details.

Table 1-1. Industry Specifications

Specification Location

Intel® I/O Controller Hub ICH7 Family Specification Update

Intel® I/O Controller Hub ICH7 Family Thermal Mechanical Guidelines

PCI Express* Base Specification, Revision 1.0a http://www.pcisig.com/specifications Low Pin Count Interface Specification, Revision 1.1

(LPC) Audio Codec ‘97 Component Specification, Version 2.3

(AC ’97)

http://developer.intel.com//design/ chipsets/specupdt/307014.htm

http://developer.intel.com//design/ chipsets/designex/307015.htm

http://developer.intel.com/design/ chipsets/industry/lpc.htm

http://www.intel.com/design/ chipsets/audio/

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Table 1-1. Industry Specifications

Specification Location

System Management Bus Specification, Version 2.0 (SMBus)

PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications PCI Mobile Design Guide, Revision 1.1 http://www.pcisig.com/specifications PCI Power Management Specification, Revision 1.1 http://www.pcisig.com/specifications Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs Advanced Configuration and Power Interface, Version

2.0 (ACPI)

Universal Host Controller Interface, Revision 1.1 (UHCI)

Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI)

Serial ATA Specification, Revision 1.0a

Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0

Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf

IEEE 802.3 Fast Ethernet

AT Attachment - 6 with Packet Interface (ATA/ATAPI -

6) IA-PC HPET (High Precision Event Timers) Specification,

Revision 1.0

Introduction

http://www.smbus.org/specs/

http://www.acpi.info/spec.htm

http://developer.intel.com/design/ USB/UHCI11D.htm

http://developer.intel.com/ technology/usb/ehcispec.htm

http://www.serialata.org/ specifications.asp

http://standards.ieee.org/ getieee802/

http://T13.org (T13 1410D)

http://www.intel.com/ hardwaredesign/hpetspec.htm

Chapter 1. Introduction

Chapter 1 introduces the ICH7 and provides information on manual organization and

gives a general overview of the ICH7.

Chapter 2. Signal Description

Chapter 2 provides a block diagram of the ICH7 interface signals and a detailed

description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals.

Chapter 3. Intel® ICH7 Pin States

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each suspend state, and their logic level before and after reset.

Chapter 4. Intel® ICH7 and System Clock Domains

Chapter 4 provides a list of each clock domain associated with the ICH7 in an ICH7

based system.

Chapter 5. Functional Description

Chapter 5 provides a detailed description of the functions in the ICH7. All PCI buses,

devices and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8, D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the ICH7’s external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration.

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Introduction

Chapter 6. Register and Memory Mappings

Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges

and memory ranges decoded by the ICH7.

Chapter 7. Chipset Configuration Registers

Chapter 7 provides a detailed description of all registers and base functionality that is

related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express). It contains the root complex register block, which describes the behavior of the upstream internal link.

Chapter 8. LAN Controller Registers

Chapter 8 provides a detailed description of all registers that reside in the ICH7’s

integrated LAN controller. The integrated LAN controller resides on the ICH7’s external PCI bus (typically Bus 1) at Device 8, Function 0 (B1:D8:F0).

Chapter 9. PCI-to-PCI Bridge Registers

Chapter 9 provides a detailed description of all registers that reside in the PCI-to-PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 10. LPC Bridge Registers

Chapter 10 provides a detailed description of all registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the ICH7 including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC.

Chapter 11. SATA Controller Registers

Chapter 12 provides a detailed description of all registers that reside in the SATA

controller. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 12. UHCI Controller Registers

Chapter 11 provides a detailed description of all registers that reside in the four UHCI

host controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3 (D29:F0/F1/F2/F3).

Chapter 13. EHCI Controller Registers

Chapter 13 provides a detailed description of all registers that reside in the EHCI host

controller. This controller resides at Device 29, Function 7 (D29:F7).

Chapter 14. SMBus Controller Registers

Chapter 14 provides a detailed description of all registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Chapter 15. IDE Controller Registers

Chapter 15 provides a detailed description of all registers that reside in the IDE

controller. This controller resides at Device 31, Function 1 (D31:F1).

Chapter 16. AC ’97 Audio Controller Registers

Chapter 16 provides a detailed description of all registers that reside in the audio

controller. This controller resides at Device 30, Function 2 (D30:F2). Note that this section of the datasheet does not include the native audio mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside.

Chapter 17. AC ’97 Modem Controller Registers

Chapter 17 provides a detailed description of all registers that reside in the modem

controller. This controller resides at Device 30, Function 3 (D30:F3). Note that this section of the datasheet does not include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside.

Chapter 18. Intel® High Definition Audio Controller Registers

Chapter 18 provides a detailed description of all registers that reside in the Intel®High

Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).

Chapter 19. PCI Express* Port Controller Registers

Chapter 19 provides a detailed description of all registers that reside in the PCI Express

controller. This controller resides at Device 28, Functions 0 to 5 (D30:F0-F5).

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Chapter 20. High Precision Event Timers Registers

Chapter 20 provides a detailed description of all registers that reside in the multimedia

timer memory mapped register space.

Chapter 21. Serial Peripheral Interface Registers

Chapter 21 provides a detailed description of all registers that reside in the SPI

memory mapped register space.

Chapter 22. Ballout Definition

Chapter 22 provides a table of each signal and its ball assignment in the 652-mBGA

package.

Chapter 23. Electrical Characteristics

Chapter 23 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 24. Package Information

Chapter 24 provides drawings of the physical dimensions and characteristics of the

652-mBGA package.

Chapter 25. Testability

Chapter 25 provides detail about the implementation of test modes provided in the

ICH7.

1.1 Overview

The ICH7 provides extensive I/O support. Functions and capabilities include:

• PCI Express* Base Specification, Revision 1.0a support (Desktop and Mobile Only)

• PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations (supports up to six Req/Gnt pairs; three pairs on Ultra Mobile).

• ACPI Power Management Logic Support

• Enhanced DMA controller, interrupt controller, and timer functions (Desktop and

Mobile Only)

• Integrated Serial ATA host controller with independent DMA operation on four ports

(Desktop only) or two ports (Mobile Only) and AHCI (ICH7R, ICH7DH, ICH7-M, and ICH7-M DH Only) support. (SATA not supported on Ultra Mobile)

• Integrated IDE controller supports Ultra ATA100/66/33

• USB host interface with support for eight USB ports; four UHCI host controllers;

one EHCI high-speed USB 2.0 Host controller

• Integrated LAN controller (Desktop and Mobile Only)

• System Management Bus (SMBus) Specification, Version 2.0 with additional

support for I2C devices (Desktop and Mobile Only)

• Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a., AC ’97 Component

Specification, Revision 2.3) which provides a link for Audio and Telephony codecs (up to 7 channels) (Desktop and Mobile Only)

• Supports Intel High Definition Audio

• Supports Intel®Matrix Storage Technology (ICH7R, ICH7DH, and Mobile Only)

• Supports Intel®Active Management Technology (Desktop and Mobile Only)

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Serial Peripheral Interface (SPI) support (Desktop and Mobile Only)

Introduction

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Introduction

The ICH7 incorporates a variety of PCI functions that are divided into six logical devices (B0:D27, B0:D28, B0:D29, B0:D30, B0:D31 and B1:D8) as listed in Table 1-2. D30 is the DMI-to-PCI bridge and the AC ’97 Audio and Modem controller functions, D31 contains the PCI-to-LPC bridge, IDE controller, SATA controller, and SMBus controller, D29 contains the four USB UHCI controllers and one USB EHCI controller, and D27 contains the PCI Express root ports. B1:D8 is the integrated LAN controller.

Table 1-2. PCI Devices and Functions

Bus:Device:Function Function Description

Bus 0:Device 30:Function 0 PCI-to-PCI Bridge Bus 0:Device 30:Function 2 AC ’97 Audio Controller (Desktop and Mobile Only) Bus 0:Device 30:Function 3 AC ’97 Modem Controller (Desktop and Mobile Only) Bus 0:Device 31:Function 0 LPC Controller Bus 0:Device 31:Function 1 IDE Controller Bus 0:Device 31:Function 2 SATA Controller (Desktop and Mobile Only) Bus 0:Device 31:Function 3 SMBus Controller Bus 0:Device 29:Function 0 USB UHCI Controller #1 Bus 0:Device 29:Function 1 USB UHCI Controller #2 Bus 0:Device 29:Function 2 USB UHCI Controller #3 Bus 0:Device 29:Function 3 USB UHCI Controller #4 Bus 0:Device 29:Function 7 USB 2.0 EHCI Controller Bus 0:Device 28:Function 0 PCI Express* Port 1 (Desktop and Mobile Only) Bus 0:Device 28:Function 1 PCI Express Port 2 (Desktop and Mobile Only) Bus 0:Device 28:Function 2 PCI Express Port 3 (Desktop and Mobile Only) Bus 0:Device 28:Function 3 PCI Express Port 4 (Desktop and Mobile Only)

Bus 0:Device 28:Function 4 Bus 0:Device 28:Function 5 PCI Express Port 6 (Intel ICH7R, ICH7DH, and ICH7-M DH Only)

Bus 0:Device 27:Function 0 Intel®High Definition Audio Controller Bus n:Device 8:Function 0 LAN Controller (Desktop and Mobile Only)

PCI Express Port 5 (Intel Only)

ICH7R, ICH7DH, and ICH7-M DH

NOTES:

1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.

The following sub-sections provide an overview of the ICH7 capabilities.

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics Memory Controller Hub ((G)MCH) and I/O Controller Hub 7 (ICH7). This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally.

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Introduction

PCI Express* Interface (Desktop and Mobile Only)

The ICH7R, ICH7DH, ICH7-M DH have six PCI Express root ports and the ICH7 and ICH7-M have four PCI Express root ports (ports 1-4), supporting the PCI Express Base Specification, Revision 1.0a. PCI Express root ports 1–4 can be statically configured as four x1 ports or ganged together to form one x4 port. Ports 5 and 6 on the ICH7R, ICH7DH, and ICH7-M DH can only be used as two x1 ports. Each Root Port supports

2.5 Gb/s bandwidth in each direction (5 Gb/s concurrent).

Serial ATA (SATA) Controller (Desktop and Mobile Only)

The ICH7 has an integrated SATA host controller that supports independent DMA operation on four ports (desktop only) or two ports (mobile only) and supports data transfer rates of up to 3.0 Gb/s (300 MB/s). The SATA controller contains two modes of operation – a legacy mode using I/O space, and an AHCI mode using memory space.

SATA and PATA can also be used in a combined function mode (where the SATA function is used with PATA). In this combined function mode, AHCI mode is not used. Software that uses legacy mode will not have AHCI capabilities.

The ICH7 supports the Serial ATA Specification, Revision 1.0a. The ICH7 also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements).

AHCI (Intel® ICH7R, ICH7DH, and Mobile Only)

The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug (Desktop and Mobile Only). AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware.

Intel® Matrix Storage Technology (Intel® ICH7R, ICH7DH, and ICH7-M DH Only)

The ICH7 provides support for Intel Matrix Storage Technology, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality (RAID 0/1 functionality for ICH7-M DH) on up to 4 SATA ports of ICH7. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare support, SMART alerting, and RAID 0 auto replace. Software components include an Option ROM for pre-boot configuration and boot functionality, a Microsoft* Windows* compatible driver, and a user interface for configuration and management of the RAID capability of ICH7.

PCI Interface

The ICH7 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters (three on Ultra Mobile) in addition to the internal ICH7 requests. This allows for combinations of up to six PCI down devices (three on Ultra Mobile) and PCI slots.

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Introduction

IDE Interface (Bus Master Capability and Synchronous DMA Mode)

The fast IDE interface supports up to two IDE devices (one device on Ultra Mobile) providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/sec and Ultra ATA transfers up 100 MB/sec. It does not consume any legacy DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers.

The ICH7’s IDE system contains a single, independent IDE signal channel that can be electrically isolated. There are integrated series resistors on the data and control lines (see Section 5.16 for details).

Low Pin Count (LPC) Interface

The ICH7 implements an LPC Interface as described in the LPC 1.1 Specification. The Low Pin Count (LPC) bridge function of the ICH7 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

The ICH7 implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI flash device can be used as a replacement for the FWH.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-bybyte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers.

The ICH7 supports LPC DMA (Desktop and Mobile Only), which is similar to ISA DMA, through the ICH7’s DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0– 3 are 8-bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.

The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for these three counters.

The ICH7 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH7 supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the ICH7 incorporates the Advanced Programmable Interrupt Controller (APIC).

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Introduction

Universal Serial Bus (USB) Controller

The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller that supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The ICH7 also contains four Universal Host Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling.

The ICH7 supports eight USB 2.0 ports. All eight ports are high-speed, full-speed, and low-speed capable. ICH7’s port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. See Section 5.19 and Section 5.20 for details.

LAN Controller (Desktop and Mobile Only)

The ICH7’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN controller to perform high speed data transfers over the PCI bus. Its bus master capabilities enable the component to process high-level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS).

The LAN controller can operate in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See

Section 5.3 for details.

Alert Standard Format (ASF) Management Controller (Desktop and Mobile Only)

ICH7 integrates an Alert Standard Format controller in addition to the integrated LAN controller, allowing interface system-monitoring devices to communicate through the integrated LAN controller to the network. This makes remote manageability and system hardware monitoring possible using ASF.

The ASF controller can collect and send various information from system components such as the processor, chipset, BIOS and sensors on the motherboard to a remote server running a management console. The controller can also be programmed to accept commands back from the management console and execute those commands on the local system.

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Introduction

RTC

The ICH7 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3 V battery.

The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on ICH7 configuration.

Enhanced Power Management

The ICH7’s power management functions include enhanced clock control and various low-power (suspend) states (e.g., Suspend-to-RAM and Suspend-to-Disk). A hardwarebased thermal management circuit permits software-independent entrance to lowpower states. The ICH7 contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 3.0.

Intel® Quick Resume Technology (Digital Home Only)

ICH7 implements Intel Quick Resume Technology that provides the capability to design a PC with a single power button that reliably and instantly (user's perception) turns the PC On and Off. When the system is On and the user presses the power button, the display instantly goes dark, sound is muted, and there is no response to keyboard/ mouse commands (except for keyboard power button). When the system is Off and the user presses the power button, picture and sound quickly return, and the keyboard/ mouse return to normal functionality, allowing user input.

Intel® Active Management Technology (Intel® AMT) (Desktop and Mobile Only)

Intel Active Management Technology is the next generation of client manageability via the wired network. Intel AMT is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research.

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Introduction

Manageability

In addition to Intel AMT the ICH7 integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.

• TCO Timer. The ICH7’s integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock.

• Processor Present Indicator. The ICH7 looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the ICH7 will reboot the system.

• ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the ICH7. The host controller can instruct the ICH7 to generate either an SMI#, NMI, SERR#, or TCO interrupt.

• Function Disable. The ICH7 provides the ability to disable the following integrated functions: AC ’97 Modem, AC ’97 Audio, IDE, LAN, USB, LPC, Intel HD Audio, SATA, or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disable functions.

• Intruder Detect. The ICH7 provides an input signal (INTRUDER#) that can be attached to a switch that is activated by the system case being opened. The ICH7 can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal.

System Management Bus (SMBus 2.0) (Desktop and Mobile Only)

The ICH7 contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented.

The ICH7’s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the ICH7 supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

ICH7’s SMBus also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus devices.

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Introduction

Intel®High Definition Audio Controller

The Intel®High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The ICH7 Intel HD Audio digital link shares pins with the AC-link. Concurrent operation of Intel HD Audio and AC ’97 functionality is not supported. The ICH7 Intel HD Audio controller supports up to 3 codecs.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel® HD Audio controller provides audio quality that can deliver CE levels of audio experience. On the input side, the ICH7 adds support for an arrays of microphones.

The Intel HD Audio controller uses multi-purpose DMA engines, as opposed to dedicated DMA engines in AC ’97 (Desktop and Mobile Only), to effectively manage the link bandwidth and support simultaneous independent streams on the link. The capability enables new exciting usage models with Intel HD Audio (e.g., listening to music while playing multi-player game on the internet.) The Intel HD Audio controller also supports isochronous data transfers allowing glitch-free audio to the system.

Note: Users interested in providing feedback on the Intel High Definition Audio Specification

or planning to implement the Intel High Definition Audio Specification into a future product will need to execute the Intel High Definition Audio Specification Developer’s Agreement. For more information, contact nextgenaudio@intel.com.

AC ’97 2.3 Controller (Desktop and Mobile Only)

The ICH7 integrates an Audio Codec '97 Component Specification, Version 2.3 controller that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or a combination of ACs and a single MC. The ICH7 supports up to six channels of PCM audio output (full AC3 decode). For a complete surround-sound experience, six-channel audio consists of: front left, front right, back left, back right, center, and subwoofer. ICH7 has expanded support for up to three audio codecs on the AC-link.

In addition, an AC '97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC '97. The ICH7-integrated AC '97 controller allows up to three external codecs to be connected to the ICH7. The system designer can provide AC '97 modem with a modem codec, or both audio and modem with up to two audio codecs with a modem codec.

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1.2 Intel® ICH7 Family High-Level Component Differences

Introduction

Table 1-3. Intel® ICH7 Desktop/Server Family

Product Name

Intel® ICH7 Base (ICH7)

ICH7 Digital Home (ICH7DH)

ICH7 RAID (ICH7R)

NOTES:

1. Feature capability can be read in D31:F0:Offset E4h.

2. The ICH7 Base (ICH7) supports Ports 1:4; ICH7 RAID (ICH7R) and ICH7 Digital Home

(ICH7DH) supports Ports 1:6.

Base

Features

Yes No/No No

Yes Yes / Yes Yes

Technology RAID

Intel® Matrix

Storage

0/1/5/10 /

AHCI

6 PCI

Express

Ports

Support

Table 1-4. Intel® ICH7-M Mobile and ICH7-U Ultra Mobile Components

Intel® Matrix

Product Name

ICH7 Mobile ICH7-M Yes Yes No No Yes ICH7 Mobile

Digital Home ICH7 Ultra

Mobile

Short

Name

ICH7-M DH Yes Yes Yes Yes Yes

ICH7-U

Base

Features

Not all

features

AHCI

No No No No

Storage

Technology

RAID 0/1

Intel

AMT

Yes No

Yes Yes

Yes No

Express*

Resume

Technology

6 PCI

Ports

Intel

Quick

Intel

Ready

AMT

NOTES:

1. Feature capability can be read in D31:F0:Offset E4h.

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Signal Description

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. Figure 2-1 shows the interface signals for the Intel® 82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH. Figure 2-2 shows the interface signals for the 82801GBM ICH7-M and 82801GHM ICH7-M DH. Figure 2-3 shows the interface signals for the 82801GU ICH7U.

The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high voltage level.

The “Type” for each signal is indicative of the functional operating mode of the signal. Unless otherwise noted in Section 3.3 or Section 3.4, a signal is considered to be in the functional operating mode after RTCRST# for signals in the RTC well, RSMRST# for signals in the suspend well, after PWROK for signals in the core well, and after LAN_RST# for signals in the LAN well.

The following notations are used to describe the signal type:

I Input Pin O Output Pin OD O Open Drain Output Pin. I/OD Bi-directional Input/Open Drain Output Pin. I/O Bi-directional Input / Output Pin. OC Open Collector Output Pin.

Intel ® ICH7 Family Datasheet 51

Page 52

Figure 2-1. Interface Signals Block Diagram (Desktop Only)

AD[31:0]

Signal Description

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY# TRDY# STOP#

PAR

PERR#

REQ[3:0]#

REQ[4]# / GPIO[22]

REQ[5]# / GPIO[1]

GNT[3:0]# GNT[4]# / GPIO[48] GNT[5]# / GPIO[17]

CPUPWRGD / GPIO[49]

PIRQ[H:E]# / GPIO[5:2]

OC[5]# / GPIO[29] OC[6]# / GPIO[30] OC[7]# / GPIO[31]

SATA_CLKP, SATA_CLKN

DMI_CLKP, DMI_CLKN

GPIO[39:38, 34:32, 28:26, 25:24, 20, 18, 16:12, 10:6]

PCICLK

PCIRST#

PLOCK#

SERR#

PME#

A20M#

CPUSLP#

FERR#

IGNNE#

INIT#

INIT3_3V#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

SPI_CS# SPI_MISO SPI_MOSI

SPI_ARB

SPI_CLK

SERIRQ

PIRQ[D:A]#

IDEIRQ

USBP[7:0]P USBP[7:0]N

OC[4:0]#

USBRBIAS#

USBRBIAS

RTCX1 RTCX2

CLK14 CLK48

INTVRMEN

SPKR

RTCRST#

TP0

TP[2:1]

TP3

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

PCI

Interface

Processor

Interface

SPI

Interrupt

Interface

USB

RTC

Clocks

Misc.

Signals

General Purpose

I/O

EEPROM

Interface

IDE

Interface

PCI Express* Interface

Serial ATA

Interface

Power

Mgnt.

AC '97/

Intel

High

Definition

Audio

Direct Media

Interface

Firmware

Hub

LPC

Interface

SMBus

Interface

System

Mgnt.

Platform

LAN

Connect

Intel® Quick

Resume

Technology

DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW# (DSTOP) IORDY (DRSTB / WDMARDY#)

PETp[6:1], PETn[6:1] PERp[6:1], PERn[6:1]

SATA[3:0]TXP, SATA[3:0]TXN SATA[3:0]RXP, SATA[3:0]RXN SATARBIAS SATARBIAS# SATA[3:0]GP/GPIO[37,36,21,19] SATALED# SATACLKREQ#/GPIO[35]

THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK LAN_RST# VRMPWRGD PLTRST#

ACZ_RST# ACZ_SYNC ACZ_BIT_CLK ACZ_SDOUT ACZ_SDIN[2:0]

DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP

FWH[3:0] / LAD[3:0] FWH[4] / LFRAME#

LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[0]# LDRQ[1]# / GPIO[23]

SMBDATA SMBCLK SMBALERT# / GPIO[11]

INTRUDER# SMLINK[1:0] LINKALERT#

LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC

EL_RSVD / GPIO26 EL_STATE[1:0] / GPIO[28:27]

Digital Home Only

52 Intel ® ICH7 Family Datasheet

Page 53

Signal Description

Figure 2-2. Interface Signals Block Diagram (Mobile Only)

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY# TRDY# STOP#

PAR

PERR#

REQ[3:0]#

REQ[4]# / GPIO[22]

REQ[5]# / GPIO[1]

GNT[3:0]# GNT[4]# / GPIO[48] GNT[5]# / GPIO[17]

CPUPWRGD / GPIO[49]

PIRQ[H:E]# / GPIO[5:2]

OC[5]# / GPIO[29] OC[6]# / GPIO[30] OC[7]# / GPIO[31]

SATA_CLKP, SATA_CLKN

DMI_CLKP, DMI_CLKN

GPIO[39:37,25:24,19,1

PME#

CLKRUN#

PCICLK

PCIRST#

PLOCK#

SERR#

SPI_CS# SPI_MISO SPI_MOSI

SPI_ARB

SPI_CLK

A20M# FERR#

IGNNE#

INIT#

INIT3_3#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

DPSLP#

SERIRQ

PIRQ[D:A]#

IDEIRQ

USBP[7:0]P

USBP[7:0]N

OC[4:0]#

USBRBIAS

USBRBIAS#

RTCX1 RTCX2

CLK14 CLK48

INTVRMEN

SPKR

RTCRST#

TP[3]

5:12,10:6]

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

PCI

Interface

SPI

Processor

Interface

Interrupt Interface

USB

RTC

Clocks

Misc.

Signals

General

Purpose

I/O

EEPROM

Interface

IDE

Interface

PCI

Express*

Interface

Serial ATA

Interface

Power Mgnt.

AC '97/

Intel®High

Definition

Audio Direct

Media

Interface

Firmware

Hub

LPC

Interface

SMBus

Interface

System

Mgnt.

Platform

LAN

Connect

Digital Home

DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW# (DSTOP) IORDY (DRSTB / WDMARDY#)

PETp[6:1], PETn[6:1] PERp[6:1], PERn[6:1]

SATA[2,0]TXP, SATA[2,0]TXN SATA[2,0]RXP, SATA[2,0]RXN SATARBIAS SATARBIAS# SATA[2,0]GP/GPIO[36,21] SATALED# SATACLKREQ#

THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# DPRSTP# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK LAN_RST# VRMPWRGD BMBUSY# / GPIO[0] STP_PCI# STP_CPU# BATLOW# DPRSLPVR PLTRST#

ACZ_RST#, ACZ_SYNC, ACZ_SDOUT

ACZ_SDIN[2:0] ACZ_BIT_CLK AZ_DOCK_EN# / GPIO[33] AZ_DOCK_RST# / GPIO[34]

DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP

FWH[3:0] / LAD[3:0] FWH[4] / LFRAME#

LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[0]# LDRQ[1]# / GPIO[23]

SMBDATA SMBCLK SMBALERT# / GPIO[11]

INTRUDER# SMLINK[1:0] LINKALERT#

LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC

El_RSVD / GPIO26 El_STATE[1:0] / GPIO[28:27

Digital Home Only

ICH7_Signals_Mobile

Intel ® ICH7 Family Datasheet 53

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Figure 2-3. Interface Signals Block Diagram (Ultra Mobile Only)

Signal Description

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY# TRDY# STOP#

PAR

PERR#

REQ4# / GPIO[22]

REQ5# / GPIO[1]

GNT4# / GPIO[48] GNT5# / GPIO[17]

CPUPWRGD / GPIO[49]

PIRQ[H:E]# / GPIO[5:2]

OC[5]# / GPIO[29] OC[6]# / GPIO[30] OC[7]# / GPIO[31]

DMI_CLKP, DMI_CLKN

REQ3#

GNT3]#

PME#

CLKRUN#

PCICLK

PCIRST#

PLOCK#

SERR#

A20M#

FERR#

IGNNE#

INIT#

INIT3_3#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

DPSLP#

SERIRQ

IDEIRQ

USBP[7:0]P USBP[7:0]N

OC[4:0]#

USBRBIAS

USBRBIAS#

RTCX1 RTCX2

CLK14 CLK48

PCI

Interface

Processor

Interface

Interrupt Interface

USB

RTC

Clocks

IDE

Interface

Power

Mgnt.

Intel®High

Definition

Audio

Direct

Media

Interface

Firmware

Hub

LPC

Interface

SMBus

Interface

System

Mgnt.

DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW#(DSTOP) IORDY(DRSTB / WDMARDY#)

THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# DPRSTP# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK

VRMPWRGD BMBUSY# / GPIO[0] STP_PCI# STP_CPU# BATLOW# DPRSLPVR PLTRST#

ACZ_RST#, ACZ_SYNC, ACZ_SDOUT ACZ_SDIN[2:0] ACZ_BIT_CLK

DMI[1:0]TXP, DMI[1:0]TXN DMI[1:0]RXP, DMI[1:0]RXN DMI_ZCOMP DMI_IRCOMP

FWH[3:0] / LAD[3:0] FWH[4] / LFRAME#

LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ0# LDRQ1# /GPIO[23]

SMBDATA SMBCLK SMBALERT# / GPIO[11]

INTRUDER# LINKALERT#

SPKR

RTCRST#

TP3

GPIO[39:37,25:24,19,1

54 Intel ® ICH7 Family Datasheet

5:12,10:6]

Misc.

Signals

General

Purpose

I/O

Page 55

Signal Description

2.1 Direct Media Interface (DMI) to Host Controller

Table 2-1. Direct Media Interface Signals

Name Type Description

DMI[0:1]TXP, DMI[0:1]TXN

DMI[2:3]TXP, DMI[2:3]TXN (Desktop and Mobile Only)

DMI[0:1]RXP, DMI[0:1]RXN

DMI[2:3]RXP, DMI[2:3]RXN (Desktop and Mobile Only)

DMI_ZCOMP I Impedance Compensation Input: Determines DMI input impedance.

DMI_IRCOMP O

O Direct Media Interface Differential Transmit Pair 0:3

I Direct Media Interface Differential Receive Pair 0:3

Impedance/Current Compensation Output: Determines DMI output impedance and bias current.

2.2 PCI Express* (Desktop and Mobile Only)

Table 2-2. PCI Express* Signals

Name Type Description

PETp[1:4], PETn[1:4]

PERp[1:4], PERn[1:4]

PETp[5:6], PETn[5:6]

(Intel® ICH7R/ ICH7DH/ICH7-M DH Only)

PERp[1:4], PERn[5:6] (ICH7R/ICH7DH/ ICH7-M DH Only)

O PCI Express* Differential Transmit Pair 1:4

I PCI Express Differential Receive Pair 1:4

PCI Express* Differential Transmit Pair 5:6

Reserved: ICH7/ICH7-M

PCI Express Differential Receive Pair 5:6

Reserved: ICH7/ICH7-M

Intel ® ICH7 Family Datasheet 55

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Signal Description

2.3 Platform LAN Connect Interface (Desktop and Mobile Only)

Table 2-3. Platform LAN Connect Interface Signals

Name Type Description

LAN_CLK I

LAN_RXD[2:0] I

LAN_TXD[2:0] O

LAN_RSTSYNC O

LAN I/F Clock: This signal is driven by the Platform LAN Connect component. The frequency range is 5 MHz to 50 MHz.

Received Data: The Platform LAN Connect component uses these signals to transfer data and control information to the integrated LAN controller. These signals have integrated weak pull-up resistors.

Transmit Data: The integrated LAN controller uses these signals to transfer data and control information to the Platform LAN Connect component.

LAN Reset/Sync: The Platform LAN Connect component’s Reset and Sync signals are multiplexed onto this pin.

2.4 EEPROM Interface (Desktop and Mobile Only)

Table 2-4. EEPROM Interface Signals

Name Type Description

EE_SHCLK O

EE_DIN I

EE_DOUT O

EE_CS O EEPROM Chip Select: This is the chip select signal to the EEPROM.

EEPROM Shift Clock: This signal is the serial shift clock output to the EEPROM.

EEPROM Data In: This signal transfers data from the EEPROM to the Intel® ICH7. This signal has an integrated pull-up resistor.

EEPROM Data Out: This signal transfers data from the ICH7 to the EEPROM.

2.5 Firmware Hub Interface (Desktop and Mobile Only)

Table 2-5. Firmware Hub Interface Signals

Name Type Description

FWH[3:0] /

LAD[3:0]

FWH4 /

LFRAME#

56 Intel ® ICH7 Family Datasheet

Firmware Hub Signals: These signals are multiplexed with the LPC

I/O

address signals. Firmware Hub Signals: This signal is multiplexed with the LPC LFRAME#

signal.

Page 57

Signal Description

2.6 PCI Interface

Table 2-6. PCI Interface Signals (Sheet 1 of 3)

Name Type Description

PCI Address/Data: AD[31:0] is a multiplexed address and data bus.

During the first clock of a transaction, AD[31:0] contain a physical

AD[31:0] I/O

C/BE[3:0]# I/O

DEVSEL# I/O

FRAME# I/O

IRDY# I/O

address (32 bits). During subsequent clocks, AD[31:0] contain data. The Intel®ICH7 will drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles.

Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables.

C/BE[3:0]# Command Type

0000b Interrupt Acknowledge 0001b Special Cycle 0010b I/O Read 0011b I/O Write 0110b Memory Read 0111b Memory Write 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1110b Memory Read Line 1111b Memory Write and Invalidate

All command encodings not shown are reserved. The ICH7 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values.

Device Select: The ICH7 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH7 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH7 address or an address destined DMI (main memory or graphics). As an input, DEVSEL# indicates the response to an ICH7-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PLTRST#. DEVSEL# remains tristated by the ICH7 until driven by a target device.

Cycle Frame: The current initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH7 when the ICH7 is the target, and FRAME# is an output from the ICH7 when the ICH7 is the initiator. FRAME# remains tri-stated by the ICH7 until driven by an initiator.

Initiator Ready: IRDY# indicates the ICH7's ability, as an initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH7 has valid data present on AD[31:0]. During a read, it indicates the ICH7 is prepared to latch data. IRDY# is an input to the ICH7 when the ICH7 is the target and an output from the ICH7 when the ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until driven by an initiator.

Intel ® ICH7 Family Datasheet 57

Page 58

Table 2-6. PCI Interface Signals (Sheet 2 of 3)

Name Type Description

Target Ready: TRDY# indicates the Intel®ICH7's ability as a target to

complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that

TRDY# I/O

STOP# I/O

PAR I/O

PERR# I/O

REQ[3:0]#

REQ4# /

GPIO22

REQ5# /

GPIO1

GNT[3:0]#

GNT4# /

GPIO48

GNT5# /

GPIO17#

PCICLK I

PCIRST# O

the ICH7, as a target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the ICH7, as a target is prepared to latch data. TRDY# is an input to the ICH7 when the ICH7 is the initiator and an output from the ICH7 when the ICH7 is a target. TRDY# is tri-stated from the leading edge of PLTRST#. TRDY# remains tri-stated by the ICH7 until driven by a target.

Stop: STOP# indicates that the ICH7, as a target, is requesting the initiator to stop the current transaction. STOP# causes the ICH7, as an initiator, to stop the current transaction. STOP# is an output when the ICH7 is a target and an input when the ICH7 is an initiator.

Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH7 counts the number of 1s within the 36 bits plus PAR and the sum is always even. The ICH7 calculates PAR on 36 bits regardless of the valid byte enables. The ICH7 generates PAR for address and data phases and only ensures PAR to be valid one PCI clock after the corresponding address or data phase. The ICH7 drives and tri-states PAR identically to the AD[31:0] lines except that the ICH7 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH7 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH7 is the initiator of a PCI write transaction, and when it is the target of a read transaction. ICH7 checks parity when it is the target of a PCI write transaction. If a parity error is detected, the ICH7 will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#.

Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH7 drives PERR# when it detects a parity error. The ICH7 can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal).

PCI Requests: The ICH7 supports up to 6 masters on the PCI bus. The REQ4# and REQ5# pins can instead be used as a GPIO.

NOTE: REQ[2:0]# are not on Ultra Mobile. PCI Grants: The ICH7 supports up to 6 masters on the PCI bus. The

GNT4# and GNT5# pins can instead be used as a GPIO. Pull-up resistors are not required on these signals. If pull-ups are used,

they should be tied to the Vcc3_3 power rail. GNT5#/GPIO17 has an internal pull-up.

NOTE: GNT[2:0]# are not on Ultra Mobile. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all

transactions on the PCI Bus.

NOTE: (Mobile/Ultra Mobile Only) This clock does not stop based on

STP_PCI# signal. PCI Clock only stops based on SLP_S3#.

PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the state of the Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6).

Signal Description

58 Intel ® ICH7 Family Datasheet

Page 59

Signal Description

Table 2-6. PCI Interface Signals (Sheet 3 of 3)

Name Type Description

PCI Lock: This signal indicates an exclusive bus operation and may

require multiple transactions to complete. The ICH7 asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. PLOCK# is

PLOCK# I/O

SERR# I/OD

PME# I/OD

ignored when PCI masters are granted the bus in desktop configurations. Devices on the PCI bus (other than the ICH7) are not permitted to assert the PLOCK# signal in mobile/Ultra Mobile configurations.

System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH7 has the ability to generate an NMI, SMI#, or interrupt.

PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1–S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the ICH7 may drive PME# active due to an internal wake event. The ICH7 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor.

2.7 Serial ATA Interface (Desktop and Mobile Only)

Table 2-7. Serial ATA Interface Signals (Sheet 1 of 2)

Name Type Description

SATA0TXP

SATA0TXN SATA0RXP

SATA0RXN

SATA1TXP

SATA1TXN

(Desktop Only)

SATA1RXP SATA1RXN

(Desktop Only)

SATA2TXP

SATA2TXN SATA2RXP

SATA2RXN

SATA3TXP

SATA3TXN

(Desktop Only)

SATA3RXP SATA3RXN

(Desktop Only)

SATARBIAS O

SATARBIAS# I

Serial ATA 0 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 0. Serial ATA 0 Differential Receive Pair: These are inbound high-

speed differential signals from Port 0.

Serial ATA 1 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 1. (Desktop Only)

Serial ATA 1 Differential Receive Pair: These are inbound high-

speed differential signals from Port 1. (Desktop Only)

Serial ATA 2 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 2. Serial ATA 2 Differential Receive Pair: These are inbound high-

speed differential signals from Port 2.

Serial ATA 3 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 3. (Desktop Only)

Serial ATA 3 Differential Receive Pair: These are inbound high-

speed differential signals from Port 3. (Desktop Only)

Serial ATA Resistor Bias: These are analog connection points for an external resistor to ground.

Serial ATA Resistor Bias Complement: These are analog connection points for an external resistor to ground.

Intel ® ICH7 Family Datasheet 59

Page 60

Table 2-7. Serial ATA Interface Signals (Sheet 2 of 2)

Name Type Description

Serial ATA 0 General Purpose: This is an input pin which can be

configured as an interlock switch corresponding to SATA Port 0.

SATA0GP /

GPIO21

SATA1GP

(Desktop Only)

/ GPIO19

SATA2GP /

GPIO36

SATA3GP

(Desktop Only)

/ GPIO37

SATALED# OC

SATACLKREQ#/

GPIO35

(Native)

I/O (GP)

When used as an interlock switch status indication, this signal should be drive to ‘0’ to indicate that the switch is closed and to ‘1’ to

indicate that the switch is open. If interlock switches are not required, this pin can be configured as

GPIO21. Serial ATA 1 General Purpose: Same function as SATA0GP, except

for SATA Port 1.

If interlock switches are not required, this pin can be configured as GPIO19.

Serial ATA 2 General Purpose: Same function as SATA0GP, except for SATA Port 2.

If interlock switches are not required, this pin can be configured as GPIO36.

Serial ATA 3 General Purpose: Same function as SATA0GP, except for SATA Port 3.

If interlock switches are not required, this pin can be configured as GPIO37.

Serial ATA LED: This is an open-collector output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is required.

NOTE: An internal pull-up is enabled only during PLTRST# assertion. Serial ATA Clock Request: This is an open-drain output pin when

configured as SATACLKREQ#. It is to connect to the system clock chip. When active, request for SATA Clock running is asserted. When

tri-stated, it tells the Clock Chip that SATA Clock can be stopped. An external pull-up resistor is required.

Signal Description

2.8 IDE Interface

Table 2-8. IDE Interface Signals (Sheet 1 of 2)

Name Type Description

IDE Device Chip Selects for 100 Range: For ATA command register

DCS1# O

DCS3# O

DA[2:0] O

DD[15:0] I/O

60 Intel ® ICH7 Family Datasheet

block. This output signal is connected to the corresponding signal on the IDE connector.

IDE Device Chip Select for 300 Range: For ATA control register block. This output signal is connected to the corresponding signal on the IDE connector.

IDE Device Address: These output signals are connected to the corresponding signals on the IDE connector. They are used to indicate which byte in either the ATA command block or control block is being addressed.

IDE Device Data: These signals directly drive the corresponding signals on the IDE connector. There is a weak internal pull-down resistor on DD7.

Page 61

Signal Description

Table 2-8. IDE Interface Signals (Sheet 2 of 2)

Name Type Description

IDE Device DMA Request: This input signal is directly driven from the

DRQ signal on the IDE connector. It is asserted by the IDE device to

DDREQ I

DDACK# O

DIOR# /

(DWSTB /

RDMARDY#)

DIOW# /

(DSTOP)

IORDY /

(DRSTB /

WDMARDY#)

request a data transfer, and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel. There is a weak internal pull-down resistor on this signal.

IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the IDE connector. DDACK# is asserted by the Intel® ICH7 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel.

Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data onto the DD lines. Data is latched by the ICH7 on the deassertion edge of DIOR#. The IDE device is selected either by the ATA register file chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge (DDAK#).

Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, ICH7 drives valid data on rising and falling edges of DWSTB.

Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, ICH7 deasserts RDMARDY# to pause burst data transfers.

Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the DD lines. Data is latched by the IDE device on the deassertion edge of DIOW#. The IDE device is

selected either by the ATA register file chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge (DDAK#).

Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst. I/O Channel Ready (PIO): This signal will keep the strobe active

(DIOR# on reads, DIOW# on writes) longer than the minimum width. It adds wait-states to PIO transfers.

Disk Read Strobe (Ultra DMA Reads from Disk): When reading from

disk, ICH7 latches data on rising and falling edges of this signal from the disk.

Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is de-asserted by the disk to pause burst data transfers.

Intel ® ICH7 Family Datasheet 61

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2.9 LPC Interface

Table 2-9. LPC Interface Signals

Name Type Description

Signal Description

LAD[3:0] /

FWH[3:0]

LFRAME# /

FWH4

LDRQ0#

LDRQ1# /

GPIO23

(Desktop

and Mobile

only)

LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-

I/O

ups are provided.

O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to external Super I/O device. An internal pull-up resistor is provided on

these signals. LDRQ1# may optionally be used as GPIO.

2.10 Interrupt Interface

Table 2-10. Interrupt Signals

Name Type Description

SERIRQ I/O

PIRQ[D:A]#

(Desktop

and Mobile

only)

PIRQ[H:E]# / GPIO[5:2]

IDEIRQ I

I/OD

Serial Interrupt Request: This pin implements the serial interrupt protocol.

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control register.

In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts.

In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO.

IDE Interrupt Request: This interrupt input is connected to the IDE drive.

62 Intel ® ICH7 Family Datasheet

Page 63

Signal Description

2.11 USB Interface

Table 2-11. USB Interface Signals

Name Type Description

USBP0P,

USBP0N,

USBP1P,

USBP1N

USBP2P,

USBP2N,

USBP3P,

USBP3N

USBP4P,

USBP4N,

USBP5P,

USBP5N

USBP6P,

USBP6N,

USBP7P,

USBP7N

OC[4:0]# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31

USBRBIAS O

USBRBIAS# I

I/O

Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. These ports can be routed to UHCI controller #1 or the EHCI controller.

NOTE: No external resistors are required on these signals. The

Intel®ICH7 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor

Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3. These ports can be routed to UHCI controller #2 or the EHCI controller.

NOTE: No external resistors are required on these signals. The ICH7

integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor

Universal Serial Bus Port [5:4] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 4 and 5. These ports can be routed to UHCI controller #3 or the EHCI controller.

NOTE: No external resistors are required on these signals. The ICH7

integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor

Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 6 and 7. These ports can be routed to UHCI controller #4 or the EHCI controller.

NOTE: No external resistors are required on these signals. The ICH7

integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor

Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred.

OC[7:5]# may optionally be used as GPIOs.

NOTE: OC[7:0]# are not 5 V tolerant. USB Resistor Bias: Analog connection point for an external resistor.

Used to set transmit currents and internal load resistors. USB Resistor Bias Complement: Analog connection point for an

external resistor. Used to set transmit currents and internal load resistors.

Intel ® ICH7 Family Datasheet 63

Page 64

2.12 Power Management Interface

Table 2-12. Power Management Interface Signals (Sheet 1 of 3)

Name Type Description

Platform Reset: The Intel®ICH7 asserts PLTRST# to reset devices

on the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH7 asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register

PLTRST# O

THRM# I

THRMTRIP# I

SLP_S3# O

SLP_S4# O

SLP_S5# O

PWROK I

CF9h). The ICH7 drives PLTRST# inactive a minimum of 1 ms after both PWROK and VRMPWRGD are driven high. The ICH7 drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h).

NOTE: PLTRST# is in the VccSus3_3 well. Thermal Alarm: THRM# is an active low signal generated by external

hardware to generate an SMI# or SCI. Thermal Trip: When low, this signal indicates that a thermal trip from

the processor occurred, and the ICH7 will immediately transition to a S5 state. The ICH7 will not wait for the processor stop grant cycle since the processor has overheated.

S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state.

NOTE: This pin must be used to control the DRAM power to use the

ICH7’s DRAM power-cycling feature. Refer to

Chapter 5.14.11.2 for details.

S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states.

Power OK: When asserted, PWROK is an indication to the ICH7 that core power has been stable for 99 ms and that PCICLK has been stable for 1 ms. An exception to this rule is if the system is in S3 which PWROK may or may not stay asserted even though PCICLK may be inactive. PWROK can be driven asynchronously. When PWROK is negated, the ICH7 asserts PLTRST#.

Signal Description

, in

HOT

NOTE: PWROK must deassert for a minimum of three RTC clock

Power Button: The Power Button will cause SMI# or SCI to indicate a

system request to go to a sleep state. If the system is already in a

PWRBTN# I

RI#

(Desktop and

Mobile Only)

64 Intel ® ICH7 Family Datasheet

sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S1-S4 states. This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input.

Ring Indicate: This signal is an input from a modem. It can be

enabled as a wake event, and this is preserved across power failures.

periods for the ICH7 to fully reset the power and properly generate the PLTRST# output.

Page 65

Signal Description

Table 2-12. Power Management Interface Signals (Sheet 2 of 3)

Name Type Description

System Reset: This pin forces an internal reset after being

SYS_RESET# I

RSMRST# I

LAN_RST#

(Desktop and

Mobile Only)

WAKE# I

MCH_SYNC# I

SUS_STAT# /

LPCPD#

SUSCLK O

VRMPWRGD I

BM_BUSY#

(Mobile/Ultra

Mobile Only) /

GPIO0

(Desktop Only)

CLKRUN#

(Mobile/Ultra

Mobile Only)/

GPIO32

(Desktop Only)

STP_PCI#

(Mobile/Ultra

Mobile Only) /

GPIO18

(Desktop Only)

debounced. The ICH7 will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system.

Resume Well Reset: This signal is used for resetting the resume power plane logic.

LAN Reset: When asserted, the internal LAN controller will be put into reset. This signal must be asserted for at least 10 ms after the resume well power (VccSus3_3 in desktop and VccLAN3_3 and VccLAN1_05 in

mobile) is valid. When deasserted, this signal is an indication that the resume (LAN for mobile) well power is stable.

NOTE: LAN_RST# should be tied to RSMRST#. PCI Express* Wake Event: Sideband wake signal on PCI Express

asserted by components requesting wake up. MCH SYNC: This input is internally ANDed with the PWROK input.

Connect to the ICH_SYNC# output of (G)MCH. Suspend Status: This signal is asserted by the ICH7 to indicate that

the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal

refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC interface.

Suspend Clock: This clock is an output of the RTC generator circuit to use by other chips for refresh clock.

VRM Power Good: This should be connected to be the processor’s VRM Power Good signifying the VRM is stable. This signal is internally ANDed with the PWROK input.

Bus Master Busy: This signal supports the C3 state. It provides an indication that a bus master device is busy. When this signal is asserted, the BM_STS bit will be set. If this signal goes active in a C3 state, it is treated as a break event.

NOTE: This signal is internally synchronized using the PCICLK and a

two-stage synchronizer. It does not need to meet any particular setup or hold time.

NOTE: In desktop configurations, this signal pin is a GPIO.

PCI Clock Run: This clock supports the PCI CLKRUN protocol. It

I/O

connects to peripherals that need to request clock restart or prevention of clock stopping.

Stop PCI Clock: This signal is an output to the external clock generator for it to turn off the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is not needed, this signal can

be configured as a GPIO.

NOTE: Refered to as STPPCI# on Ultra Mobile.

Intel ® ICH7 Family Datasheet 65

Page 66

Table 2-12. Power Management Interface Signals (Sheet 3 of 3)

Name Type Description

STP_CPU#

(Mobile/Ultra

Mobile Only) /

GPIO20

(Desktop Only)

BATLOW#

(Mobile/Ultra

Mobile Only) /

TP0

(Desktop Only)

DPRSLPVR

(Mobile/Ultra

Mobile Only) /

GPIO16

(Desktop Only)

DPRSTP#

(Mobile/Ultra

Mobile Only) /

TP1

(Desktop Only)

Stop CPU Clock: This signal is an output to the external clock generator for it to turn off the processor clock. It is used to support the C3 state. If this functionality is not needed, this signal can be

configured as a GPIO.

NOTE: Refered to as STPCPU# on Ultra Mobile.

Battery Low: This signal is an input from battery to indicate that

there is insufficient power to boot the system. Assertion will prevent

wake from S3–S5 state. This signal can also be enabled to cause an SMI# when asserted.

Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM during the C4 state. When the signal is high, the

voltage regulator outputs the lower “Deeper Sleep” voltage. When low (default), the voltage regulator outputs the higher “Normal” voltage.

O Deeper Stop: This is a copy of the DPRSLPVR and it is active low.

Signal Description

2.13 Processor Interface

Table 2-13. Processor Interface Signals (Sheet 1 of 3)

Name Type Description

A20M# O

CPUSLP# O

FERR# I

Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active.

CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The Intel® ICH7 can optionally assert the CPUSLP# signal when going to the S1 state. (Desktop Only)

Reserved. (Mobile/Ultra Mobile Only) Numeric Coprocessor Error: This signal is tied to the coprocessor error

signal on the processor. FERR# is only used if the ICH7 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Config Registers:Offset 31FFh: bit 1). If FERR# is asserted, the ICH7 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled.

NOTE: FERR# can be used in some states for notification by the processor

of pending interrupt events. This functionality is independent of the OIC register bit setting.

66 Intel ® ICH7 Family Datasheet

Page 67

Signal Description

Table 2-13. Processor Interface Signals (Sheet 2 of 3)

Name Type Description

Ignore Numeric Error: This signal is connected to the ignore error pin

on the processor. IGNNE# is only used if the ICH7 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Config

IGNNE# O

INIT# O

INIT3_3V#

(Desktop

and Mobile

Only)

INTR O

NMI O

SMI# O

STPCLK# O

RCIN# I

Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error register (I/O register F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error register is written, the IGNNE# signal is not asserted.

Initialization: INIT# is asserted by the ICH7 for 16 PCI clocks to reset the processor. ICH7 can be configured to support processor Built In Self Test (BIST).

Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended

for Firmware Hub.

CPU Interrupt: INTR is asserted by the ICH7 to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low.

Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the processor. The ICH7 can generate an NMI when either SERR# is asserted or IOCHK# goes active via the SERIRQ# stream. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control register (I/O Register 61h).

System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH7 in response to one of many enabled hardware or software events.

Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH7 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock.

Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH7’s other sources of INIT#. When the ICH7 detects the assertion of this signal, INIT# is generated for 16 PCI clocks.

NOTE: The ICH7 will ignore RCIN# assertion during transitions to the S1,

S3, S4, and S5 states.

Intel ® ICH7 Family Datasheet 67

Page 68

Table 2-13. Processor Interface Signals (Sheet 3 of 3)

Name Type Description

Signal Description

A20GATE I

CPUPWRGD

/ GPIO49

DPSLP#

(Mobile/Ultra

Mobile Only)

/ TP2

(Desktop

Only)

A20 Gate: A20GATE is from the keyboard controller. The signal acts as an alternative method to force the A20M# signal active. It saves the external OR gate needed with various other chipsets.

CPU Power Good: This signal should be connected to the processor’s PWRGOOD input to indicate when the CPU power is valid. This is an output signal that represents a logical AND of the ICH7’s PWROK and VRMPWRGD

signals. This signal may optionally be configured as a GPIO.

Deeper Sleep: DPSLP# is asserted by the ICH7 to the processor. When the signal is low, the processor enters the deep sleep state by gating off

the processor core clock inside the processor. When the signal is high (default), the processor is not in the deep sleep state.

2.14 SMBus Interface

Table 2-14. SM Bus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# /

GPIO11

SMBus Alert: This signal is used to wake the system or generate

SMI#. If not used for SMBALERT#, it can be used as a GPIO.

2.15 System Management Interface

Table 2-15. System Management Interface Signals

Name Type Description

Intruder Detect: This signal can be set to disable the system if the

INTRUDER# I

SMLINK[1:0]

(Desktop

and Mobile

Only)

LINKALERT#

(Desktop

and Mobile

Only)

68 Intel ® ICH7 Family Datasheet

I/OD

chasis is detected open. This signal’s status is readable, so it can be used like a GPIO if the Intruder Detection is not needed.

System Management Link: These signals provide a SMBus link to optional external system management ASIC or LAN controller. External pull-ups are required. Note that SMLINK0 corresponds to an SMBus clock signal, and SMLINK1 corresponds to an SMBus Data signal.

SMLink Alert: This signal is an output of the integrated LAN and input to either the integrated ASF or an external management controller in order for the LAN’s SMLINK slave to be serviced.

Page 69

Signal Description

2.16 Real Time Clock Interface

Table 2-16. Real Time Clock Interface

Name Type Description

Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If

RTCX1 Special

RTCX2 Special

no external crystal is used, RTCX1 can be driven with the desired clock rate.

Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, RTCX2 should be left floating.

2.17 Other Clocks

Table 2-17. Other Clocks

Name Type Description

CLK14 I

CLK48 I

SATA_CLKP SATA_CLKN

(Desktop

and Mobile

Only)

DMI_CLKP,

DMI_CLKN

Oscillator Clock: This clock signal is used for the 8254 timers. It runs at

14.31818 MHz. This clock is permitted to stop during S3 (or lower) states.

48 MHz Clock: This clock signal is used to run the USB controller. It runs at 48.000 MHz. This clock is permitted to stop during S3 (or lower) states.

100 MHz Differential Clock: These signals are used to run the SATA

controller at 100 MHz. This clock is permitted to stop during S3/S4/S5 states.

100 MHz Differential Clock: These signals are used to run the Direct

Media Interface. They run at 100 MHz.

Intel ® ICH7 Family Datasheet 69

Page 70

2.18 Miscellaneous Signals

Table 2-18. Miscellaneous Signals

Name Type Description

INTVRMEN

(Desktop and

Mobile Only)

SPKR O

Internal Voltage Regulator Enable: This signal enables the internal

1.05 V Suspend regulator when connected to VccRTC. When connected to Vss, the internal regulator is disabled

Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PLTRST#, its output state is 0.

NOTE: SPKR is sampled at the rising edge of PWROK as a functional

strap. See Section 2.24.1 for more details. There is a weak integrated pull-down resistor on SPKR pin.

RTC Reset: When asserted, this signal resets register bits in the RTC well.

Signal Description

RTCRST#

(Desktop and

Mobile Only)

TP0

(Desktop

Only) /

BATLOW#

(Mobile/Ultra

Mobile Only)

TP1

(Desktop

Only) /

DPRSTP#

(Mobile/Ultra

Mobile Only)

TP2

(Desktop

Only) /

DPSLP#

(Mobile/Ultra

Mobile Only)

TP3 I/O Test Point 3: Route signal to a test point.

NOTES:

1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must be high when all other RTC

2. In the case where the RTC battery is dead or missing on the

I Test Point 0: This signal must have an external pull-up to VccSus3_3.

O Test Point 1: Route signal to a test point.

O Test Point 2: Route signal to a test point.

power planes are on.

platform, the RTCRST# pin must rise before the RSMRST# pin.

70 Intel ® ICH7 Family Datasheet

Page 71

Signal Description

2.19 AC ’97/Intel® High Definition Audio Link

Note: AC ‘97 is not supported on Ultra Mobile.

Table 2-19. AC ’97/Intel® High Definition Audio Link Signals

1,2

Name

ACZ_RST# O

ACZ_SYNC O

ACZ_BIT_CLK I/O

ACZ_SDOUT O

ACZ_SDIN[2:0] I

AZ_DOCK_EN#

(Mobile Only) /

GPIO33

AZ_DOCK_RST#

(Mobile Only) /

GPIO34

NOTES:

1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details.

2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0 AC ‘97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode).

Type Description

AC ’97/Intel®High Definition Audio Reset: This signal is the

master hardware reset to external codec(s). AC ’97/Intel High Definition Audio Sync: This signal is a 48 kHz

fixed rate sample sync to the codec(s). It is also used to encode the stream number.

AC ’97 Bit Clock Input: This signal is a 12.288 MHz serial data clock generated by the external codec(s). This signal has an integrated pull-down resistor (see Note below).

Intel High Definition Audio Bit Clock Output: This signal is a

24.000 MHz serial data clock generated by the Intel High Definition Audio controller (the Intel®ICH7). This signal has an integrated pulldown resistor so that ACZ_BIT_CLK doesn’t float when an Intel High Definition Audio codec (or no codec) is connected but the signals are temporarily configured as AC ’97.

AC ’97/Intel High Definition Audio Serial Data Out: This signal is the serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel High Definition Audio.

NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a

functional strap. See Section 2.24.1 for more details. There is a weak integrated pull-down resistor on the ACZ_SDOUT pin.

AC ’97/Intel High Definition Audio Serial Data In [2:0]: These signals are serial TDM data inputs from the three codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel®High Definition Audio. These signals have integrated pull-down resistors that are always enabled.

High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active low signal. When deasserted, the external docking switch is in isolate mode. When asserted, the external docking switch electrically connects the Intel HD Audio dock signals to the corresponding Intel

I/O

ICH7 signals. This signal is shared with GPIO33. This signal defaults to GPIO33

mode after PLTRST# reset and will be in the high state after PLTRST# reset. BIOS is responsible for configuring GPIO33 to AZ_DOCK_EN# mode.

High Definition Audio Dock Reset: This signal is a dedicated AZ_RST# signal for the codec(s) in the docking station. Aside from operating independently from the normal ACZ_RST# signal, it otherwise works similarly to the ACZ_RST# signal.

I/O

This signal is shared with GPIO34. This signal defaults to GPIO34 mode after PLTRST# reset and will be in the low state after PLTRST# reset. BIOS is responsible for configuring GPIO34 to AZ_DOCK_RST# mode.

Intel ® ICH7 Family Datasheet 71

Page 72

Signal Description

2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

Table 2-20. Serial Peripheral Interface (SPI) Signals

Name Type Description

SPI_CS# I/O

SPI_MISO I

SPI_MOSI O

SPI_ARB I

SPI_CLK O

SPI Chip Select: This chip select signal is also used as the SPI bus request signal.

SPI Master IN Slave OUT: This signal is the data input pin for Intel® ICH7.

SPI Master OUT Slave IN: This signal is the data output pin for ICH7.

SPI Arbitration: SPI_ARB is the SPI arbitration signal used to arbitrate the SPI bus with Intel PRO 82573E Gigabit Ethernet Controller when Shared Flash is implemented.

SPI Clock: This signal is the SPI clock signal. During idle, the bus owner will drive the clock signal low. 17.86 MHz.

2.21 Intel® Quick Resume Technology (Intel® ICH7DH Only)

Signal Name Type Description

Intel® Quick Resume Technology Reserved: This signal is

EL_RSVD /

GPIO26

EL_STATE[1:0] /

GPIO[28:27]

reserved and should be left as a no connect when Intel Quick Resume Technology is enabled.

I/O

NOTE: This signal cannot be reused as a GPIO when Intel Quick

Resume Technology is enabled.

Intel Quick Resume Technology State: Intel Quick Resume

I/O

Technology status signals that may optionally be used to drive front chassis indicators. See Section 5.26.3 for details.

2.22 General Purpose I/O Signals

Table 2-21. General Purpose I/O Signals (Sheet 1 of 3)

1,2

Name

GPIO49 I/O V_CPU_IO V_CPU_IO Native Multiplexed with CPUPWRGD

GPIO48 I/O 3.3 V Core Native Multiplexed with GNT4# GPIO[47:40] N/A N/A N/A N/A Not implemented. GPIO[39:38]

(Desktop and

Mobile Only)

GPIO37

(Desktop and

Mobile Only)

72 Intel ® ICH7 Family Datasheet

Type Tolerance

I/O 3.3 V Core GPI Unmultiplexed.

I/O 3.3 V Core GPI Multiplexed with SATA3GP.

Power

Well

Default Description

Page 73

Signal Description

Table 2-21. General Purpose I/O Signals (Sheet 2 of 3)

Name

1,2

Type Tolerance

Power

Well

Default Description

GPIO36

(Desktop and

I/O 3.3 V Core GPI Multiplexed with SATA2GP.

Mobile Only)

GPIO35

(Desktop and

I/O 3.3 V Core GPO Multiplexed with SATACLKREQ#.

Mobile Only)

GPIO34

(Desktop and

Mobile Only)

GPIO33

(Desktop and

Mobile Only)

I/O 3.3 V Core GPO

Mobile Only: Multiplexed with AZ_DOCK_RST#.

Desktop Only: Unmultiplexed. Mobile Only: Multiplexed with

AZ_DOCK_EN#. Desktop Only: Unmultiplexed. Mobile/Ultra Mobile Only: this

GPIO32

(Desktop Only)

I/O 3.3 V Core GPO

GPIO is not implemented and is used instead as CLKRUN#.

Desktop Only: Unmultiplexed. GPIO31 I/O 3.3 V Resume Native Multiplexed with OC7# GPIO30 I/O 3.3 V Resume Native Multiplexed with OC6# GPIO29 I/O 3.3 V Resume Native Multiplexed with OC5#

ICH7, ICH7R, and Mobile

GPIO28

(Desktop and

Mobile Only)

GPIO27

(Desktop and

Mobile Only)

GPIO26

(Desktop and

Mobile Only)

I/O 3.3 V Resume GPO

Intel

Only: Unmultiplexed.

ICH7DH Only: Multiplexed with

EL_STATE1

Intel® ICH7, ICH7R, and Mobile

Only: Unmultiplexed.

ICH7DH Only: Multiplexed with

EL_STATE0

Intel® ICH7, ICH7R, and Mobile

Only: Unmultiplexed.

ICH7DH Only: Multiplexed with

EL_RSVD GPIO25

(Desktop and

I/O 3.3 V Resume GPO Unmultiplexed.

Mobile Only)

GPIO24

(Desktop and

Mobile Only)

I/O 3.3 V Resume GPO

Unmultiplexed. Not cleared by

CF9h reset event. GPIO23

(Desktop and

I/O 3.3 V Core Native Multiplexed with LDRQ1#

Mobile Only)

GPIO22 I/O 3.3 V Core Native Multiplexed with REQ4# GPIO21

(Desktop and

I/O 3.3 V Core GPI Multiplexed with SATA0GP.

Mobile Only)

Mobile/Ultra Mobile Only: GPIO is GPIO20

(Desktop Only)

I/O 3.3 V Core GPO

not implemented and is used

instead as STP_CPU#.

Desktop Only: Unmultiplexed.

Intel ® ICH7 Family Datasheet 73

Page 74

Table 2-21. General Purpose I/O Signals (Sheet 3 of 3)

Signal Description

Name

1,2

Type Tolerance

Power

Well

Default Description

GPIO19

(Desktop and

I/O 3.3 V Core GPI Multiplexed with SATA1GP.

Mobile Only)

Mobile/Ultra Mobile Only: GPIO is

GPIO18

(Desktop Only)

I/O 3.3 V Core GPO

not implemented and is used instead as STP_PCI#.

Desktop Only: Unmultiplexed.

GPIO17 I/O 3.3 V Core GPO Multiplexed with GNT5#.

Native

GPIO16 I/O 3.3 V Core

(Mobile/

Ultra

Mobile) /

GPO

Mobile/Ultra Mobile Only: Natively used as DPRSLPVR.

Desktop Only: Unmultiplexed.

(Desktop)

GPIO[15:12] I/O 3.3 V Resume GPI Unmultiplexed.

GPIO11 I/O 3.3 V Resume Native Multiplexed with SMBALERT#

GPIO[10:8] I/O 3.3 V Resume GPI Unmultiplexed.

GPIO[7:6] I/O 3.3 V Core GPI Unmultiplexed. GPIO[5:2] I/OD 5 V Core GPI Multiplexed with PIRQ[H:E]#.

GPIO1 I/O 5 V Core GPI Multiplexed with REQ5#. GPIO0

(Desktop Only)

I/O 3.3 V Core GPI

Mobile/Ultra Mobile Only: Multiplexed with BM_BUSY#.

Desktop Only: Unmultiplexed

NOTES:

1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI, but not both.

2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some ICH7 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down.

2.23 Power and Ground

Table 2-22. Power and Ground Signals (Sheet 1 of 3)

Name Description

Vcc3_3

Vcc1_05

Vcc1_5_A

Vcc1_5_B

V5REF

(Desktop and

Mobile Only)

74 Intel ® ICH7 Family Datasheet

These pins provide the 3.3 V supply for core well I/O buffers (22pins). This power may be shut off in S3, S4, S5 or G3 states.

These pins provide the 1.05 V supply for core well logic (20 pins). This power may be shut off in S3, S4, S5 or G3 states.

These pins provide the 1.5 V supply for Logic and I/O (30 pins). This power may be shut off in S3, S4, S5 or G3 states.

These pins provide the 1.5 V supply for Logic and I/O (53 pins). This power may be shut off in S3, S4, S5 or G3 states.

These pins provide the reference for 5 V tolerance on core well inputs (2 pins). This power may be shut off in S3, S4, S5 or G3 states.

Page 75

Signal Description

Table 2-22. Power and Ground Signals (Sheet 2 of 3)

Name Description

V5REF1

(Ultra Mobile

Only)

V5REF2

(Ultra Mobile

Only)

VccSus3_3

VccSus1_05

V5REF_Sus

VccLAN3_3

(Mobile Only)

These pins provide the reference for 5 V tolerance on core well inputs (1 pin). This power may be shut off in S3, S4, S5 or G3 states.

These pins provide the 3.3 V supply for resume well I/O buffers (24 pins). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations.

These pins provide the 1.05 V supply for resume well logic (5 pins). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations.

This voltage may be generated internally (see Section 2.24.1 for strapping option). If generated internally, these pins should not be connected to an external supply.

This pin provides the reference for 5 V tolerance on resume well inputs (1 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations.

These pins provide the 3.3 V supply for LAN Connect interface buffers (4 pins). This is a separate power plane that may or may not be powered in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1.

VccLAN1_05

(Mobile Only)

VccSusHDA

(Mobile/Ultra

Mobile Only)

VccHDA

(Mobile/Ultra

Mobile Only)

NOTE: In Desktop mode these signals are added to the VccSus3_3 group. These pins provide the 1.05 V supply for LAN controller logic (2 pins). This is a

separate power plane that may or may not be powered in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1.

NOTE: This voltage will be generated internally if VccSus1_05 is generated

internally (see Section 2.24.1 for strapping option). If generated internally, these pins should not be connected to an external supply.

NOTE: In Desktop mode these signals are added to the VccSus1_05 group. This pin provides the suspend supply for Intel High Definition Audio (1 pins).

This pin can be either 1.5 V or 3.3 V. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations.

NOTE: In Desktop mode this signal is added to the VccSus3_3 group. This pin provides the core supply for Intel High Definition Audio (1 pin). This pin

can be either 1.5 V or 3.3 V. This power may be shut off in S3, S4, S5 or G3 states. This plane must be on in S0 and S1.

NOTE: In Desktop mode these signals are added to the Vcc3_3 group.

Intel ® ICH7 Family Datasheet 75

Page 76

Table 2-22. Power and Ground Signals (Sheet 3 of 3)

Name Description

This pin provides the 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This power is not expected to be shut off unless the RTC

VccRTC

VccUSBPLL

(Desktop and

Mobile Only)

VccDMIPLL

VccSATAPLL

(Desktop and

Mobile Only)

V_CPU_IO

Vss Grounds (194 pins).

battery is removed or completely drained.

NOTE: Implementations should not attempt to clear CMOS by using a jumper to

pull VccRTC low. Clearing CMOS in an Intel®ICH7-based platform can be done by using a jumper on RTCRST# or GPI.

This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not used.

This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.

This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA not used.

These pins are powered by the same supply as the processor I/O voltage (3 pins). This supply is used to drive the processor interface signals listed in

Table 2-13.

Signal Description

2.24 Pin Straps

2.24.1 Functional Straps

The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled.

Table 2-23. Functional Strap Definitions (Sheet 1 of 3)

Signal Usage

XOR Chain

Entrance /

ACZ_SDOUT

ACZ_SYNC

EE_CS

(Desktop

and Mobile

Only)

Express*

Port Config

PCI Express

Port Config

Reserved

PCI

bit 1

bit 0

When

Sampled

Rising Edge of

PWROK

Rising Edge of

PWROK

Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK. See Chapter 25 for XOR Chain functionality information.

When TP3 not pulled low at rising edge of PWROK, sets bit 1 of RPC.PC (Chipset Configuration Registers:Offset 224h). See Section 7.1.34 for details.

This signal has a weak internal pull-down. This signal has a weak internal pull-down.

Sets bit 0 of RPC.PC (Chipset Configuration Registers:Offset 224h). See Section 7.1.34 for details.

This signal has a weak internal pull-down.

NOTE: This signal should not be pulled high.

Comment

76 Intel ® ICH7 Family Datasheet

Page 77

Signal Description

Table 2-23. Functional Strap Definitions (Sheet 2 of 3)

Signal Usage

EE_DOUT

(Desktop

and Mobile

Reserved

Only)

GNT2# Reserved

Top-Block

GNT3#

Override

GNT5# /

GPIO17#,

GNT4# /

GPIO48

Boot BIOS

Destination

Selection

GPIO16

(Desktop

Only) /

DPRSLPVR

Reserved

(Mobile/Ultra

Mobile Only)

DMI AC/DC

Coupling

GPIO25

Selection (Desktop

INTVRMEN

(Desktop

and Mobile

Only)

Integrated

VccSus1_05

Enable/

Disable

Swap

Only)

VRM

When

Sampled

Rising Edge of

PWROK

Rising Edge of

PWROK

Rising Edge of

RSMRST#

Always

Comment

This signal has a weak internal pull-up. NOTE: This signal should not be pulled low.

The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the “top-block swap” mode (Intel

ICH7 inverts A16 for all cycles targeting FWH BIOS space). The status of this strap is readable via the Top Swap bit (Chipset Configuration Registers:Offset 3414h:bit 0). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

This field determines the destination of accesses to the BIOS memory range. Signals have weak internal pull-ups. Also controllable via Boot BIOS Destination bit (Chipset Configuration Registers:Offset 3410h:bit 11:10)

(GNT5# is MSB) 01 = SPI (Desktop and Mobile Only) 10 = PCI 11 = LPC

This signal has a weak internal pull-down.

NOTE: This signal should not be pulled high.

This signal has a weak internal pull-up.The internal

pull-up is disabled within 100 ms after RSMRST# deasserts.

If the signal is sampled high, the DMI interface is strapped to operate in DC coupled mode (No coupling capacitors are required on DMI differential pairs).

If the signal is sampled low, the DMI interface is strapped to operate in AC coupled mode (Coupling capacitors are required on DMI differential pairs).

NOTE: Board designer must ensure that DMI

implementation matches the strap selection.

NOTE: The signal must be held low at least 2 us after

RSMRST# deassertion to enable AC coupled mode.

Enables integrated VccSus1_05 VRM when sampled high.

Intel ® ICH7 Family Datasheet 77

Page 78

Table 2-23. Functional Strap Definitions (Sheet 3 of 3)

Signal Description

Signal Usage

When

Sampled

LINKALERT#

(Desktop

and Mobile

Reserved This signal requires an external pull-up resistor.

Only)

REQ[4:1]#

SATALED#

(Desktop

and Mobile

Only)

XOR Chain

Selection

Reserved

Rising Edge of

PWROK

See Chapter 25 for functionality information.

This signal has a weak internal pull-up enabled only when PLTRST# is asserted. NOTE: This signal should not be pulled low.

The signal has a weak internal pull-down. If the signal is sampled high, this indicates that the system is strapped to the “No Reboot” mode (ICH7 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO

SPKR No Reboot

Rising Edge of

PWROK

REBOOT bit (Chipset Config Registers:Offset 3410h:bit 5).

See Chapter 25 for functionality information. This

TP3

XOR Chain

Entrance

Rising Edge of

PWROK

signal has a weak internal pull-up. NOTE: This signal should not be pulled low unless

using XOR Chain testing.

NOTE: See Section 3.1for full details on pull-up/pull-down resistors.

Comment

2.24.2 External RTC Circuitry

To reduce RTC well power consumption, the ICH7 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. Figure 2-4 shows an example schematic recommended to ensure correct operation of the ICH7 RTC.

Figure 2-4. Example External RTC Circuit

VccSus3_3

1 K

Vbatt

NOTE: C1 and C2 depend on crystal load.

Schottky

Diodes

20 K

+ –

1 µF

(20% tolerance)

1 µF

(20% tolerance)

32.768 kHz Xtal

15 pF

(5% tolerance)

15 pF

(5% tolerance)

VCCRTC

RTCX2

10 M

RTCX1

RTCRST#

78 Intel ® ICH7 Family Datasheet

Page 79

Intel® ICH7 Pin States

3 Intel® ICH7 Pin States

3.1 Integrated Pull-Ups and Pull-Downs

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)

Signal Resistor Nominal Notes

ACZ_BIT_CLK, AC ‘97 (Desktop and Mobile Only)

ACZ_RST#, AC ‘97 (Desktop and Mobile Only)

ACZ_SDIN[2:0], AC ‘97 (Desktop and Mobile Only)

ACZ_SDOUT, AC ‘97 (Desktop and Mobile Only)

ACZ_SYNC, AC ‘97 (Desktop and Mobile Only)

ACZ_BIT_CLK, Intel®High Definition Audio

ACZ_RST#, Intel High Definition Audio None N/A 2 ACZ_SDIN[2:0], Intel High Definition

Audio ACZ_SDOUT, Intel High Definition Audio Pull-down 20 k 1, 2 ACZ_SYNC, Intel High Definition Audio Pull-down 20 k 2, 4 DD7 Pull-down 11.5 k 8 DDREQ Pull-down 11.5 k 8 DPRSLPVR / GPIO16 Pull-down 20 k 4, 9 EE_CS (Desktop and Mobile Only) Pull-down 20 k 10, 11 EE_DIN (Desktop and Mobile Only) Pull-up 20 k 10 EE_DOUT (Desktop and Mobile Only) Pull-up 20 k 10 GNT[1:0] Pull-up 20 k 10, 12 GNT[3:2],

GNT4# / GPIO48 GNT5# / GPIO17

GPIO25 Pull-up 20 k 10, 13 LAD[3:0]# / FHW[3:0]# Pull-up 20 k 10 LAN_CLK (Desktop and Mobile Only) Pull-down 100 k 14 LAN_RXD[2:0] (Desktop and Mobile

Only) LDRQ[0] Pull-up 20 k 10 LDRQ1 / GPIO23 Pull-up 20 k 10 PME# Pull-up 20 k 10 PWRBTN# Pull-up 20 k 10 SATALED# Pull-up 15 k 16

Pull-down 20 k 1, 2, 3

Pull-down 20 k 1, 2, 4

Pull-down 20 k 2, 4

Pull-down 20 k 2, 4, 5

Pull-Down 20 k 2, 6, 7

Pull-down 20 k 2, 4

Pull-up 20 k 10, 19

Pull-up 20 k 15

Intel ® ICH7 Family Datasheet 79

Page 80

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2)

Signal Resistor Nominal Notes

SPI_ARB (Desktop and Mobile Only) Pull-down 20 k 10 SPI_CLK (Desktop and Mobile Only) Pull-down 20 k 10 SPKR Pull-down 20 k 4 TP3 Pull-up 20 k 17 USB[7:0] [P,N] Pull-down 15 k 18

NOTES:

1. The pull-down resistors on ACZ_BIT_CLK (AC ‘97) and ACZ_RST# are enabled when either:

- The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or

- Both Function 2 and Function 3 of Device 30 are disabled.

2. The AC ‘97/Intel High Definition Audio Link signals may either all be configured to be an

3. Simulation data shows that these resistor values can range from 10 k to 20 k

4. Simulation data shows that these resistor values can range from 9 k to 50 k .

5. The pull-down resistors on ACZ_SYNC (AC ‘97) and ACZ_SDOUT (AC ‘97) are enabled

6. Simulation data shows that these resistor values can range from 10 k to 40 k .

7. The pull-down on this signal (in Intel High Definition Audio mode) is only enabled when in

8. Simulation data shows that these resistor values can range from 5.7 k to 28.3 k .

9. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

10. Simulation data shows that these resistor values can range from 15 k to 35 k

11. The pull-down on this signal is only enabled when LAN_RST# is asserted.

12. The internal pull-up is enabled only when the PCIRST# pin is driven low and the PWROK

13. Internal pull-up is enabled during RSMRST# and is disabled within 100 ms after RSMRST#

14. Simulation data shows that these resistor values can range from 45 k to 170 k

15. Simulation data shows that these resistor values can range from 15 k to 30 k .

16. Simulation data shows that these resistor values can range from 10 k to 20 k . The

17. Simulation data shows that these resistor values can range from 10 kW to 30 kW.

18. Simulation data shows that these resistor values can range from 14.25 k to 24.8 k

19. The internal pull-up is enabled only when PCIRST# is low.

Otherwise, the integrated Pull-down resistor is disabled.

AC-Link or an Intel High Definition Audio Link.

during reset and also enabled when either:

- The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or

- Both Function 2 and Function 3 of Device 30 are disabled.

Otherwise, the integrated Pull-down resistor is disabled.

COLD

indication is high.

de-asserts.

internal pull-up is only enabled only during PLTRST# assertion.

Intel® ICH7 Pin States

3.2 IDE Integrated Series Termination Resistors

Table 3-2 shows the ICH7 IDE signals that have integrated series termination resistors.

Table 3-2. IDE Series Termination Resistors

Signal Integrated Series Termination Resistor Value

DD[15:0], DIOW#, DIOR#, DREQ,

DDACK#, IORDY, DA[2:0], DCS1#,

DCS3#, IDEIRQ

NOTE: Simulation data indicates that the integrated series termination resistors are a nominal

33 but can range from 21 to 75 .

80 Intel ® ICH7 Family Datasheet

approximately 33 (See Note)

Page 81

Intel® ICH7 Pin States

3.3 Output and I/O Signals Planes and States

Table 3-3 and Table 3-4 show the power plane associated with the output and I/O

signals, as well as the state at various times. Within the table, the following terms are used:

“High-Z” Tri-state. ICH7 not driving the signal high or low. “High” ICH7 is driving the signal to a logic 1 “Low” ICH7 is driving the signal to a logic 0 “Defined” Driven to a level that is defined by the function (will be high or

low) “Undefined” ICH7 is driving the signal, but the value is indeterminate. “Running” Clock is toggling or signal is transitioning because function not

stopping “Off” The power plane is off, so ICH7 is not driving

Note that the signal levels are the same in S4 and S5, except as noted. ICH7 suspend well signal states are indeterminate and undefined and may glitch,

including input signals acting as outputs, prior to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion.

ICH7 core well signal states are indeterminate and undefined and may glitch, including input signals acting as outputs, prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK assertion.

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 1 of 5)

Immediately

PLTRST#1 /

RSMRST#

DMI

after

S1 S3

Defined Off Off

COLD

Signal Name

PETp[4:1],

PETn[4:1]

PETp[6:5],

PETn[6:5]

(Intel® ICH7R and

ICH7DH Only)

DMI[3:0]TXP,

DMI[3:0]TXN

Power

Plane

Core High High

During

PLTRST#1 /

RSMRST#

PCI Express*

S4/S5

Intel ® ICH7 Family Datasheet 81

Page 82

Intel® ICH7 Pin States

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 2 of 5)

Immediately

PLTRST#1 /

RSMRST#

after

S1 S3

COLD

S4/S5

Signal Name

Power

Plane

During

PLTRST#1 /

RSMRST#

PCI Bus

AD[31:0] Core Low Undefined Defined Off Off

C/BE[3:0]# Core Low Undefined Defined Off Off

DEVSEL# Core High-Z High-Z High-Z Off Off

FRAME# Core High-Z High-Z High-Z Off Off

GNT[3:0]# GNT4# / GPIO48 GNT5# / GPIO17

Core

High-Z with

Internal Pull-

High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z Off Off

PAR Core Low Undefined Defined Off Off

PCIRST# Suspend Low High High Low Low

PERR# Core High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z Off Off

LPC Interface

LAD[3:0] /

FWH[3:0]

Core High High High Off Off

LFRAME# / FWH[4] Core High High High Off Off

LAN Connect and EEPROM Interface

EE_CS Suspend Low Running Defined Defined Defined

EE_DOUT Suspend High High Defined Defined Defined

EE_SHCLK Suspend High-Z Running Defined Defined Defined LAN_RSTSYNC Suspend High Low Defined Defined Defined LAN_TXD[2:0] Suspend Low Low Defined Defined Defined

IDE Interface

DA[2:0] Core Undefined Undefined Undefined Off Off

DCS1#, DCS3# Core High High High Off Off

DD[15:8], DD[6:0] Core High-Z High-Z High-Z Off Off

DD[7] Core Low Low Low Off Off

DDACK# Core High High High Off Off

DIOR#, DIOW# Core High High High Off Off

SATA Interface

SATA[3:0]TXP, SATA[3:0]TXN

Core High-Z High-Z Defined Off Off

SATALED# Core High-Z High-Z Defined Off Off

82 Intel ® ICH7 Family Datasheet

Page 83

Intel® ICH7 Pin States

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 3 of 5)

Immediately

PLTRST#1 /

RSMRST#

after

S1 S3

COLD

S4/S5

Signal Name

Power

Plane

During

PLTRST#1 /

RSMRST#

SATARBIAS Core High-Z High-Z High-Z Off Off

SATA3GP / GPIO37 SATA2GP / GPIO36 SATA1GP / GPIO19

Core Input Input Driven Driven Driven

SATA0GP / GPIO21

SATACLKREQ# /

GPIO35

Core Low Low Defined Off Off

Interrupts

PIRQ[A:D]#,

PIRQ[H:E]# /

Core High-Z High-Z High-Z Off Off

GPIO[5:2]

SERIRQ Core High-Z High-Z High-Z Off Off

USB Interface

USBP[7:0][P,N] Suspend Low Low Low Low Low

USBRBIAS Suspend High-Z High-Z Defined Defined Defined

OC[7:5]# /

GPIO[31:29]

Suspend Input Input Driven Driven Driven

Power Management

PLTRST# Suspend Low High High Low Low SLP_S3# Suspend Low High High Low Low SLP_S4# Suspend Low High High High Low SLP_S5# Suspend Low High High High Low

SUS_STAT# Suspend Low High High Low Low

SUSCLK Suspend Low Running

Processor Interface

Dependant

A20M# Core

on A20GATE

See Note 6 High Off Off

Signal

CPUPWRGD /

GPIO49

Core Defined High

High Off Off

CPUSLP# Core High High Defined Off Off

IGNNE# Core High See Note 6 High Off Off

INIT# Core High High High Off Off

INIT3_3V# Core High High High Off Off

INTR Core See Note 6 See Note 8 Low Off Off

NMI Core See Note 6 See Note 8 Low Off Off

SMI# Core High High High Off Off

Intel ® ICH7 Family Datasheet 83

Page 84

Intel® ICH7 Pin States

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 4 of 5)

Immediately

PLTRST#1 /

RSMRST#

after

S1 S3

COLD

S4/S5

Signal Name

Power

Plane

During

PLTRST#1 /

RSMRST#

STPCLK# Core High High Low Off Off

SMBus Interface

SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined

System Management Interface

SMLINK[1:0] Suspend High-Z High-Z Defined Defined Defined

LINKALERT# Suspend High-Z High-Z Defined Defined Defined

Miscellaneous Signals

High-Z with

SPKR Core

Internal Pull-

Low Defined Off Off

down

AC ’97 Interface

ACZ_RST# Suspend Low Low Low Low Low

ACZ_SDOUT Core Low Running Low Off Off

ACZ_SYNC Core Low Running Low Off Off

Intel®High Definition Audio Interface

ACZ_RST# Suspend Low Low

Running Low Low

High-Z with

ACZ_SDOUT Core

Internal Pull-

Running Low Off Off

down

High-Z with

ACZ_SYNC Core

Internal Pull-

Running Low Off Off

down

High-Z with

ACZ_BIT_CLK Core

Internal Pull-

Low9 Low Off Off

down

Unmultiplexed GPIO Signals

GPIO[7:6, 0] Core Input Input Driven Off Off

GPIO[15:12,10:8] Suspend Input Input Driven Driven Driven

GPIO16 Core Low Low Defined Off Off GPIO18 Core High See Note 10 Defined Off Off GPIO20 Core High High Defined Off Off GPIO24 Suspend No Change No Change Defined Defined Defined GPIO25 Suspend High High

Defined Defined Defined GPIO[28:26] Suspend Low Low Defined Defined Defined GPIO[33:32] Core High High Defined Off Off

GPIO34 Core Low Low Defined Off Off

84 Intel ® ICH7 Family Datasheet

Page 85

Intel® ICH7 Pin States

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 5 of 5)

Immediately

PLTRST#1 /

RSMRST#

after

S1 S3

COLD

S4/S5

Signal Name

Power

Plane

During

PLTRST#1 /

RSMRST#

GPIO[39:38] Core Input Input Driven Off Off

SPI Interface

SPI_CS# Suspend High High High High High

SPI_MOSI Suspend High High High High High

SPI_CLK Suspend Low Low Low Low Low

Intel® Quick Resume Technology Interface (ICH7DH Only)

EL_RSVD / GPIO26 Suspend Low Low Defined Defined Defined

EL_STATE[1:0] /

GPIO[28:27]

Suspend Low Low Defined Defined Defined

NOTES:

1. The states of Vcc3_3 signals are taken at the times During PLTRST# and Immediately after PLTRST#.

2. The states of VccSus3_3 signals are taken at the times During RSMRST# and Immediately after RSMRST#.

3. In S3 and interfaces may be powered when the ICH7 is in the S3

, signal states are platform implementation specific, as some external components

HOT

state.

4. On the ICH7, PETp/n[4:1] are high until port is enabled by software. On the ICH7R and ICH7DH, PETp/n[6:1] are high until port is enabled by software.

5. SLP_S5# signals will be high in the S4 state.

6. ICH7 drives these signals High after the processor Reset.

7. CPUPWRGD represents a logical AND of the ICH7’s VRMPWRGD and PWROK signals, and thus will be driven low by the ICH7 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z.

8. ICH7 drives these signals Low before PWROK rising and Low after the processor Reset.

9. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running.

10. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset

11. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the deassertion of the RSMRST# pin.

Intel ® ICH7 Family Datasheet 85

Page 86

Intel® ICH7 Pin States

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 1 of 4)

Immediately

PLTRST#1 /

RSMRST#

after

C3/C4 S1 S3

COLD

S4/

Signal Name

Power

Plane

During

PLTRST#1 /

RSMRST#

PCI Express* (Mobile Only)

PETp[6:1],

PETn[6:1]

Core High High

Defined Defined Off Off

DMI

DMI[3:0]TXP, DMI[3:0]TXN

Core High High

Defined Defined Off Off

PCI Bus

AD[31:0] Core Low Undefined Defined Defined Off Off

C/BE[3:0]# Core Low Undefined Defined Defined Off Off

CLKRUN# Core Low Low Defined Off Off DEVSEL# Core High-Z High-Z High-Z High-Z Off Off

FRAME# Core High-Z High-Z High-Z High-Z Off Off

GNT[3:0]# GNT4# / GPIO48 GNT5# / GPIO17

Core

High with

Internal Pull-

ups

High High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z High-Z Off Off

PAR Core Low Undefined Defined Defined Off Off

PCIRST# Suspend Low High High High Low Low

PERR# Core High-Z High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z High-Z Off Off

LPC Interface

LAD[3:0] /

FWH[3:0]

LFRAME# /

FWH[4]

Core High High High High Off Off

LAN Connect and EEPROM Interface (Mobile Only)

EE_CS LAN Low Running Defined Defined Note 5 Note 5

EE_DOUT LAN High High Defined Defined Note 5 Note 5

EE_SHCLK LAN High-Z Running Defined Defined Note 5 Note 5 LAN_RSTSYNC LAN High Low Defined Defined Note 5 Note 5 LAN_TXD[2:0] LAN Low Low Defined Defined Note 5 Note 5

IDE Interface

DA[2:0] Core Undefined Undefined

UndefinedUndefine

Off Off

DCS1#, DCS3# Core High High High High Off Off

DD[15:8],

DD[6:0]

Core High-Z High-Z Defined High-Z Off Off

86 Intel ® ICH7 Family Datasheet

Page 87

Intel® ICH7 Pin States

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 2 of 4)

Immediately

PLTRST#1 /

RSMRST#

after

C3/C4 S1 S3

COLD

Signal Name

Power

Plane

During

PLTRST#1 /

RSMRST#

DD[7] Core Low Low Defined Low Off Off

DDACK# Core High High High High Off Off

DIOR#, DIOW# Core High High High High Off Off

SATA Interface (Mobile Only)

SATA[0]TXP, SATA[0]TXN

SATA[2]TXP,

Core High-Z High-Z Defined Defined Off Off

SATA[2]TXN

SATALED# Core High-Z High-Z Defined Defined Off Off

SATARBIAS Core High-Z High-Z Defined Defined Off Off

SATA2GP / GPIO36 SATA0GP / GPIO21

SATACLKREQ# /

GPIO35

Core Input Input Driven Driven Driven

Core Low Low Defined Defined Off Off

Interrupts

PIRQ[A:D]#,

PIRQ[H:E]# /

Core High-Z High-Z Defined High-Z Off Off

GPIO[5:2]

SERIRQ Core High-Z High-Z Running High-Z Off Off

USB Interface

USBP[7:0][P,N] Suspend Low Low Low Low Low Low

USBRBIAS Suspend High-Z High-Z Defined Defined Defined

OC[7:5]# /

GPIO[31:29]

Suspend Input Input Driven Driven Driven Driven

Power Management

PLTRST# Suspend Low High High High Low Low SLP_S3# Suspend Low High High High Low Low SLP_S4# Suspend Low High High High High Low SLP_S5# Suspend Low High High High High Low

STP_PCI# Core High High Defined High Low Low

STP_CPU# Core High High Low High Low Low

SUS_STAT# Suspend Low High High High Low Low

DPRSLPVR Core Low Low

DPRSTP# Core High High

Low/

High

Low/

High

High Off Off

SUSCLK Suspend Low Running

S4/

Define

Intel ® ICH7 Family Datasheet 87

Page 88

Intel® ICH7 Pin States

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 3 of 4)

Immediately

PLTRST#1 /

RSMRST#

after

C3/C4 S1 S3

COLD

S4/

Signal Name

Power

Plane

During

PLTRST#1 /

RSMRST#

Processor Interface

Dependant

A20M# Core

on A20GATE

See Note 8 Defined High Off Off

Signal

CPUPWRGD /

GPIO49

Core See Note 9 High High High Off Off

IGNNE# Core High See Note 8 High High Off Off

INIT# Core High High High High Off Off

INIT3_3V# Core High High High High Off Off

INTR Core See Note 10 See Note 10 Defined Low Off Off

NMI Core See Note 10 See Note 10 Defined Low Off Off

SMI# Core High High Defined High Off Off

STPCLK# Core High High Low Low Off Off

DPSLP# Core High High High/Low High Off Off

SMBus Interface

SMBCLK,

SMBDATA

Suspend High-Z High-Z Defined Defined Defined

Define

System Management Interface

SMLINK[1:0] Suspend High-Z High-Z Defined Defined Defined

LINKALERT# Suspend High-Z High-Z Defined Defined Defined

Define

Miscellaneous Signals

High-Z with

SPKR Core

Internal Pull-

Low Defined Defined Off Off

down

AC ’97 Interface (Mobile Only)

Cold

ACZ_RST# Suspend Low Low High

Reset Bit

Low Low

(High)

ACZ_SDOUT Core Low Running Running Low Off Off

ACZ_SYNC Core Low Running Running Low Off Off

Intel® High Definition Audio Interface

ACZ_RST# Suspend Low Low

High TBD Low Low

High-Z with

ACZ_SDOUT Core

Internal Pull-

Running Running Low Off Off

down

High-Z with

ACZ_SYNC Core

Internal Pull-

Running Running Low Off Off

down

88 Intel ® ICH7 Family Datasheet

Page 89

Intel® ICH7 Pin States

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 4 of 4)

Immediately

PLTRST#1 /

RSMRST#

after

Low

C3/C4 S1 S3

COLD

Running Low Off Off

S4/

Signal Name

Power

Plane

ACZ_BIT_CLK Core

During

PLTRST#1 /

RSMRST#

High-Z with

Internal Pull-

down

AZ_DOCK_RST# /

GPIO34

AZ_DOCK_EN# /

GPIO33

Core Low Low

Core High High Defined Defined Off Off

Defined Defined Off Off

Unmultiplexed GPIO Signals

GPIO[7:6] Core Input Input Driven Driven Off Off

GPIO[15:12,10:8] Suspend Input Input Driven Driven Driven Driven

GPIO18 Core High See Note 12 Driven Driven Off Off GPIO19 Core Input Input Driven Driven Off Off

GPIO24 Suspend No Change No Change Defined Defined Defined

GPIO25 Suspend High High

Defined Defined Defined

GPIO[28:26] Suspend Low Low Defined Defined Defined

Define

GPIO[39:37] Core Input Input Driven Driven Off Off

SPI Interface (Mobile Only)

SPI_CS# Suspend High High High High High High

SPI_MOSI Suspend High High High High High High

SPI_ARB Suspend Low Low Low Low Low Low

SPI_CLK Suspend Low Low Low Low Low Low

NOTES:

1. The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after PLTRST#.

2. The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately after RSMRST#.

3. In S3 and interfaces may be powered when the Intel®ICH7 is in the S3

4. PETp/n[6:1] high until port is enabled by software.

, signal states are platform implementation specific, as some external components

HOT

state.

5. LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3–S5 states depending upon whether or not the LAN power planes are active.

6. SLP_S5# signals will be high in the S4 state.

7. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled or low if it is disabled.

8. ICH7 drives these signals High after the processor Reset.

9. CPUPWRGD is an output that represents a logical AND of the Intel®ICH7’s VRMPWRGD and PWROK signals, and thus will be driven low by ICH7 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High.

10. IICH7 drives these signals Low before PWROK rising and Low after the processor Reset.

Intel ® ICH7 Family Datasheet 89

Page 90

11. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running.

12. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset

13. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the deassertion of the RSMRST# pin.

3.4 Power Planes for Input Signals

Table 3-5 and Table 3-6 show the power plane associated with each input signal, as

well as what device drives the signal at various times. Valid states include: High

Low Static: Will be high or low, but will not change Driven: Will be high or low, and is allowed to change Running: For input clocks

ICH7 suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion.

ICH7 core well signal states are indeterminate and undefined and may glitch prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK assertion.

Intel® ICH7 Pin States

Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 1 of 3)

Signal Name Power Well Driver During Reset S1 S3

A20GATE Core

ACZ_BIT_CLK (AC ‘97 Mode)

ACZ_SDIN[2:0] (AC ‘97

Mode)

ACZ_SDIN[2:0] (Intel®

High Definition Audio

Mode) CLK14 Core Clock Generator Running Low Low CLK48 Core Clock Generator Running Low Low

DDREQ Core IDE Device Static Low Low

DMI_CLKP, DMI_CLKN Core Clock Generator Running Low Low

EE_DIN Suspend EEPROM Component Driven Driven Driven

FERR# Core Processor Static Low Low

PERp[4:1], PERn[4:1] PERp[6:5], PERn[6:5]

(Intel® ICH7R and

ICH7DH Only)

DMI[3:0]RXP, DMI[3:0]RXN

IDEIRQ Core IDE Static Low Low

INTRUDER# RTC External Switch Driven Driven Driven

Core AC ’97 Codec Low Low Low

Suspend AC ’97 Codec Low Low Low

Suspend

Core PCI Express* Device Driven Driven Driven

Core (G)MCH Driven Low Low

External

Microcontroller

Intel® High Definition

Audio Codec

Static Low Low

Low Low Low

COLD

S4/S5

90 Intel ® ICH7 Family Datasheet

Page 91

Intel® ICH7 Pin States

Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 2 of 3)

Signal Name Power Well Driver During Reset S1 S3

INTVRMEN RTC

External Pull-up or

Pull-down

Driven Driven Driven

IORDY Core IDE Device Static Low Low

LAN_CLK Suspend

LAN Connect

Component

Driven Driven Driven

LAN_RST# Suspend External RC Circuit High High High

LAN_RXD[2:0] Suspend

LAN Connect

Component

Driven Driven Driven

LDRQ0# Core LPC Devices High Low Low

LDRQ1# / GPIO23

Core LPC Devices High Low Low

MCH_SYNC# Core (G)MCH Driven Low Low

OC[7:0]# Suspend External Pull-ups Driven Driven Driven

PCICLK Core Clock Generator Running Low Low

PME# Suspend Internal Pull-up Driven Driven Driven

PWRBTN# Suspend Internal Pull-up Driven Driven Driven

PWROK RTC System Power Supply Driven Low Low

RCIN# Core

REQ[3:0]#, REQ4# / GPIO22 REQ5# / GPIO12

2 2

Core PCI Master Driven Low Low

External

Microcontroller

High Low Low

RI# Suspend Serial Port Buffer Driven Driven Driven

RSMRST# RTC External RC Circuit High High High

RTCRST# RTC External RC Circuit High High High

SATA_CLKP, SATA_CLKN Core Clock Generator Running Low Low

SATA[3:0]RXP, SATA[3:0]RXN

Core SATA Drive Driven Driven Driven

SATARBIAS# Core External Pull-down Driven Driven Driven

SATA[3:0]GP /

GPIO[31:29,26]

Core

External Device or

External Pull-up/Pull-

down

Driven Driven Driven

SERR# Core PCI Bus Peripherals High Low Low

SMBALERT# / GPIO11

Suspend External Pull-up Driven Driven Driven

SYS_RESET# Suspend External Circuit Driven Driven Driven

THRM# Core Thermal Sensor Driven Low Low

THRMTRIP# Core Thermal Sensor Driven Low Low

TP0 Suspend External Pull-up High High High TP3 Suspend Internal Pull-up High High High

USBRBIAS# Suspend External Pull-down Driven Driven Driven VRMPWRGD Core

Processor Voltage

Regulator

High Low Low

COLD

S4/S5

Intel ® ICH7 Family Datasheet 91

Page 92

Intel® ICH7 Pin States

Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 3 of 3)

Signal Name Power Well Driver During Reset S1 S3

WAKE# Suspend External Pull-up Driven Driven Driven

SPI_MISO Suspend External Pull-up Driven Driven Driven

SPI_ARB Suspend Internal Pull-down Low Low Low

NOTES:

1. In S3 and interfaces may be powered when the ICH7 is in the S3

2. These signals can be configured as outputs in GPIO mode.

, signal states are platform implementation specific, as some external components

HOT

state.

COLD

S4/S5

Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations

(Sheet 1 of 3)

Signal Name

A20GATE Core

Power

Well

Driver During Reset C3/C4 S1 S3

External

Microcontroller

Static Static Low Low

ACZ_BIT_CLK

(AC ‘97 mode)

Core AC ’97 Codec Driven Low Low Low

(Mobile Only)

ACZ_SDIN[2:0]

(AC ‘97 mode)

Suspend AC ’97 Codec Driven Low Low Low

(Mobile Only)

ACZ_SDIN[2:0] (Intel® High Definition Audio

Suspend

Intel® High Definition

Audio Codec

Driven Low Low Low

Mode)

BM_BUSY# /

GPIO0

Core

Graphics Component

[(G)MCH]

Driven High Low Low

BATLOW# Suspend Power Supply High High High High

CLK14 Core Clock Generator Running Running Low Low CLK48 Core Clock Generator Running Running Low Low

DDREQ Core IDE Device Driven Static Low Low

DMI_CLKP

DMI_CLKN

EE_DIN

(Mobile Only)

Core Clock Generator Running Running Low Low

LAN EEPROM Component Driven Driven Note 2 Note 2

FERR# Core Processor Static Static Low Low

PERp[6:1],

PERn[6:1]

Core PCI Express* Device Driven Driven Driven Driven

(Mobile Only)

DMI[3:0]RXP, DMI[3:0]RXN

Core (G)MCH Driven Driven Low Low

IDEIRQ Core IDE Driven Static Low Low

INTRUDER# RTC External Switch Driven Driven Driven Driven

INTVRMEN

(Mobile Only)

RTC

External Pull-up or Pull-

down

Driven Driven Driven Driven

COLD

S4/S5

92 Intel ® ICH7 Family Datasheet

Page 93

Intel® ICH7 Pin States

Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations

(Sheet 2 of 3)

Signal Name

Power

Well

Driver During Reset C3/C4 S1 S3

COLD

IORDY Core IDE Device Static Static Low Low

LAN_CLK

(Mobile Only)

LAN_RST#

(Mobile Only)

LAN_RXD[2:0]

(Mobile Only)

LAN

Suspend Power Supply High High Static Static

LAN

LAN Connect

Component

LAN Connect

Component

Driven Driven Note 2 Note 2

LDRQ0# Core LPC Devices Driven High Low Low

LDRQ1# /

GPIO23

Core LPC Devices Driven High Low Low

MCH_SYNC# Core (G)MCH Driven Driven Low Low

OC[7:0]# Suspend External Pull-ups Driven Driven Driven Driven

PCICLK Core Clock Generator Running Running Low Low

PME# Suspend Internal Pull-up Driven Driven Driven Driven

PWRBTN# Suspend Internal Pull-up Driven Driven Driven Driven

PWROK RTC System Power Supply Driven Driven Low Low

RCIN# Core

External

Microcontroller

High High Low Low

REQ[3:0]#,

REQ4# / GPIO22

REQ5# / GPIO1

Core PCI Master Driven Driven Low Low

RI# Suspend Serial Port Buffer Driven Driven Driven Driven

RSMRST# RTC External RC Circuit High High High High

RTCRST# RTC External RC Circuit High High High High

SATA_CLKP, SATA_CLKN

Core Clock Generator Running Running Low Low

(Mobile Only)

SATA[0]RXP,

SATA[0]RXN

SATA[2]RXP,

Core SATA Drive Driven Driven Driven Driven

SATA[2]RXN

(Mobile Only)

SATARBIAS#

(Mobile Only)

SATA[2,0]GP

(Mobile Only)

Core External Pull-Down Driven Driven Driven Driven

External Device or

Core

External Pull-up/Pull-

Driven Driven Driven Driven

down

SERR# Core PCI Bus Peripherals Driven High Low Low

SMBALERT# /

GPIO11

Suspend External Pull-up Driven Driven Driven Driven

SYS_RESET# Suspend External Circuit Driven Driven Driven Driven

THRM# Core Thermal Sensor Driven Driven Low Low

S4/S5

Intel ® ICH7 Family Datasheet 93

Page 94

Intel® ICH7 Pin States

Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations

(Sheet 3 of 3)

Signal Name

Power

Well

Driver During Reset C3/C4 S1 S3

COLD

S4/S5

THRMTRIP# Core Thermal Sensor Driven Driven Low Low

TP3 Suspend Internal Pull-up High High High High

USBRBIAS# Suspend External Pull-down Driven Driven Driven Driven

VRMPWRGD Core

Processor Voltage

Regulator

Driven Driven Low Low

WAKE# Suspend External Pull-up Driven Driven Driven Driven

SPI_MISO

(Mobile Only)

SPI_ARB

(Mobile Only)

Suspend External Pull-up Driven Driven Driven Driven

Suspend Internal Pull-down Low Low Low Low

NOTES:

1. In S3 and interfaces may be powered when the Intel®ICH7 is in the S3

2. LAN Connect and EEPROM signals will either be “Driven” or “Low” in S3–S5 states

, signal states are platform implementation specific, as some external components

HOT

state.

depending upon whether or not the LAN power planes are active.

3. These signals can be configured as outputs in GPIO mode.

94 Intel ® ICH7 Family Datasheet

Page 95

Intel® ICH7 and System Clock Domains

4 Intel® ICH7 and System Clock

Domains

Table 4-1 shows the system clock domains. Figure 4-1 and Figure 4-2 show the

assumed connection of the various system components, including the clock generator in desktop and mobile/ultra mobile systems. For complete details of the system clocking solution, refer to the system’s clock generator component specification.

Table 4-1. Intel® ICH7 and System Clock Domains

Clock Domain Frequency Source Usage

Intel® ICH7

SATA_CLKP, SATA_CLKN

(Desktop and

Mobile only)

ICH7 DMI_CLKP, DMI_CLKN

ICH7

PCICLK

System PCI 33 MHz

ICH7

CLK48

ICH7

CLK14

ICH7

ACZ_BIT_CLK

(Desktop and

Mobile only)

LAN_CLK

(Desktop and

Mobile only)

SPI_CLK

(Desktop and

Mobile Only)

100 MHz

33 MHz

48.000 MHz

14.31818 MHz

12.288 MHz AC ’97 Codec

5 to 50 MHz

17.86 MHz ICH

Main Clock

Generator

Main Clock

Generator

Main Clock

Generator

Main Clock

Generator

Main Clock

Generator

Main Clock

Generator

LAN Connect

Component

Differential clock pair used for SATA.

Differential clock pair used for DMI.

Free-running PCI Clock to ICH7. This clock remains on during S0 and S1 (in desktop) state, and is expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile/ultra mobile configurations.

PCI Bus, LPC I/F. These only go to external PCI and LPC devices. Will stop based on CLKRUN# (and STP_PCI#) in mobile/ultra mobile configurations.

Super I/O, USB controllers. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile/ultra mobile configurations.

Used for ACPI timer and Multimedia Timers. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile/ ultra mobile configurations.

AC-link. Generated by AC ’97 Codec. Can be shut by codec in D3. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. NOTE: For use only in AC ‘97 mode.

Generated by the LAN Connect component. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations.

Intel ® ICH7 Family Datasheet 95

Page 96

Figure 4-1. Desktop Only Conceptual System Clock Diagram

Intel® ICH7 and System Clock Domains

33 MHz

14.31818 MHz

48.000 MHz

Intel

ICH7

100 MHz Diff. Pair

SATA 100 MHz Diff. Pair DMI 100 MHz Diff. Pair

50 MHz

12.288 MHz 24 MHz

32 kHz

XTAL

SUSCLK# (32 kHz)

Figure 4-2. Mobile Only Conceptual Clock Diagram

33 MHz

14.31818 MHz

48.000 MHz

STP_CPU#

STP_PCI#

Intel

ICH7-M

SATA 100 MHz Diff. Pair DMI 100 MHz Diff. Pair

50 MHz

12.288 MHz

32 kHz

XTAL

24 MHz

Clock

Gen.

1 to 6

Differential

Clock Fan

Out Dev ice

LAN Connect

AC ’97 Codec(s)

High Definition Audio Codec(s)

Clock

Gen.

100 MHz Diff. Pair

1 to 6

Differential

Clock Fan

Out Device

LAN Connect

AC ’97 Codec(s)

High Definition Audio Codec(s)

PCI

Clocks

(33 MHz)

14.31818 MHz

48.000 MHz

PCI Express

100 MHz

Diff. Pairs

PCI Clocks

(33 MHz)

14.31818 MHz 48 MHz

PCI Express

100 MHz

Diff. Pairs

SUSCLK# (32 kHz)

96 Intel ® ICH7 Family Datasheet

Page 97

Intel® ICH7 and System Clock Domains

Figure 4-3. Ultra Mobile Only Conceptual Clock Diagram

Intel

ICH7-U

32 kHz

XTAL

33 MHz

14.31818 MHz

48.000 MHz STP_CPU#

STP_PCI#

Clock

Generator

PCI Clocks

(33 MHz)

14.31818 MHz

48 MHz

DMI 100 MHz Diff Pair

24 MHz

High Definition Audio Codec(s)

SUSCLK# (32 kHz)

Intel ® ICH7 Family Datasheet 97

Page 98

Intel® ICH7 and System Clock Domains

98 Intel ® ICH7 Family Datasheet

Page 99

Functional Description

5 Functional Description

This chapter describes the functions and interfaces of the ICH7 family.

5.1 PCI-to-PCI Bridge (D30:F0)

The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH7 implements the buffering and control logic between PCI and Direct Media Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the DMI. All register contents are lost when core well power is removed.

Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub 7 (ICH7). This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally.

To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (i.e., the ICH7 and (G)MCH).

Configuration registers for DMI, virtual channel support, and DMI active state power management (ASPM) are in the RCRB space in the Chipset Config Registers (Section 7).

5.1.1 PCI Bus Interface

The ICH7 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz. The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH7 requests.

5.1.2 PCI Bridge As an Initiator

The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the following cycle types:

Table 5-1. PCI Bridge Initiator Cycle Types

Command C/BE# Notes

I/O Read/Write 2h/3h Non-posted Memory Read/Write 6h/7h Writes are posted Configuration Read/Write Ah/Bh Non-posted Special Cycles 1h Posted

5.1.2.1 Memory Reads and Writes

The bridge bursts memory writes on PCI that are received as a single packet from DMI.

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5.1.2.2 I/O Reads and Writes

The bridge generates single DW I/O read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle.

5.1.2.3 Configuration Reads and Writes

The bridge generates single DW configuration read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle.

5.1.2.4 Locked Cycles

The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI bridge implements bus lock, which means the arbiter will not grant to any agent except DMI while locked.

If a locked read results in a target or master abort, the lock is not established (as per the PCI Local Bus Specification). Agents north of the ICH7 must not forward a subsequent locked read to the bridge if they see the first one finish with a failed completion.

Functional Description

5.1.2.5 Target / Master Aborts

When a cycle initiated by the bridge is master/target aborted, the bridge will not reattempt the same cycle. For multiple DW cycles, the bridge increments the address and attempts the next DW of the transaction. For all non-postable cycles, a target abort response packet is returned for each DW that was master or target aborted on PCI. The bridge drops posted writes that abort.

5.1.2.6 Secondary Master Latency Timer

The bridge implements a Master Latency Timer via the SLT register which, upon expiration, causes the de-assertion of FRAME# at the next legal clock edge when there is another active request to use the PCI bus.

5.1.2.7 Dual Address Cycle (DAC)

The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB.

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