8xC251TB, 8xC2 51TQ,
Hardware Description
Addendum to the 8xC251SA, 8xC251SB,
8xC251SP, 8xC251S Q, User’s Manual
Release Date: December 2003
Order Number: 273138-002
The 8xC251Tx may contain design defects or err ors known as errata which may cause
the product to deviate from published specifications. Such errata are not covered by
Intel's warranty. Current characterized errata are available on request.
Information in this document is provided in connection with Intel products. No license, express or implied, by
estopp el or otherwise, to an y intellectual property rights is granted by this document. Except as provid ed in Intel's
Term s and C onditi ons of S ale for s uch pr oducts , Intel assumes no liab ility whatsoev er, and Inte l discl aims an y
expres s or implied w arranty, relati ng to sale and/or use of Intel produ c ts including liability or warranties relating to
fitnes s for a particul ar purpose, me rchantabilit y, or inf ringement of any patent, copyright or other intellectua l
propert y ri ght. Inte l pro duc ts are no t in tend ed for us e in me dic al, lif e sav ing, or lif e sus tai ning appli cati ons. Inte l
may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel
sales office or your distributor t o obtain the latest specifications and before placing your product order.
Design ers mu st not r ely on the absenc e or cha racter istics of any fe atures o r instru ctio ns marke d "rese rved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The 8x C251Tx ma y contai n desi gn def ects o r error s kno wn as er rata w hich m ay cau se the produ ct to de viat e
from published specifications. Current characterized er rata are av ailable on request.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver CO 80217-9808
or call 1-800-548-4725.
Many documents are available for download from Intel’s website at http://www.intel.com.
Copyright © Intel Corporation 1997, 2003.
*Third party brands and names are the property of their respective owners.
8xC251Tx Hardware Description
REVISION HISTORY:
Date Revision Description
November 1997 001 Initial release of t his document
December 2003 002 Removed references to 8XC251TA, 8XC251TP
273138-002 December 2003 iii
8xC251Tx Hardware Description
iv December 2003 273138-002
8xC251Tx Hardware Description
8xC251TB, 8xC251TQ Hardware Description
Addendum to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ, User’s Manual
1.0 INTRODUCTION TO THE 8xC251Tx
1.1 Comparing the 8xC251Tx and 8xC251Sx..................................................................... 1
2.0 SIGNAL SUMMARY
3.0 THE SECOND SERIAL I/O PORT
3.1 Overview........................................................................................................................ 7
3.2 Special Function Register Definitions............................................................................ 9
3.2.1 SCON1 .................................................................................................................... 9
3.2.2 SBUF1 ................................................................................................................... 10
3.2.3 SADDR1 ................................................................................................................ 10
3.2.4 SADEN1 ................................................................................................................ 10
3.2.5 BGCON ... ..... ....... ....... ..... ........ ....... ....... ..... ....... ........ ....... ..... ....... ....... ..... ........ ...... 10
3.2.6 IE1 ......................................................................................................................... 11
3.2.7 IPH1 . ............ ............ ............ .......... ............ ............ .......... ............ ............ ............ .. 11
3.2.8 IPL1 ....................................................................................................................... 11
4.0 EXTENDED DATA FLOAT TIMING
4.1 Summary of the Extended Dat a Float Timing Changes .............................................. 12
FIGURES
Figure 1 8xC251Tx Block Diagram .....................................................................................1
TABLES
Table 1. 8xC251Tx Signal Summary................................................................................. 2
Table 2. 8xC251Tx Signal Descriptions......... .................................... ................................ 3
Table 3. Special Function Register (SFR) Map.................................................................. 6
Table 4. Second Serial I/O Port Signals ............................................................................ 7
Table 5. Second Serial I/O Port Special Function Registers.............................................. 8
Table 6. SCON1 Special Function Register Definitions ..................................................... 9
Table 7. BGCON S pe c ia l F unc tion Regis te r D e fin it i o ns ................. .. ... ......... ... .......... .. .... 10
Table 8. IE1 Spec ia l F unc tion Regist e r D ef in itions... .......... .. .......... .. ... ......... ... .......... .. .... 11
Table 9. IPH1 Spe c ia l F unc tion Regist e r D ef in it io n s ............ .. ... .......... .. .......... .. .......... .. .. 11
Table 10. IPL1 Spe c ia l Fun c tio n R eg i st er De f in itions. .......... .. .......... .. ... ......... ... .......... .. .... 11
Table 11. Interru p t P rio r it y of Se c o nd S er ia l I/O Port....... .. ... ......... ... ......... ... .......... .. ... ...... 11
Table 12. UCONFIG1 bit definitions for the 8xC251Tx...................................................... 12
Table 13. Summary of the EDF# and WSB#[1:0] Configuration Options........................... 13
273138-002 December 2003 v
8xC251 Tx Hardware Description
vi December 2003 273138-002
1.0 INTRODUCTION TO THE 8xC251Tx
8xC251Tx Hardware Description
This Har dware Des criptio n describ es the 8x C251TB, 8xC25 1TQ (referred to collec tively as the 8xC 251Tx)
embedded microcontroller, which is the newest member of the MCS
®
251 microcontroller family. The
8xC251Tx is pin and code compatible with the 8xC251Sx but is enhanced wi th the additio n of new features.
This document addresses the differences between the two members of the MCS 251 microcontroller family.
For a detailed description of the MCS
251 microcontroller core and standard peripherals shared by both the
8xC251Sx and 8xC251Tx, please refer to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded
Microcontroller User’s Manual (272795).
1.1 Comparing the 8xC251Tx and 8xC251Sx
The differences between the 8xC251Tx and the 8xC251Sx are briefly described here.
• The maximum operating frequency of the 8xC251Tx is 24 Mhz compared to 16 MHz for the 8xC251Sx.
• The 8xC251Tx has two serial I/O ports while the 8xC251Sx has one. The pins for the second serial I/O
port are multiplexed with other functional pin s .
• The 8xC251Tx has a new co nf iguration option (Ext e nd ed Data Fl oa t tim ing) to allow interfacing w ith
slower me mories. This feature is supp orted by a bit in the configuration byte, UCONFIG1. The corre
sponding bit in the 8xC251Sx has a different function.
• The 8xC251Tx is offered in with factory programmed ROM while the 8xC251Sx is also offered with
OTPROM/EPROM.
RESETP0 (A7-
Clock and
Reset Unit
XTAL2
Interrupt
Handler Unit
Peripherals
IB Bus
8
3 Timers
XTAL1
P2 (A15-8)
P3
PORT
0-3
16
16
BUS INTE RFACE UNIT
0/D7-0)
EPROM/
ROM
RAM
824
Memory Data
Memory Address
Data Bus
Data Address
-
PSEN
ALU
16
INSTR
Instruction
Sequencer
24
PC
CPU
SRC1, SRC2
Register
File
Program
Counter
DST
ALE VCC VSS
Data Memory Interface
Figure 1. 8xC251Tx Block Diagram
1
Peripheral Interface Unit
Serial I/O
WDT
PCA
2nd Serial
I/O
P1
8xC251 Tx Hardware Description
2.0 SIGNAL SUMMARY
T able 1. 8xC251Tx Sign al Summary
Address & Data Input/Output
Name PLCC DIP Name PLCC DIP
AD0/P0.0 43 39 P1.0/T2 2 1
AD1/P0.1 42 38 P1.1/T2EX 3 2
AD2/P0.2 41 37 P1.2/EC/RXD1 4 3
AD3/P0.3 40 36 P1.3/CEX0/TXD1 5 4
AD4/P0.4 39 35 P1.4/CEX1 6 5
AD5/P0.5 38 34 P1.5/CEX2 7 6
AD6/P0.6 37 33 P1.6/CEX3/WAIT# 8 7
AD7/P0.7 36 32 P1.7/CEX4/A17/WCLK 9 8
A8/P2.0 24 21 P3.0/RXD 11 10
A9/P2.1 25 22 P3.1/TXD 13 11
A10/P2.2 26 23 P3.4/T0 16 14
A11/P2.3 27 24 P3.51/T1 17 15
A12/P2.4 28 25
A13/P2.5 29 26 Power & Ground
A14/P2.6 30 27 Name PLCC DIP
A15P2.7 31 28 V
P3.7/RD#/A16 19 17 V
P1.7/CEX4/A17/WCLK 9 8 V
Processor Control V
CC
CC2
SS
V
SS1
SS2
Name PLCC DIP
P3.2/INT0# 14 12 Bus Control & Status
P3.3/INT1# 15 13 Name PLCC DIP
EA# 35 31 P3.6/WR# 18 16
RST 10 9 P3.7/RD#/A16 19 17
XTAL1 21 18 ALE 33 30
XTAL2 20 19 PSEN# 32 29
NOTE: Pins in this font indicate function s associated with the second serial I/O port.
44 40
12
22 20
1
23,24
2
8xC251Tx Hardware Description
T able 2. 8xC251Tx Sign al Des cr iptions (Sh e et 1 of 3)
Signal
Name
A17 O Addres s Li ne 17. Output to memory as the 18th external address bit
A16 O Address Line 16. See RD#. P3.7/RD#
A15:8* O Address Lines. Upper address lines for the external bus. P2.7:0
A7:0 I/O Address/Data Lines. Multiplexed lower address lines and data lines
ALE O Address Latch Enable. ALE signals the start of an external bus
CEX0
CEX1
CEX2
CEX3
CEX4
EA# I External Access. Direct program acces s es to on-chip or off-chip
ECI I PCA External Clock Input. External clock input to the 16 bit PCA
INT1:0# I External Interrup ts 0 and 1. These inputs set IE1:0 in the TCON
P0.7:0 I/O Port 0. This is an 8 bit, open drain, bidirectional I/O port. AD7:0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.7:0 I/O Port 2. This is an 8 bit, bidirectional I/O port with internal pullups. A15:8
* The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mode configuration. If configured in
page mode, Port 0 carries the lower address bits (A7:0) and Port 2 carries the upper address bits (A15:8)
and the data (D 7: 0)
Type Description
(A17) in extended bus applications, depending on the values of bits
RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4,
"Device Configuration," of t he 8xC251SA, 8xC251SB, 8xC251S P,
8xC251SQ Embedded Microcontroller User’s Manual (272795). See
also RD# and PSEN#.
for external bus.
cycle an d ind ic at e s tha t va lid add r es s inf o rm ati on is av ai labl e on li n es
A15:8 and A7:0. An external latch can use ALE to dem ultiplex the
address from the address/data bus.
I/O Programmable Counter Array (PCA) input/output pins. These are
input signals for the PCA capture mode and output signals for the
PCA com pare mode and P CA PWM mode.
code memory. For EA# = 0, all program memory accesses are off
chip. For EA# = 1, all program memory accesses are on-chip if the
address is within the range of the on-chip program memory; other
wise the access is off-chip. The value of EA# is latched at reset. For
devic es without on-chip program memory, EA# mu st be strapped to
ground.
timer.
register. If bits IT1:0 in the TCON register are set, units IE1:0 are set
by the falling edge on the INT1#/INT0#. If bits IT1:0 are clear, bits
IE1:0 are set by a low level on INTO1:0# .
I/O Port 1. This is an 8 bit, bidirectional I/O port with internal pullups. T2
P1.7/CEX4/
WCLK
P0/7:0
P1.3/TXD1
P1.4
P1.5
P1.6/WAIT#
P1.7/A17/
WCLK
-
P1.2/RXD1
P3.3:2
T2EX
ECI/RXD1
CEX0/TXD1
CEX1
CEX2
CEX3/WAIT#
CEX4/A17/
WCLK
Alternate
Function
3
8xC251 Tx Hardware Description
Table 2. 8xC251Tx Signal Descriptions (Sheet 2 of 3)
Signal
Name
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Type Description
I/O Port 3. This is an 8 bit, bidirectional I/O port with internal pullups RXD
Alternate
Function
TXD
INT0#
INT1#
T0
T1
WR#
RD#/A16
PSEN# O Program Store Enable. Read sign al ou tp ut to ex te r na l me mo r y.
Asserted for the address range specified by the configuration byte
UCONFIG0, bits RD1:0.
RD# O Read. Read signal outp ut to externa l mem ory. Asserted for the
address range specified by the configuration byte UCONFIG0, bits
RD1:0.
P3.7/A16
RST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator
period s whi le th e os cil lat or is ru nn in g res et s the de vi ce. The po r t pin s
are driven to their reset conditions when a voltage greater than VIH1
is applied, whether or not the oscillator is running. This signal has a
Schmitt trigger input. Connecting the RST pin to V
capacitor provides power-on reset. Asserting RST when the chip is in
idle mo de or powerdown mode returns the chip to normal operation.
RXD I/O Receive Seria l Data. RXD send an d r ecei ve s da t a in se r ial I /O mode
0 and receives data in serial I/O modes 1, 2 and 3.
RXD1 I/O Re ceive Serial Data 1. RXD send and receives data in serial I/O
mode 0 and receives data in serial I/O modes 1, 2 and 3 for the sec
ond serial I/O port.
T1:0 I Timer 1:0 External Clock Inputs. When Timer 1:0 op er a te s as a
through a
CC
P3.0
P1.2/ECI
-
P3.5:4
counter, a falling edge on the T1:0 pin increments the count.
T2 I/O Timer 2 Clock Input/Output. For Timer 2 capture mode, this signal
is the external clock input. For the clock-out mode, it is the timer 2
P1.0
clock input.
T2EX I Timer 2 External Input. In Timer 2 captur e mod e, a fal li ng edge ini-
tiates a capture of Timer 2 registers. In auto-reload mode, a falling
edge causes the Timer 2 registers to be reloaded. In the up-down
counter mode, this signal determi nes the count direction:
P1.1
• 1=up
• 0 = down.
TXD O Transmit Seria l D ata. TXD outputs the shift clock in serial I/O mode
TXD1 O T ransmit Serial Data 1. TXD ou tputs the shift clock in serial I/O
V
CC
* The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mode configuration. If configured in
page mode, Port 0 carries the lower address bits (A7:0) and Port 2 carries the upper address bits (A15:8)
0 and transmits serial data in serial I/O modes 1, 2 and 3.
mode 0 and t r ansm it s se ria l dat a i n seri al I /O mode s 1 , 2 a nd 3 f o r th e
second serial I/O port.
PWR Supply Voltage. Connect this pin to the +5 supply voltage.
P3.1
P1.3/CEX0
and the data (D 7: 0)
4
8xC251Tx Hardware Description
Table 2. 8xC251Tx Signal Descriptions (Sheet 3 of 3)
Signal
Name
V
CC2
V
SS
V
SS1
V
SS2
WAIT# I Real-t im e W ai t S t a t e Inp u t. T he real - tim e WAIT# input is en abl e d by
Type Description
PWR Secondary Supply Voltage 2. This supply voltage connection is pro-
vided to reduce po w er supp ly noi se . Con ne cti on of this sp in to th e
+5V supply voltage is recommended. However, when using the ZX3
as a pin for pin replacement for the 8XC51FX, V
nected without loss of compatibility (Not available on DIP).
can be uncon-
CC2
GND Circuit Ground. Connect this pin to ground.
GND Secondary Ground. This ground is provided to reduce ground
bounce and improve power supply bypassing. C onnection of this pin
to ground is recommended. However, when usi ng the ZX3 as a pi n
for pin r epl ac em ent fo r the 8XC5 1F X, V
out loss of compatibility . (Not available in DIP).
can be unconnected with-
SS1
GND Secondary Ground 2. This ground i s provided to re duce ground
bounce and improve power supply bypassing. C onnection of this pin
to ground is recommended. However, when usi ng the ZX3 as a pi n
for pin r epl ac em ent fo r the 8XC5 1F X, V
out loss of compatibility . (Not available in DIP).
can be unconnected with-
SS1
writing a logical "1" to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal ‘system ready’ to the
microprocessor in real time by controlling the WAIT# input sign al
WCLK O Wait Clock Output. The real-time Wait Clock output is driven by writ-
ing a logical "1" to the WCON.1 (RTWCE) bit at S :A7H. When
enabled, the WCLK output produces a square wave signal with a
period of one-half the oscillator frequency
WR# O Write. Write signal output to external memory. Asserted for the mem-
XTAL1 I Input to On-chip, Inverting Oscillator Amplifier. To use the internal
ory address range specified by configuration byte UCONFIG0, bits
RD1:0.
oscil lator, a crystal/resonator circuit is connected to this pin. If an
extern al os ci ll ato r is us ed, it s o utpu t is co nnect e d t o th i s p in . XTAL1 is
Alternate
Function
P1.6/CEX3
P1.7/CEX4/
A17
P3.6
the clock source for the internal timing
XTAL2 O Output of the On-chip, Inverting Oscillator Amplifier. To use the
inter nal osci ll a tor, a cryst al /r eso nat or cir cu it i s co nn ec ted t o this pi n. If
an external oscillator is used, leave XTAL2 unconnected.
* The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mode configuration. If configured in
page mode, Port 0 carries the lower address bits (A7:0) and Port 2 carries the upper address bits (A15:8)
and the data (D 7: 0)
5
8xC251 Tx Hardware Description
Table 3. Special Function Register (SFR) Map
F8
F0 B
00000000
E8 CL
E0 ACC
00000000
D8 CCON
00x00000
D0 PSW
00000000
C8 T2CON
00000000
C0
B8 IPL0
x0000000
B0 P3
11111111
A8 IE0
00000000
A0 P2
11111111
98 SCON
00000000
90 P1
11111111
88 TCON000
00000
80 P0
11111111
NOTE: Regist ers in thi s f o nt are spec ia l fun ct i ons reg is ter s t hat a re as so ci at ed with t he se cond s er i al I/ O
port.
CH00000
000
00000000
CMOD
00xxx000
PSW1
00000000
T2MOD
xxxxxx00
SADEN
00000000
IE1
xxxxxxx0
SADDR
00000000
SBUF
xxxxxxxx
TMOD
00000000
SP
00000111
CCAP0Hx
xxxxxxx
CCAP0L
xxxxxxxx
CCAPM0
x0000000
RCAP2L
00000000
SADEN1
00000000
IP1L
xxxxxxx0
SADDR1
00000000
SCON1
00000000
TL0
00000000
DPL
00000000
CCAP1Hx
CCAP1L
xxxxxxxx
CCAPM1
x0000000
RCAP2H
00000000
IP1H
xxxxxxx0
SBUF1
xxxxxxxx
TL1
00000000
DPH
00000000
xxxxxxx
CCAP2Hx
xxxxxxx
CCAP2L
xxxxxxxx
CCAPM2
x0000000
TL2
00000000
TH0
00000000
DPXL
00000001
CCAP3Hx
xxxxxxx
CCAP3L
xxxxxxxx
CCAPM3
x0000000
TH2
00000000
TH1
00000000
CCAP4Hx
xxxxxxx
CCAP4L
xxxxxxxx
CCAPM4
x0000000
SPH
00000000
WDTRST
xxxxxxxx
IPH0
x0000000
WCON
xxxxxxxx
BGCON
0000xxxx
PCON
00xx0000
6
8xC251Tx Hardware Description
3.0 THE SECOND SERIAL I/O PORT
The second serial I/O port is functionally the same as the standard serial I/O port shared by both the
8xC251Tx and the 8xC251Sx. This section provides information about the new special function registers
(SFRs) associated with the second serial port. Detailed operation and programming of the serial I/O ports can
be obtained from Chapter 10 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcon
troller User’s Manual (272795). All the SFRs an d control bits for the standa rd serial I/O port in bo th the
8xC251Sx and 8xC2 51Tx ha ve an eq uivalen t in th e second se rial I/O port. Th is sho uld be kept in min d w h en
referencing Chapter 10 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller
User’s Manual (272795).
3.1 Overview
The s econd serial I/O port provides synchronous and asynchronous communications modes. It operates as a
univers al asynchron ous receiver and transm itter (UART) in three full-duple x modes (mod es 1, 2 and 3).
Asynchronous transmission and reception can occur simultaneously and at different baud rates. The second
UART provides framing-bit error detection, multiprocessor communications and automatic address recog
nition. The second serial port also operates in a single synchronous mode (mode 0).
The sync h r on ou s m od e ( m o de 0 ) op er a te s at a single bau d r a te. Mode 2 op er a tes at two baud r ate s. Modes
1 and 3 operate over a wide range of frequencies, w hich are generated by Timer 1 and Timer 2.
The second serial I/O port signals are defined in Table 4 and the special function registers are described in
Table 5.
For the three asynchronous modes, the second serial I/O port transmits on the TXD1 pin and receives on the
RXD1 pin. For th e synchronous mode (mode 0), the second serial I/O port outputs a clock signal on the TXD1
pin an d sends and receives messages on the RXD1 pin. The SBUF1 register holds received bytes and bytes
to be trans mitte d. To send, software wri tes a by te to SBUF 1; t o re c eiv e , softwa r e rea ds SBU F 1. Th e re ceiv e
shift register allows reception of a second byte before the first byte has been read from SBUF1. However, if
software has not read the first byte by the time the second byte is received, the second byte will overwrite the
first. The second serial I/O port sets interrupts bits TI1 and RI1 on transmission and reception, respectively.
These tw o share a single interrupt request and interrupt vector.
-
-
The serial port control 1 (SCON1) and the secondary serial port control (BGCON) registers configures and
cont rols the second s erial I/O port.
T able 4. Second S er i al I/ O P or t Si gn al s
Function
Name
TXD1 O T ran smi t Se r ial D at a. TXD1 outputs the shift clock in serial I/O mode
RXD1 I/O Receive Serial Data 1. RXD1 send and receives data in serial I/O
Type Description
0 and transmits serial data in serial I/O modes 1, 2 and 3 for the second serial I/O port
mode 0 and receives data in serial I/O modes 1, 2 and 3 for the second serial I/O port
7
Multiplexed
With
P1.3/CEX0
P1.2/ECI
8xC251 Tx Hardware Description
Table 5. Second Serial I/O Port Special Function Registers
Mnemonic Description Address
SBUF1 Serial Buffer 1. Two separate regi sters comprise the SBUF1 register. Writ-
ing to SB UF1 loads the transmit buffer; reading SBUF1 access the receive
buffer
SCON1 Serial Port Control 1. Selects the second serial I/O port operatin g mode.
SCON1 enables and disables the receiver, framing bit error detection, multi
process or com mun ic at ion, au to mati c add res s re co gn iti on an d th e ser ia l port
interrupt bits.
SADDR1 Serial Address 1. Defines the i ndividual address for a slave device AAH
SADEN1 Serial Address Enable 1. Specifies the mask byte that is used to define the
BGCON Secondary Serial Port Control. Contains controls to the second serial port
given address for a slave device
including the double baud rate bi t, read/wri te access to the SCON1.7 bit as
well as bits to control Timer1 or 2 overflow as the baud rate generator for
reception and transmission
IE1 Inter rupt Enable Register 1. Con tains the second serial I/O port interrupt
IPL0 Interrupt Priority Low Control Register 1. IPL0, together with IPH0,
IPH0 Interrupt Priority High Control Register 1. IPH0, together with IPL0,
enable bit
assigns the second serial I/O port interrupt level from 0 (lowest) to 3 (high-
est)
assigns the second serial I/O port interrupt level from 0 (lowest) to 3 (high-
est)
9BH
9AH
-
BAH
8FH
B1H
B2H
B3H
The second serial I/O port interrupt is enabled by setting the ES1 bit in the IE1 register. The priority of the
second serial I/O port’s interrupt is set to one of four levels by programming the IPL1.0 and IPH1.0 bits in the
IPL1 and IPH1 registers, respectively. The second serial I/O port is last in the interrupt poll ing sequence (se e
Chapter 6 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual
(272795) for details of the interrupt system). The second serial I/O port's Interrupt Service Routine Vector
Address is FF:0043H.
When the second serial I/O port is used, the alternate functions of RXD1 and TXD1 can no longer be used.
Specificall y, the PC A c an no longer be clocke d by an ex t e rna l c lo c k i np ut s i nc e ECI now fu nctions a s RXD1.
The PCA c an, howe ver, be cloc ked by on e of three other meth ods. Th ey consi st of two fi xed freq uencies
(fixed in relation to the Oscillator frequency); F
OSC
/12 an d F
/4 and Timer 0 overflow.
OSC
The other consequence of using the secon d serial I/ O port is Module 0 of the PCA can now be used only as a
16 bit Software Timer. The 16-bit Capture, High Speed Output and Pulse Width Modulation modes are no
long er available to Module 0 as these modes require the use of CEX0 (which, when the second serial I/O port
is in operation, functions as TXD1).
8
8xC251Tx Hardware Description
3.2 Special Function Register Definitions
The following describes the special function registers associated with the second serial I/O port and their bit
definitions.
3.2.1 SCON1
Address: 9AH
Reset Value: 0000 0000B
Table 6. SCON1 Special Function Register Definitions
Bit Number
7 FE1SM0 Framing Error Bit 1:
6 SM1 Second Serial I/O Port Mo de Bit 1:
5 SM2 Second Serial I/O Port Mo de Bit 2:
4 REN1 Receive Enable Bit 1:
3 TB8 Transmit Bit 8:
2 RB8 Receive Bit 8:
1 TI1 Second Ser ial I/O Port Transmit Interrupt Flag Bit:
0 RI1 Second Serial I/O Port Receive Interrupt Flag Bit:
Bit
Mnemonic
Function
To Select this function, set the SMOD0 bit in the BGCON register. Set by hardware to indicate an invalid stop bit. Cleared by software, not by valid frames
Second Serial I/O Port Mode Bit 0:
To select this function, clear the SMOD0 bit in the BGCON register. Software
writes to bit SM0 and SM1 to select the second serial I/O port operating
mode. Refer to SM1 bit for mode selections
Software write to bit SM0 and SM1 (above) to select the serial port operating
mode.
SM0 SM1 Mo de Description Baud Rate
0 0 0 Shift Register Fosc/12
0 1 1 8 bit UART variable
1 0 2 9 bit UART Fosc/32* or Fosc/64*
1 1 3 9 bit UART variable
* Select by programming the SMOD0 bit in the BGCON register
Software writes to SM2 enable and disable the multiprocess or communication and automatic address recog nition featu res. This allows the second
serial I/O port to differentiate between data and command frames and t o recognize slave and broadcast addresses
To enable reception, set this bit. To enable transmission, clear this bit
In modes 2 an d 3, so ft w are wr i tes the n in th data bit to be tra ns mit ted to TB8.
Not used in modes 0 and 1
Mode 0: not used
Mode 1 (SM2 clear): Set or cleared by hardware to reflect the stop bit
received
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth
data bit received
Set by transmitter after the last data bit is transmitted. Cleared by software
Set by the receiver after the last data bit of a frame has been received.
Cleare d by softw a re
9
8xC251 Tx Hardware Description
3.2.2 SBUF1
Address: 9BH
Reset Value: xx xx xxxxB
To send serial data, software writes a byte to SBUF1 and to receive serial data, software reads from SBUF1.
3.2.3 SADDR1
Address: AAH
Reset Value: 0000 0000B
Slave Individual Address Register1 (SADDR1) contains the device’s individual address for multiprocessor
communications.
3.2.4 SADEN1
Address: BAH
Reset Value: 0000 0000B
Mask Byte Register 1 (SADEN1) masks bits in the SADDR1 register to form the devices given address for
multiprocessor communications.
3.2.5 BGCON
Address: 8FH
Reset Value: 0000 xxxxB
Table 7. BGCON Special Function Register Definitions
Bit Number
7 SMOD1 Double Baud Rate Bit:
6 SMOD0 SCO N 1. 7 S el ec t :
5 RCLK1 Second Serial I/O Port Receive Clock Bit:
4 TCLK1 Second Se rial I/O Port Transmit Clock Bit:
3 - 0 - Reserved.
Bit Mne-
monic
Function
When set, doubles the baud rate for the second serial I/O port when timer 1
is used and mode 1, 2 or 3 is selected in the SCON1 register.
When set, read/write accesses to SCON1.7 are to the FE1 bit. When
cleared, read/write accesses to SC ON1.7 are to the S M0 bit.
Selects timer 2 over flow pulses (RCLK1 = 1) or timer 1 overflow pulses
(RCLK1 = 0) as the baud rate generator for the serial port modes 1 and 3.
Selects timer 2 overflow pulses (TCLK = 1) or ti mer 1 overflow pulses
(TCLK1 = 0) as the baud rate generator for the serial port modes 1 and 3.
10
3.2.6 IE1
Address: B1H
Reset Value: xx xx xxx0B
8xC251Tx Hardware Description
Table 8. IE1 Special Function Register Definitions
Bit Number
7 - 1 - Reserved
0 ES1 Second serial I/O port Interrupt Enable:
3.2.7 IPH1
Address: B3H
Reset Value: xx xx xxx0B
Bit Number
7 - 1 - Reserved
0 IPH1.0 Second serial I/O port Interrupt Priority High Bit
3.2.8 IPL1
Address: B2H
Reset Value: xx xx xxx0B
Bit Number
7 - 1 - Reserved
0 IPL1.0 Second serial I/O port Interrupt Priority Low Bit
Bit Mne-
monic
Setting this bit enables the second serial I/O port interrupt
T able 9. IPH1 Special Function Register Definitions
Bit Mne-
monic
Table 10. IPL1 Special Function Register Definitions
Bit Mne-
monic
Function
Function
Function
Interru pt prior ity of t he second serial I/O port can be program med to o ne of fou r level s depend ing on t he
IPH1.0 and IPL1.0 bits.
Table 11. Interrupt Priority of Second Serial I/O Port
IPH1.0 IPL1.0 Priority Level
0 0 0 (Lowest Priority)
0 1 1
1 0 2
1 1 3 (Highest Priority)
11
8xC251 Tx Hardware Description
4.0 EXTENDED DATA FLOAT TIMING
The Exte nded Data Float Timing feature seeks to provide a sol ution to use rs that may be using s lower
memory devices. Essentially, this feature extends the TRHDZ1 AC timing specification to accommodate
slower memory devices which require a longer period of dead time between a data and address bus cycles.
This feature is controlled by a bit in the Configuration byte (UCONFIG1). Bit 3 of UCONFIG1 in the 8xC251Tx
is def ined as EDF#. In the 8xC251S x , Bit 3 is defined as WSB. The implications of this change are discussed
below. Refer to Cha pter 4 of th e 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller
User’s Manual (272795) for details of the device configuration for the 8xC251Sx. The information in that
chapt er is valid for the 8xC251Tx with the exception of the change note d in this section.
4.1 Summary of t he E x t ended Data Float Timing Changes
EDF# is used to determine whether the Extended Data Float Timing is enabled. Table 12 shows the definition
of UCONFI G1 for the 8xC25 1Tx. Only bit 3 has been rede fined.
T able 12. UCONFIG1 bit definitions for the 8xC251Tx
Bit Number
7:5 - Reserved for Internal or Future Use.
4 INTR Interrupt Mode:
3 EDF# Extended Data Float Timings:
2:1 WSB1:0# Exter nal Wait State B (Region 01:):
0 EMAP EPROM Map:
Refer to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual
(272795) for the AC timings specif ications.
Bit
Mnemonic
Function
Set these bits when programming UCONFIG1
If this bit is set, i nterrupts push 4 bytes onto the stack ( the 3 bytes of th e PC
and PSW1). If this bit is clear, interrupts push the 2 lower bytes of the PC
onto the stack.
When cle are d, th e ext en ded data float timings are en ab le d. Wh en set,
8xC251Sx comp atible AC timings are enab led
WSB1# WSB2#
0 0 Inserts 3 wait states for region 01:
0 1 Inserts 2 wait states for region 01:
1 0 Inserts 1 wait state for region 01:
1 1 Zero wait states for region 01:
For devices with 16 Kbytes of on-chip code memory, clear this bit to map the
upper half of the on-chip code memory to region 00: (data memory). Maps
FF:2000H-FF:3FFFH to 00:E000H-00:FFFFH. If this bit is set, mapping does
not oc cur and the addresses in the range 00:E000H-0 0:FFFFH access
external RAM.
12
8xC251Tx Hardware Description
Tabl e 13 shows the effect of programming EDF# and WSB#[1:0] on the extended data float timing feature as
well as the inserti on of wait s tates for re gion 01: . It should b e noted t hat enabli ng the ext ended data float
timing allows region 01: to have 1 or 3 wait states inserted (depending on WSB#[1:0]) but not 0 or 2 wait
states.
T able 13. Summary of the EDF# and WSB#[1:0] Configuration Options
EDF# WSB#[1:0] Wait State
1 11 0 No
1 10 1 No
1 01 2 No
1 00 3 No
0 11 1 Yes
0 10 1 Yes
0 01 3 Yes
0 00 3 Yes
The external user configuration cycle (UCONF = 1 and EA# = 0) will be executed with the extended TRHDZ1
timing bu s cycle.
Extended D ata Floa t
Timings
13
Loading...