INTEL 8xC251TA, 8xC251TB, 8xC251TP, 8xC251TQ User Manual
8xC251TA, 8xC251TB,
8xC251TP, 8xC251TQ,
Hardware Description
Addendum to the 8xC251SA, 8xC251SB,
8xC251SP, 8xC251SQ, User’s Manual
Release Date: November, 1997
Order Number: 273138-001
The 8xC251Tx m ay contain desig n defects or er rors known as errata which may cause
the product to deviate from published specifications. Such errata are not covered by
Intel’s warranty. Current characterized errata are available on request.
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incompatibilities arising from future changes to them.
The 8x C251Tx may co ntain de sign de fect s or err ors kno wn as er rata wh ich ma y cause th e pro duct to d eviate
from published specifications. Current characterized errata are available on request.
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8xC251Tx Hardware Description
8xC251TA, 8xC251TB, 8xC251TP, 8xC251TQ, Hardware Description
Addendum to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ, User’s Manual
1.0 INTRODUCTION TO THE 8xC251Tx
1.1 Comparing the 8xC251Tx and 8xC251Sx........ ............ .. ............ ............ ....................... 1
2.0 SIGNAL SUMMARY
3.0 THE SECOND SERIAL I/O PORT
3.1 Overview........................................................................................................................ 7
3.2 Special Function Register Definitions............................................................................ 9
3.2.1 SCON1 .................................................................................................................... 9
3.2.2 SBUF1 ................................................................................................................... 10
3.2.3 SADDR1 ................................................................................................................ 10
3.2.4 SADEN1 ................................................................................................................ 10
3.2.5 BGCON .................................................................................................................. 10
3.2.6 IE1 ......................................................................................................................... 11
3.2.7 IPH1 ....................................................................................................................... 11
3.2.8 IPL1 ....................................................................................................................... 11
4.0 EXTENDED DATA FLOAT TIMING
4.1 Summary of the Extended Data Float Timing Changes .............................. ................ 12
FIGURES
Figure 1 8xC251Tx Block Diagram .....................................................................................1
TABLES
Table 1. 8xC251Tx Signal Summary . ................................................................................ 2
Table 2. 8xC251Tx Signal Descriptions............................................................................. 3
Table 3. Special Function Register (SFR) Map.................................................................. 6
Table 4. Second Serial I/O Port Signals ... .. .............. ......................... .............. .................. 7
Table 5. Second Serial I/O Port Special Function Registers.............................................. 8
Table 6. SCON1 Special Function Register Definitions..................................................... 9
Table 7. BGCON Special Function Register Definitions .................................................. 10
Table 8. IE1 Special Function Register Definitions.......................................................... 11
Table 9. IPH1 Special Function Register Definitions ....................................................... 11
Table 10. IPL1 Special Function Register Definitions........................................................ 11
Table 11. Interrupt Priority of Second Serial I/O Port......................................................... 11
Table 12. UCONFIG1 bit definitions for the 8xC251Tx......................................... .. ........... 12
Table 13. Summary of the EDF# and WSB#[1:0] Configuration Options........................... 13
III
1.0 INTRODUCTION TO THE 8xC251Tx
8xC251Tx Hardware Description
This Ha rdwa re D escr iptio n de scrib es t he 8 xC2 51TA, 8xC 251 TB, 8 xC2 51TP, 8xC 251 TQ (r efer red t o co llec tively as th e 8x C 25 1T x) em b ed ded microc on troller, wh ic h is the ne w e st m em be r of th e MC S
®
251 micro controller family. The 8xC251Tx is pin and code compatible with t he 8xC251Sx but is e nhanced with the addition
of new features.
This document addresses the differences between the two members of the MCS 251 microcontroller family.
For a d e t ai le d de sc r i pti on of the MCS 251 mic ro co ntrolle r c o r e an d s t an d ard peripherals shar ed b y b oth the
8xC251 Sx and 8xC 251Tx, pleas e refer to the
Microc ontroller User’s Manual
(272795).
8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded
1.1 Comparing the 8xC251Tx and 8xC251Sx
The di fferences between the 8xC251Tx and the 8xC251Sx are brief ly described here.
• The maximum operating frequency of the 8xC251Tx is 24 Mh z compared to 16 MHz for the 8xC251Sx.
• The 8xC251Tx has two serial I/O ports while the 8xC251Sx has one. The pins for the second serial I/O
port are multiplexed with other functional pins.
• The 8xC251Tx ha s a new configuration option (E xtended Data Float timing) to allow interfac ing with
slower memories. This feature is supported by a bit in the configuration byte, UCONFIG1. Th e corresponding bit in the 8xC251Sx has a different function.
• The 8xC251Tx is offered in with factory programmed ROM while the 8xC251Sx is also offered with
OTPROM/EPROM.
8
RESETP0 (A7-
Clock and
Reset Unit
XTAL2
Interrupt
Handler Unit
Peripherals
IB Bus
3 Timers
XTAL1
P2 (A15-8)
P3
PORT
0-3
16
16
BUS INTE RFACE UNIT
0/D7-0)
EPROM/
ROM
RAM
824
Memory Data
Memory Address
Data Bus
Data Address
PSEN
ALU
16
INSTR
Instruction
Sequencer
24
PC
CPU
SRC1, SRC2
Register
File
Program
Counter
DST
ALE VCC VSS
Data Memory Interface
Figure 1. 8xC251Tx Block Diagram
1
Peripheral Interface Unit
Serial I/O
WDT
PCA
2nd Serial
I/O
P1
8xC251Tx Hardware Description
2.0 SIGNAL SUMMARY
Table 1. 8xC251Tx Signal Summary
Address & Data Input/Output
Name PLCC DIP Name PLCC DIP
AD0/P0.0 43 39 P1.0/T2 2 1
AD1/P0.1 42 38 P1.1/T2EX 3 2
AD2/P0.2 41 37
AD3/P0.3 40 36
AD4/P0.4 39 35 P1.4/CEX1 6 5
AD5/P0.5 38 34 P1.5/CEX2 7 6
AD6/P0.6 37 33 P1.6/CEX3/WAIT# 8 7
AD7/P0.7 36 32 P1.7/CEX4/A17/WCLK 9 8
A8/P2.0 24 21 P3.0/RXD 11 10
A9/P2.1 25 22 P3.1/TXD 13 11
A10/P2.2 26 23 P3.4/T0 16 14
A11/P2.3 27 24 P3.51/T1 17 15
A12/P2.4 28 25
A13/P2.5 29 26 Power & Ground
A14/P2.6 30 27 Name PLCC DIP
A15P2.7 31 28 V
P3.7/RD#/A16 19 17 V
P1.7/CEX4/A17/WCLK 9 8 V
Processor Control V
Name PLCC DIP
P3.2/INT0# 14 12 Bus Control & Status
P3.3/INT1# 15 13 Name PLCC DIP
EA# 3531 P3.6/WR# 1816
RST 10 9 P3.7/RD#/A16 19 17
XTAL12118ALE 3330
XTAL2 20 19 PSEN# 32 29
NOTE: Pins in
this font
indicate functions associated with the second serial I/O port.
P1.2/EC/RXD1 4 3
P1.3/CEX0/TXD1 5 4
CC
CC2
SS
V
SS1
SS2
44 40
12
22 20
1
23,24
2
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