8XC251SA, 8XC251SB,
8XC251SP, 8XC251SQ
Embedded Microcontroller
Users Manual
8XC251SA, 8XC251SB,
8XC251SP, 8XC251SQ
Embedded Microcontroller
User’s Manual
May 1996 Order Number 272795-002
Information in this docu men t is pro vided in con nection with Intel products. Intel assumes no liability whatsoe ver, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of
Sale for such products.
Intel retains the right to make changes to these specifications at any time, with ou t not ice. M icroco ntroller products may have
minor variations to this specification known as errata.
*Other brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an orderin g number and ar e refere nced in this docum ent, or other Intel literat ure, may be
obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
COPYRIGHT © INTEL CORPORATION, 1996
CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1 MANUAL CONTENTS................................................................................................... 1-1
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY................................................ 1-3
1.3 RELATED DOCUMENTS.............................................................................................. 1-5
1.3.1 Data Sheet ................................................................................................................1-6
1.3.2 Application Notes ......................................................................................................1-6
1.4 APPLICATION SUPPORT SERVICES.......................................................................... 1-7
1.4.1 World Wide Web .......................................................................................................1-7
1.4.2 CompuServe Forums ................................................................................................1-7
1.4.3 FaxBack Service .......................................................................................................1-8
1.4.4 Bulletin Board System (BBS) ....................................................................................1-8
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1 8XC251SA, SB, SP, SQ ARCHITECTURE................................................................... 2-3
2.2 MCS 251 MICROCONTROLLER CORE....................................................................... 2-4
2.2.1 CPU ..........................................................................................................................2-5
2.2.2 Clock and Reset Unit ................................................................................................2-6
2.2.3 Interrupt Handler ........................................................................... ..... ...... ...... ...........2-7
2.2.4 On-chip Code Memory ..............................................................................................2-7
2.2.5 On-chip RAM ............................................................................................................2-7
2.3 ON-CHIP PERIPHERALS.............................................................................................. 2-7
2.3.1 Timer/Counters and Watchd og Timer .......................................................................2-7
2.3.2 Programmable Counter Array (PCA) ........................................................................2-8
2.3.3 Serial I/O Port ...........................................................................................................2-8
CHAPTER 3
ADDRESS SPACES
3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS................................... 3-1
3.1.1 Compatibility with the MCS® 51 Architecture ...........................................................3-2
3.2 8XC251SA, SB, SP, SQ MEMORY SPACE.................................................................. 3-5
3.2.1 On-chip General-purpose Data RAM ........................................................................3-8
3.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ) .............3-8
3.2.2.1 Accessing On-chip Code Memory in Region 00: ..................................................3-9
3.2.3 External Memory ......................................... ........................................................ ....3-10
3.3 8XC251SA, SB, SP, SQ REGISTER FILE.................................................................. 3-10
3.3.1 Byte, Word, and Dword Registers ...........................................................................3-13
3.3.2 Dedicated Registers ................................................................................................3-13
3.3.2.1 Accumulator and B Register ..............................................................................3-13
3.3.2.2 Extended Data Pointer, DPX ..............................................................................3-15
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8XC251SA, SB, SP, SQ USER’S MANUAL
3.3.2.3 Extended Stack Pointer, SPX ............................................................................3-15
3.4 SPECIAL FUNCTION REGISTERS (SFRS)............................................................... 3-16
CHAPTER 4
DEVICE CONFIGURATION
4.1 CONFIGURATION OVERVIEW .................................................................................... 4-1
4.2 DEVICE CONFIGURATION............................. ...... ....................................................... 4-1
4.3 THE CONFIGURATION BITS........................................................................................ 4-4
4.4 CONFIGURATION BYTE LOCATION SELECTOR (UCON)......................................... 4-5
4.5 CONFIGURING THE EXTERNAL MEMORY INTERFACE........................................... 4-8
4.5.1 Page Mode and Nonpage Mode (PAGE#) ................................................................4-8
4.5.2 Configuration Bits RD1:0 ..........................................................................................4-9
4.5.2.1 RD1:0 = 00 (18 External Address Bits) .................................... ..... .......................4-9
4.5.2.2 RD1:0 = 01 (17 External Address Bits) .................................... ..... .......................4-9
4.5.2.3 RD1:0 = 10 (16 External Address Bits) .................................... ..... .....................4-12
4.5.2.4 RD1:0 = 11 (Compatible with MCS 51 Microcontrollers) ..................... ...............4-12
4.5.3 Wait State Configuration Bits ..................................................................................4-12
4.5.3.1 Configuration Bits WSA1:0#, WSB1:# ...............................................................4-12
4.5.3.2 Configuration Bit WSB .......................................................................................4-12
4.5.3.3 Configuration Bit XALE# ....................................................................................4-13
4.6 OPCODE CONFIGURATIONS (SRC)......................................................................... 4-13
4.6.1 Selecting Binary Mode or Source Mode ..................................................................4-14
4.7 MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#)...................... 4-16
4.8 INTERRUPT MODE (INTR)......................................................................................... 4-16
CHAPTER 5
PROGRAMMING
5.1 SOURCE MODE OR BINARY MODE OPCODES........................................................ 5-1
5.2 PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE......................... 5-1
5.2.1 Data Types ................................................................................................................5-2
5.2.1.1 Order of Byte Storage for Words and Double Words ...........................................5-2
5.2.2 Register Notation ........................................ ...... ..... ...... .............................................5-2
5.2.3 Address Notation ......................................................................................................5-2
5.2.4 Addressing Mode s ................................. ........................................................ ...........5-4
5.3 DATA INSTRUCTIONS................................................................................................. 5-4
5.3.1 Data Addressing Modes ............................................................................................5-4
5.3.1.1 Register Addressing .............................................................................................5-5
5.3.1.2 Immediate ............................................................................................................5-5
5.3.1.3 Direct ....................................................................................................................5-5
5.3.1.4 Indirect .................................................................................................................5-6
5.3.1.5 Displacement .......................................................................................................5-8
5.3.2 Arithmetic Instructions ............................ ..... ...... ..... ...................................................5-8
5.3.3 Logical Instructions ...................................................................................................5-9
5.3.4 Data Transfer Instructions .......................................................................................5-10
iv
CONTENTS
5.4 BIT INSTRUCTIONS................................................................................................... 5-11
5.4.1 Bit Addressing .........................................................................................................5-11
5.5 CONTROL INSTRUCTIONS....................................................................................... 5-12
5.5.1 Addressing Modes for Control Instructions .............................................................5-13
5.5.2 Conditional Jumps .................................................................................................. 5-14
5.5.3 Unconditional Jumps ...............................................................................................5-15
5.5.4 Calls and Returns ...................................................................................................5-15
5.6 PROGRAM STATUS WORDS .................................................................................... 5-16
CHAPTER 6
INTERRUPT SYSTEM
6.1 OVERVIEW ................................................................................................................... 6-1
6.2 8XC251SA, SB, SP, SQ INTERRUPT SOURCES........................................................ 6-3
6.2.1 External Interrupts .....................................................................................................6-3
6.2.2 Timer Interrupts .........................................................................................................6-4
6.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT........................................ 6-5
6.4 SERIAL PORT INTERRUPT.......................................................................................... 6-5
6.5 INTERRUPT ENABLE................................................................................................... 6-5
6.6 INTERRUPT PRIORITIES............................................................................................. 6-7
6.7 INTERRUPT PROCESSING......................................................................................... 6-9
6.7.1 Minimum Fixed Interrupt Time ................................................................................6-10
6.7.2 Variable Interrupt Parameters .................................................................................6-10
6.7.2.1 Response Time Variables ..................................................................................6-10
6.7.2.2 Computation of Worst-case Latency With Variables ..........................................6-12
6.7.2.3 Latency Calculations ..........................................................................................6-13
6.7.2.4 Blocking Conditions ............................................................................................6-14
6.7.2.5 Interrupt Vector Cycle .................................. ..... ...... ...... .....................................6-14
6.7.3 ISRs in Process ......................................................................................................6-15
CHAPTER 7
INPUT/OUTPUT PORTS
7.1 INPUT/OUTPUT PORT OVERVIEW............................................................................. 7-1
7.2 I/O CONFIGURATIONS................... ...... ...... ............................................................. ..... 7-2
7.3 PORT 1 AND PORT 3................................................................................................... 7-2
7.4 PORT 0 AND PORT 2................................................................................................... 7-2
7.5 READ-MODIFY-WRITE INSTRUCTIONS..................................................................... 7-5
7.6 QUASI-BIDIRECTIONAL PORT OPERATION.............................................................. 7-6
7.7 PORT LOADING............................................................................................................ 7-7
7.8 EXTERNAL MEMORY ACCESS................................................................................... 7-7
CHAPTER 8
TIMER/COUNTERS AND WATCHDOG TIMER
8.1 TIMER/COUNTER OVERVIEW..................................................................................... 8-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
8.2 TIMER/COUNTER OPERATION................................................................................... 8-1
8.3 TIMER 0......................................................................................................................... 8-3
8.3.1 Mode 0 (13-bit Timer) ...............................................................................................8-4
8.3.2 Mode 1 (16-bit Timer) ...............................................................................................8-4
8.3.3 Mode 2 (8-bit Timer With Auto-reload) ......................................................................8-5
8.3.4 Mode 3 (Two 8-bit Timers) ........................................................................................8-5
8.4 TIMER 1......................................................................................................................... 8-5
8.4.1 Mode 0 (13-bit Timer) ...............................................................................................8-9
8.4.2 Mode 1 (16-bit Timer) ...............................................................................................8-9
8.4.3 Mode 2 (8-bit Timer with Auto-reload) .......................................................................8-9
8.4.4 Mode 3 (Halt) ............................................................................................................8-9
8.5 TIMER 0/1 APPLICATIONS........................................................................................... 8-9
8.5.1 Auto-load Setup Example .........................................................................................8-9
8.5.2 Pulse Width Measurements ....................................................................................8-10
8.6 TIMER 2....................................................................................................................... 8-10
8.6.1 Capture Mode .........................................................................................................8-11
8.6.2 Auto-reload Mode ...................................................................................................8-12
8.6.2.1 Up Counter Operation ........................................................................................8-12
8.6.2.2 Up/Down Counter Operation ..............................................................................8-13
8.6.3 Baud Rate Generator Mode ............................................... ..... ...... ..... .....................8-14
8.6.4 Clock-out Mode .......................................................................................................8-14
8.7 WATCHDOG TIMER................................................................................................... 8-16
8.7.1 Description ..............................................................................................................8-16
8.7.2 Using the WDT ........................................................................................................8-18
8.7.3 WDT During Idle Mode ...........................................................................................8-18
8.7.4 WDT During PowerDown ........................................................................................8-18
CHAPTER 9
PROGRAMMABLE COUNTER ARRAY
9.1 PCA DESCRIPTION...................................................................................................... 9-1
9.1.1 Alternate Port Usage .................................................................................................9-2
9.2 PCA TIMER/COUNTER................................................................................................. 9-2
9.3 PCA COMPARE/CAPTURE MODULES ....................................................................... 9-5
9.3.1 16-bit Capture Mode .................................................................................................9-5
9.3.2 Compare Modes .......................................................................................................9-7
9.3.3 16-bit Software Timer Mode ......................................................................................9-7
9.3.4 High-speed Output Mode ................................................... .......................................9-8
9.3.5 PCA Watchdog Timer Mode .....................................................................................9-9
9.3.6 Pulse Width Modulation Mode ................................................................................9-11
CHAPTER 10
SERIAL I/O PORT
10.1 OVERVIEW ................................................................................................................. 10-1
vi
CONTENTS
10.2 MODES OF OPERATION............................................................................................ 10-4
10.2.1 Synchronous Mode (Mode 0) ..................................................................................10-4
10.2.1.1 Transmission (Mode 0) ......................................................................................10-4
10.2.1.2 Reception (Mode 0) ............................................................................................10-5
10.2.2 Asynchronous Modes (Mode s 1, 2, and 3) .............................................................10-6
10.2.2.1 Transmission (Modes 1, 2, 3) .............................................................................10-6
10.2.2.2 Reception (Modes 1, 2, 3) ..................................................................................10-6
10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)...................................... 10-7
10.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3).................................... 10-7
10.5 AUTOMATIC ADDRESS RECOGNITION................................................................... 10-7
10.5.1 Given Address ........................................................................................................10-8
10.5.2 Broadcast Address ..................................................................................................10-9
10.5.3 Reset Addresses ...................................................................................................10-10
10.6 BAUD RATES............................................................................................................ 10-10
10.6.1 Baud Rate for Mode 0 ...................... ........................................................ ...... ..... ..10-10
10.6.2 Baud Rates for Mode 2 .........................................................................................10-10
10.6.3 Baud Rates for Modes 1 and 3 .............................................................................10-10
10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) ............................................10-11
10.6.3.2 Selecting Timer 1 as the Baud Rate Generator ...............................................10-11
10.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3) ............................................10-12
10.6.3.4 Selecting Timer 2 as the Baud Rate Generator ...............................................10-12
CHAPTER 11
MINIMUM HARDWARE SETUP
11.1 MINIMUM HARDWARE SETUP............ .............................................................. ..... ... 11-1
11.2 ELECTRICAL ENVIRONMENT......................................... .......................................... 11-2
11.2.1 Power and Ground Pins ..........................................................................................11-2
11.2.2 Unused Pins ............................................................................................................11-2
11.2.3 Noise Considerations ..............................................................................................11-2
11.3 CLOCK SOURCES...................................................................................................... 11-3
11.3.1 On-chip Oscillator (Crystal) .....................................................................................11-3
11.3.2 On-chip Oscillator (Ceramic Resonator) .................................................................11-4
11.3.3 External Clock .........................................................................................................11-4
11.4 RESET......................................................................................................................... 11-5
11.4.1 Externally Initiated Re sets .......................... ...... ..... .................................................11-6
11.4.2 WDT Initiated Resets ..............................................................................................11-6
11.4.3 Reset Operation ......................................................................................................11-6
11.4.4 Power-on Reset ......................................................................................................11-7
CHAPTER 12
SPECIAL OPERATING MODES
12.1 GENERAL.................................................................................................................... 12-1
12.2 POWER CONTROL REGISTER ....................................... ...... ..... ............................... 12-1
12.2.1 Serial I/O Control Bits .............................................................................................12-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
12.2.2 Power Off Flag ........................................................................................................12-1
12.3 IDLE MODE................................................................................................................. 12-4
12.3.1 Entering Idle Mode ....................................................... ...........................................12-4
12.3.2 Exiting Idle Mode ....................................................................................................12-5
12.4 POWERDOWN MODE................................................................................................ 12-5
12.4.1 Entering Powerdown Mode .....................................................................................12-6
12.4.2 Exiting Powerdown Mode .......................................................................................12-6
12.5 ON-CIRCUIT EMULATION (ONCE) MODE................................................................ 12-7
12.5.1 Entering ONCE Mode .................................................. ...... ..... ...... ..... .....................12-7
12.5.2 Exiting ONCE Mode ................................................................ ................................12-7
CHAPTER 13
EXTERNAL MEMORY INTERFACE
13.1 OVERVIEW ................................................................................................................. 13-1
13.2 EXTERNAL BUS CYCLES.......................................................................................... 13-3
13.2.1 Bus Cycle Definition s ..............................................................................................13-3
13.2.2 Nonpage Mode Bus Cycles ................................... ...... ...... .....................................13-4
13.2.3 Page Mode Bus Cycles ....................................................................................... ....13-5
13.3 WAIT STATES............................................................................................................. 13-8
13.4 EXTERNAL BUS CYCLES WITH CONFIGURABLE WAIT STATES.......................... 13-8
13.4.1 Extending RD#/WR#/PSEN# ..................................................................................13-8
13.4.2 Extending ALE ......................................................................................................13-10
13.5 EXTERNAL BUS CYCLES WITH REAL-TIME WAIT STATES................................. 13-10
13.5.1 Real-time WAIT# Enable (RTWE) .........................................................................13-12
13.5.2 Real-time WAIT CLOCK Enable (RTWCE) ...........................................................13-12
13.5.3 Real-time Wait State Bus Cycle Diagrams ............................................................13-12
13.6 CONFIGURATION BYTE BUS CYCLES................................................................... 13-15
13.7 PORT 0 AND PORT 2 STATUS................................................................................ 13-16
13.7.1 Port 0 and Port 2 Pin Status in Nonpage Mode ....................................................13-16
13.7.2 Port 0 and Port 2 Pin Status in Page Mode ..........................................................13-17
13.8 EXTERNAL MEMORY DESIGN EXAMPLES............................................................ 13-18
13.8.1 Example 1: RD1:0 = 00, 18-bit Bus, External Flash and RAM ..............................13-18
13.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAM ..............................13-20
13.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAM ..............................................13-22
13.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAM ..............................................13-24
13.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM .........................13-26
13.8.5.1 An Application Requiring Fast Access to the Stack .........................................13-26
13.8.5.2 An Application Requiring Fast Access to Data .................................................13-26
13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAM .........................13-29
13.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External Flash ..............................................13-30
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CONTENTS
CHAPTER 14
PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY
14.1 GENERAL.................................................................................................................... 14-1
14.1.1 Programming Considerations for On-chip Code Memory .......................................14-2
14.1.2 EPROM Devices .....................................................................................................14-3
14.2 PROGRAMMING AND VERIFYING MODES.............................................................. 14-3
14.3 GENERAL SETUP.................................................. ..... ................................................ 14-3
14.4 PROGRAMMING ALGORITHM................................................................................... 14-5
14.5 VERIFY ALGORITHM.................................................................................................. 14-6
14.6 PROGRAMMABLE FUNCTIONS................................................. ...... ..... ...... .............. 14-6
14.6.1 On-chip Code Memory ............................................................................................ 14-7
14.6.2 Configuration Bytes .................................................................................................14-7
14.6.3 Lock Bit System ......................................................................................................14-7
14.6.4 Encryption Array .................................... ........................................................ ..... ....14-8
14.6.5 Signature Bytes .......................................................................................................14-8
14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM)...................................................... 14-9
APPENDIX A
INSTRUCTION SET REFERENCE
A.1 NOTATION FOR INSTRUCTION OPERANDS............................................................ A-2
A.2 OPCODE MAP AND SUPPORTING TABLES............................................................. A-4
A.3 INSTRUCTION SET SUMMARY................................................................................ A-11
A.3.1 Execution Times for Instructions that Access the Port SFRs ............ .................... A-11
A.3.2 Instruction Summaries ..........................................................................................A-14
APPENDIX B
SIGNAL DESCRIPTIONS
APPENDIX C
REGISTERS
GLOSSARY
INDEX
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8XC251SA, SB, SP, SQ USER’S MANUAL
FIGURES
Figure Page
2-1 Functional Block Diagram of the 8XC251SA, SB, SP, SQ...........................................2-2
2-2 The CPU.......................................................................................................................2-5
2-3 Clocking Definitions......................................................................................................2-6
3-1 Address Spaces for MCS® 251 Microcontrollers.........................................................3-1
3-2 Address Spaces for the MCS® 51 Architecture ...........................................................3-3
3-3 Address Space Mappi ngs MCS ® 51 Arch itec tu re to MCS® 251 Arch ite cture.............3-4
3-4 8XC251SA, SB, SP, SQ Address Space .....................................................................3-6
3-5 Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space.................3-7
3-6 The Register File........................................................................................................3-11
3-7 Register File Locations 0–7........................................................................................3-12
3-8 Dedicated Registers in the Register File and their Corresponding SFRs...................3-14
4-1 Configuration Array (On-chip).......................................................................................4-2
4-2 Configuration Array (External)......................................................................................4-3
4-3 Configuration Byte UCONFIG0 ....................................................................................4-6
4-4 Configuration Byte UCONFIG1 ....................................................................................4-7
4-5 Internal/External Address Mapping (RD1:0 = 00 and 01)...........................................4-10
4-6 Internal/External Address Mapping (RD1:0 = 10 and 11)...........................................4-11
4-7 Binary Mode Opcode Map..........................................................................................4-15
4-8 Source Mode Opcode Map........................................................................................4-15
5-1 Word and Double-word Storage in Big Endien Form...................................................5-3
5-2 Program Status Word Register...................................................................................5-18
5-3 Program Status Word 1 Register................................................................................5-19
6-1 Interrupt Control System ...................................... ..... ...... .............................................6-2
6-2 Interrupt Enable Registe r.......................... ..... ...... ..... ...................................................6-6
6-3 Interrupt Priority High Register.....................................................................................6-8
6-4 Interrupt Priority Low Register.................................................... ..................................6-8
6-5 The Interrupt Process...................................................................................................6-9
6-6 Response Time Example #1......................................................................................6-11
6-7 Response Time Example #2......................................................................................6-12
7-1 Port 1 and Port 3 Structure...........................................................................................7-3
7-2 Port 0 Structure............................................................................................................7-3
7-3 Port 2 Structure............................................................................................................7-4
7-4 Internal Pullup Configurations ......................................................................................7-7
8-1 Basic Logic of the Timer/Counters ...............................................................................8-2
8-2 Timer 0/1 in Mode 0 and Mode 1 .................................................................................8-4
8-3 Timer 0/1 in Mode 2, Auto-Reload................................................................................8-5
8-4 Timer 0 in Mode 3, Two 8-bit Timers..................................... ..... ...... ..... ...... .................8-6
8-5 TMOD: Timer/Counter Mode Control Register.............................................................8-7
8-6 TCON: Timer/Counter Control Register.......................................................................8-8
8-7 Timer 2: Capture Mode ..............................................................................................8-11
8-8 Timer 2: Auto Reload Mode (DCEN = 0)....................................................................8-12
8-9 Timer 2: Auto Reload Mode (DCEN = 1)....................................................................8-13
8-10 Timer 2: Clock Out Mode............................................................................................8-15
8-11 T2MOD: Timer 2 Mode Control Register....................................................................8-16
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CONTENTS
FIGURES
Figure Page
8-12 T2CON: Timer 2 Control Register..............................................................................8-17
9-1 Programmable Counter Array.......................................................................................9-3
9-2 PCA 16-bit Capture Mode............................................................................................9-6
9-3 PCA Software Timer and High-speed Output Modes...................................................9-8
9-4 PCA Watchdog Timer Mode.......................................................................................9-10
9-5 PCA 8-bit PWM Mode................................................................................................9-11
9-6 PWM Variable Duty Cycle..........................................................................................9-12
9-7 CMOD: PCA Timer/Counter Mode Register...............................................................9-13
9-8 CCON: PCA Timer/Counter Control Register.............................................................9-14
9-9 CCAPMx: PCA Compare/Capture Module Mode Registers.......................................9-15
10-1 Serial Port Block Diagram..........................................................................................10-2
10-2 SCON: Serial Port Control Register...........................................................................10-3
10-3 Mode 0 Timing............................................................................................................10-5
10-4 Data Frame (Modes 1, 2, and 3)................................................................................10-6
10-5 Timer 2 in Baud Rate Generator Mode....................................................................10-13
11-1 Minimum Setup ..........................................................................................................11-1
11-2 CHMOS On-chip Oscillator.........................................................................................11-3
11-3 External Clock Connection.........................................................................................11-4
11-4 External Clock Drive Waveforms................................................................................11-5
11-5 Reset Timing Sequence.............................................................................................11-8
12-1 Power Control (PCON) Register.................................................................................12-2
12-2 Idle and Powerdown Clock Control............................................................................12-3
13-1 Bus Structure in Nonpage Mode and Page Mode......................................................13-1
13-2 External Code Fetch (Nonpage Mode).......................................................................13-4
13-3 External Data Read (Nonpage Mode)........................................................................13-4
13-4 External Data Write (Nonpage Mode) ........................................................................13-5
13-5 External Code Fetch (Page Mode).............................................................................13-6
13-6 External Data Read (Page Mode)..............................................................................13-7
13-7 External Data Write (Page Mode)...............................................................................13-7
13-8 External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) .......................13-9
13-9 External Data Write (Nonpage Mode, One WR# Wait State).....................................13-9
13-10 External Code Fetch (Nonpage Mode, One ALE Wait State)...................................13-10
13-11 Real-time Wait State Control Register (WCON).......................................................13-11
13-12 External Code Fetch/Data Read (Nonpage Mode, RT Wait State)..........................13-13
13-13 External Data Write (Nonpage Mode, R T Wait State)..............................................13-13
13-14 External Data Read (Page Mode, RT Wait State)....................................................13-14
13-15 External Data Write (Page Mode, RT Wait State)....................................................13-14
13-16 Configuration Byte Bus Cycles.................................................................................13-15
13-17 Bus Diagram for Example 1: 80C251SB in Page Mode...........................................13-18
13-18 Address Space for Example 1..................................................................................13-19
13-19 Bus Diagram for Example 2: 80C251SB in Page Mode...........................................13-20
13-20 Address Space for Example 2..................................................................................13-21
13-21 Bus Diagram for Example 3: 87C251SB/83C251SB in Nonpage Mode..................13-22
13-22 Address Space for Example 3..................................................................................13-23
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8XC251SA, SB, SP, SQ USER’S MANUAL
FIGURES
Figure Page
13-23 Bus Diagram for Example 4: 87C251SB/83C251SB in Nonpage Mode..................13-24
13-24 Address Space for Example 4..................................................................................13-25
13-25 Bus Diagram for Example 5: 80C251SB in Nonpage Mode.....................................13-27
13-26 Address Space for Examples 5 and 6......................................................................13-28
13-27 Bus Diagram for Example 6: 80C251SB in Page Mode...........................................13-29
13-28 Bus Diagram for Example 7: 80C251SB in Page Mode...........................................13-30
14-1 Setup for Programming and Verifying Nonvolatile Memory........ ...... ..........................14-5
14-2 Program/Verify Bus Cycles.........................................................................................14-6
B-1 8XC251SA, SB, SP, SQ 44-pin PLCC Package......................................................... B-1
B-2 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages ............................B-3
xii
CONTENTS
TABLES
Table Page
1-1 Intel Application Support Services................................................................................1-7
2-1 8XC251SA, SB, SP, SQ Features................................................................................2-3
3-1 Address Mapping s........................................................................................................3-4
3-2 Minimum Times to Fetch Two Bytes of Code...............................................................3-9
3-3 Register Bank Selectio n................ ........................................................ ...... ...... ..... ....3-12
3-4 Dedicated Registers in the Register File and their Corresponding SFRs...................3-15
3-5 8XC251SA, SB, SP, SQ SFR Map and Reset Values ...............................................3-17
3-6 Core SFRs..................................................................................................................3-18
3-7 I/O Port SFRs...................................... .............................................................. ..... ....3-18
3-8 Serial I/O SFRs ..........................................................................................................3-19
3-9 Timer/Counter and Watchdog Timer SFRs................................................................3-19
3-10 Programmable Counter Array (PCA) SFRs................................................................3-19
4-1 External Addresses for Configuration Array .................................................................4-4
4-2 Memory Signal Selections (RD1:0)..............................................................................4-8
4-3 RD#, WR#, PSEN# External Wait States...................................................................4-13
4-4 Examples of Opcodes in Binary and Source Modes..................................................4-14
5-1 Data Types...................................................................................................................5-2
5-2 Notation for Byte Registers, Word Registers, and Dword Registers............................5-3
5-3 Addressing Modes for Data Instructions in the MCS® 51 Architecture........................5-6
5-4 Addressing Modes for Data Instructions in the MCS® 251 Architecture......................5-7
5-5 Bit-addressable Locations..........................................................................................5-11
5-6 Addressing Two Sample Bits......................................................................................5-12
5-7 Addressing Modes for Bit Instructions........................................................................5-12
5-8 Addressing Modes for Control Instructions.................................................................5-13
5-9 Compare-condit ion al Jump Ins truc tions.................... .................................................5-14
5-10 The Effects of Instructions on the PSW and PSW1 Flags................................. ..... ....5-17
6-1 Interrupt System Pin Signals............... ...... ..... ...... ........................................................6-1
6-2 Interrupt System Special Function Regi ste rs................................... ..... ...... .................6-3
6-3 Interrupt Control Matrix........................................................................................... ......6-4
6-4 Level of Priority.............................................................................................................6-7
6-5 Interrupt Priority Within Level............................... ..... ...... ...... ..... ..................................6-7
6-6 Interrupt Latency Variable s................................................... ..... ...... ..... .....................6-13
6-7 Actual vs. Predicted Latency Calculations..................................................................6-13
7-1 Input/Output Port Pin Descriptions...............................................................................7-1
7-2 Instructions for External Data Moves............................................................................7-9
8-1 Timer/Counter and Watchdog Timer SFRs..................................................................8-2
8-2 External Signals...........................................................................................................8-3
8-3 Timer 2 Modes of Operation.......................................................................................8-15
9-1 PCA Special Function Registers (SFRs)......................................................................9-4
9-2 External Signals...........................................................................................................9-4
9-3 PCA Module Modes ...................................................................................................9-14
10-1 Serial Port Signals ......................................................................................................10-1
10-2 Serial Port Special Function Registers.......................................................................10-2
10-3 Summary of Baud Rates..........................................................................................10-10
xiii
8XC251SA, SB, SP, SQ USER’S MANUAL
TABLES
Table Page
10-4 Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3..................................10-12
10-5 Selecting the Baud Rate Generator(s).....................................................................10-13
10-6 Timer 2 Generated Baud Rates...............................................................................10-14
12-1 Pin Conditions in Various Modes............... ..... ........................................................ ....12-3
13-1 External Memory Interface Signals.............................................................................13-2
13-2 Bus Cycle Definitions (No Wait States)......................................................................13-3
13-3 Port 0 and Port 2 Pin Status In Normal Operating Mode..........................................13-16
14-1 Programming and Verifying Modes............................................................................14-4
14-2 Lock Bit Function ........................................................................................................14-8
14-3 Contents of the Signature Bytes.................................................................................14-9
A-1 Notation for Register Operands................. ..... ........................................................ .....A-2
A-2 Notation for Direct Addresses... ........................................................ ..... ...... ...... .......... A-3
A-3 Notation for Immediate Addressing.............................................................................A-3
A-4 Notation for Bit Addressing..........................................................................................A-3
A-5 Notation for Destination s in Contro l Instru ct ion s................................... ...... ...... .......... A-3
A-6 Instructions for MCS® 51 Microcontro lle rs..................................................................A-4
A-7 New Instructions for the MCS® 251 Architecture........................................................A-5
A-8 Data Instructions.........................................................................................................A-6
A-9 High Nibble, Byte 0 of Data Instructions......................................................................A-6
A-10 Bit Instructions............................................................................................................. A-7
A-11 Byte 1 (High Nibble) for Bit Instructions.......................................................................A-7
A-12 PUSH/POP Instructions .............................................................................................. A-8
A-13 Control Instructions ....................................................................................................A-8
A-14 Disp lacement /Ext end ed MOVs. ............................................................. ...... ...... .......... A-9
A-15 INC/DEC.................. ...... ..... ...... ..... ...... ...... ............................................................. ...A-10
A-16 Encoding for INC/DEC .............................................................................................. A-10
A-17 Shifts.........................................................................................................................A-10
A-18 St ate Times to Acces s the Port SFRs.................. ..... ...... ..........................................A-12
A-19 Summary of Add and Subtract Instructions...............................................................A-14
A-20 Summary of Compare Instructions............................................................................A-15
A-21 Summary of Increment and Decrement Instructions.................................................A-16
A-22 Summary of Multiply, Divide, and Decimal-adjust Instructions..................................A-16
A-23 Summary of Logical Instructions ...............................................................................A-17
A-24 Summary of Move Instructions..................................................................................A-19
A-25 Summary of Exchange, Push, and Pop Instructions................................................. A-22
A-26 Summary of Bit Instructions.......................................................................................A-23
A-27 Summary of Control Instructions ...............................................................................A-24
A-28 Flag Symbols.............................................................................................................A-26
B-1 PLCC/DIP Pin Assignments Li sted by Functional Category........................................B-2
B-2 Signal Descriptions......................................................................................................B-3
B-3 Memory Signal Selections (RD1:0).............................................................................B-7
C-1 8XC251SA, SB, SP, SQ SFR Map..............................................................................C-2
C-2 Core SFRs...................................................................................................................C-3
C-3 I/O Port SFRs................ ..... .............................................................. ..... ......................C-3
xiv
CONTENTS
TABLES
Table Page
C-4 Serial I/O SFRs ...........................................................................................................C-4
C-5 Timer/Counter and Watchdog Timer SFRs.................................................................C-4
C-6 Programmable Counter Array (PCA) SFRs.................................................................C-5
C-7 Register Fil e.................................. ...... ...... ..... ...... ..... ...... ............................................C-6
xv
Guide to This Manual
1
CHAPTER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC251SA, S B, SP, SQ† embedded microcontr oller , whic h is the first
member of the Intel MCS
software and hardware designers familiar with the principles of microcontrollers.
1.1 MANUAL CONTENTS
This manual contains 14 chapters and 3 appendices. This chapter, Chapter 1, provides an overview of the manual. This section summarizes the contents of the remaining chapters and appendices. The remainder of this chapter describes notational conventions and terminology used
throughout the manual and provides references to related documentation.
Chapter 2, “Architectural Overview” — provides an overview of device hardware. It covers
core functions (pipelined CPU, clock and reset unit, and o n-ch ip memory) and on-chip peripherals (timer/counters, watchdog timer, programmable counter array, and serial I/O port.)
Chapter 3, “Address Spaces” — describes the three address spaces of the MCS 251 microcontroller: memory address space, special function register (SFR) space, and the register file. It also
provides a map of the S F R space sh owing the lo catio n of the SF Rs an d th eir reset values and explains the mapping of the address spaces of the MCS
the MCS 251 architecture.
Chapter 4, “Device Configuration” — describes microcontroller f eatures that are con figured at
device reset, including the external memory interface (the number of external address bits, the
number of wait states, memory regions for asserting RD#, WR#, and PSEN#, pag e mode), binary/
source opcodes, interrupt mode, and the mapping of a portion of on-chip code memory to data
memory. It describes the configuration bytes and how to program them for the desired configuration. It also describes how internal memory space maps into external memory.
®
251 microcontroller family. This manual is intended for use by both
®
51 architecture into the address spaces of
Chapter 5, “Programming” — prov ides an overview of the instruction set. It describes each instruction type (control, arithmetic, logical, etc.) and lists the instructions in tabular form. This
chapter also discusses the addressing modes, bit instructions, and the program status words.
Appendix A provides a detailed description of each instructi on.
Chapter 6, “Interrupt System” — describes the 8XC251Sx interrupt circuitry which provides
a TRAP instruction interrupt and seven maskable interrupts: two external interrupts, three timer
interrupts, a PCA interrupt, and a serial port interrupt. This chapter also discusses the interrupt
priority scheme, interrupt enable, interrupt processing, and interrupt response time.
† The 8XC251SA, SB, SP, SQ products are also collectively referred to as 8XC251Sx.
1-1
8XC251SA, SB, SP, SQ USER’S MANUAL
Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discusses
their configuration for general-purpose I/O, external memory accesses (ports 0, 2), and alternative special functions.
Chapter 8, “Timer/Counters and WatchDog Timer” — describes the three on-chip timer/counters and discusses their application. This chapter also provides instructions for using the
hardware watchdog timer (WDT) and describes the operation of the WDT during the idle and
powerdown modes.
Chapter 9, “Programmable Counter Array” — describes the PCA o n-ch ip periph eral and explains how to configure it for general-purpose applicatio ns (timers and counters) and special applications (programmable WDT and pulse-width modulator).
Chapter 10, “Serial I/O Port” — describes the full-duplex serial I/O port and explains how to
program it to communicate with external peripherals. This chapter also discusses baud rate generation, framing error detection, multiprocessor communications, and automatic address recognition.
Chapter 11, “Minimum Hardware Setup” — describes the basic requirements for operating
the 8XC251Sx in a system. It also discusses on-chip and external clock sources and describes device resets, including power-on reset.
Chapter 12, “Special Operating Modes” — provides an overview of the idle, power down, an d
on-circuit emulation (ONCE) modes and describes how to enter and exit each mode. This chapter
also describes the power control (PCON) special function register and lists the status of the device
pins during the special modes and reset (Table 12-1).
Chapter 13, “External Memory Interface” —describes the external memory signals and bus
cycles and provides examples of external memory design. It provides waveform diagr ams for the
bus cycles, bus cycles with wait states, and the configuration byte bus cycles. It also provides bus
cycle diagrams with AC timing symbols and definitions of the symbols.
Chapter 14, “Programming and Verifying Nonvolatile Memory” — provides instructions for
programming and verifying on-chip cod e memory, configuration bytes, signature bytes, lock bits
and the encryption array.
Appendix A, “Instruction Set Reference” — provides reference in formation for the instruction
set. It describes each instruction; defines the bits in the program status word regis ters (PSW,
PSW1); shows the relationships between instructions and PSW flags; and l ists hexadecimal opcodes, instruction lengths, and execution times. Chapter 5, “Programming,” includes a general
discussion of the instruction set.
1-2
GUIDE TO THIS MANUAL
Appendix B, “Signal Descriptions” — describes the function(s) of each device pin. Descriptions are listed alphabetically by signal name. This appendix also provides a list of the signals
grouped by functional category.
Appendix C, “Registers” — accumulates, for convenient reference, copies of the register definition figures that appear throughout the manual.
A glossary has been included for your convenience.
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY
The following notations and terminology are used in this manual. The Glossary defines other
terms with special meanings.
# The pound symbol (#) has either of two meanings, depending on the
context. When used with a signal name, the symbol means that the
signal is active low . When u sed in an instru ction, th e sy mbol prefix es
an immediate value in immediate addressing mode.
italics Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible
meanings.
Variables in registers and signal names are commonly represented by
x and y, where x represents the first variable and y represents the
second variable. For example, in register Px.y, x represents the
variable [1–4] that identifies the specific port, and y represents the
register bit variable [7:0]. Variables must be replaced with the correct
values when configuring or programming registers or identifying
signals.
XXXX Uppercase X (no italics) represents an unknown value or a “don’t
care” state or condition. The value may be either binary or
hexadecimal, depending on the context. For example, 2XAFH (hex)
indicates that bits 11:8 are unknown; 10XX in binary context
indicates that the two LSBs are unknown.
Assert and Deassert The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active
polarity (high/low) is defined by the signal name. Active-low signals
are designated by a pound symbol (#) suf fix; active-high s ignals have
no suffix. To assert RD# is to drive it low; to assert ALE is to drive it
high; to deassert RD# is to drive it high; to deassert ALE is to drive i t
low .
1-3
8XC251SA, SB, SP, SQ USER’S MANUAL
Instructions Instruction mnemonics are shown in upper case to avoid confusion.
When writing code, either upper case or lower case may be used.
Logic 0 (Low) An input voltage level equal to or less than the maximum value of
or an output voltage level equal to or less than the maximum
V
IL
value of V
. See data sheet for values.
OL
Logic 1 (High) An input voltage level equal to or greater than the minimum value of
V
or an output voltage level equal to or greater than the minimum
IH
value of V
. See data sheet for values.
OH
Numbers Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are
represented by their customary notations. That is, 255 is a decimal
number and 1111 1111 is a binary number. In some cases, the letter B
is added for clarity.
Register Bits Bit locations are indexed by 7:0 for byte registers, 15:0 for word
registers, and 31:0 for double-word (dword) registers, where bit 0 is
the least-significant bit and 7, 15, or 31 is the most-significant bit. An
individual bit is represented by the register name, followed by a
period and the bit number. For example, PCON.4 is bit 4 of the
power control register. In some discussions, bit names are used. For
example, the name of PCON.4 is POF, the power-off flag.
Register Names Register names are shown in upper case. For example, PCON is the
power control register. If a register name contains a lowercase
character, it represents more than one register. For example,
CCAPMx represents the five registers: CCAPM0 through CCAPM4.
Reserved Bits Some registers contain reserved bits. These bits are not used in this
device, but they may be used in future implementations. Do not write
a “1” to a reserved bit. The value read from a reserved bit is indeterminate.
Set and Clear The terms set and clear refer to the value of a bit or the act of givi ng
it a value. If a bit is set, its value is “1;” setting a bit gives it a “1”
value. If a bit is clear, its value is “0;” clearing a bit gives it a “0”
value.
Signal Names Signal names are shown in upper case. When several signals share a
common name, an in dividual sig nal is repre sented by the sign al name
followed by a number. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P0.0, P0.1). A pound
symbol (#) appended to a signal name identifies an active- low s ignal.
1-4
GUIDE TO THIS MANUAL
Units of Measure The following abbrevi ations are used to represent units of measure:
A amps, amperes
DCV direct current volts
Kbyte kilobytes
KΩ kilo-ohms
mA milliamps, milliamperes
Mbyte megabytes
MHz megahertz
ms milliseconds
mW milliwatts
ns nanoseconds
pF picofarads
W watts
V volts
µA microamps, microamperes
µF microfarads
µs microseconds
µW microwatts
1.3 RELATED DOCUMENTS
The following documents contain additional information that is useful in designing systems that
incorporate the 8XC251Sx microcontroller. To order documents, please call Intel Literature Fulfillment (1-800-548-4725 in the U.S. and Canada; +44(0) 793-431155 in Europe).
Embedded Microcontrollers Order Number 270646
Embedded Processors Order Number 272396
Embedded Applications Order Number 270648
Packaging Order Number 240800
1-5
8XC251SA, SB, SP, SQ USER’S MANUAL
1.3.1 Data Sheet
The data sheet is included in Embedded Microcontrollers and is also available individually.
8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller Order Number 272783
(Commercial/Express)
1.3.2 Application Notes
The following application notes apply to the MCS 251 microcontroller.
AP-125, Designing Microcontroller Systems Order Number 210313
for Electrically Noisy Environments
AP-155, Oscillators for Microcontrollers Order Number 230659
AP-708, Introducing the MCS
®
251 Microcontroller Order Number 272670
—the 8XC251SB
AP-709, Maximizing Performance Using MCS
®
251 Microcontroller Order Number 272671
—Programming the 8XC251SB
AP-710, Migrating from the MCS
®
51 Microcontroller to the MCS 251 Order Number 272672
Microcontroller (8XC251SB)—Software and Hardware
Considerations
The following MCS 51 microcontroller applicati on notes also apply to the MCS 251 microcontroller.
®
AP70, Using the Intel MCS
51 Boolean Processing Capabilities Order Number 203830
AP-223, 8051 Based CRT Terminal Controller Order Number 270032
AP-252, Designing With the 80C51BH Order Number 270068
AP-425, Small DC Motor Control Order Number 270622
AP-410, Enhanced Serial Port on the 83C51FA Order Number 270490
AP-415, 83C51FA/FB PCA Cookbook Order Number 270609
AP-476, How to Implement I
®
Using Intel MCS
1-6
51 Microcontrollers
2
C Serial Communication Order Number 272319
GUIDE TO THIS MANUAL
1.4 APPLICATION SUPPORT SERVICES
You can get up-to-date technical information from a variety of electronic support systems: the
World Wide Web, CompuServe, the FaxBack* service, and Intel’s Brand Products and Applications Support bulletin board service (BBS). These systems are available 2 4 hours a day, 7 days a
week, providing technical information whenever you need it.
In the U.S. and Canada, technical support representatives are available to answer your questions
between 5 a.m. and 5 p.m. Pacific Standard T ime (PST). Out side the U.S. and Canada, please contact your local distributor. You can order product literature from Intel literature centers and sales
offices.
Table 1-1 lists the information you need to access these services.
Table 1-1. Intel Application Support Services
Service U.S. and Canada Asia-Pacific and Japan Europe
World Wide Web URL: http://www.intel.com/ URL: htt p:/ /w ww.intel.com/ URL: htt p:/ /w w w.intel.com/
CompuServe go intel go intel go intel
FaxBack* 800-525-3019 503-264-6835
916-356-3105
BBS 503-264-7999
916-356-3600
Help Desk 800-628-8686
916-356-7999
Literature 800-548-4725 708-296-9333
503-264-7999
916-356-3600
Please contact your local
distributor.
+81(0)120 47 88 32
+44(0)1793-496646
+44(0)1793-432955
Please contact your local
distributor.
+44(0)1793-431155 England
+44(0)1793-421777 France
+44(0)1793-421333 Germany
1.4.1 World Wide Web
We offer a variety of technical and product information through the World Wide Web (URL: http://www.intel.com/design/mcs96). Also visit Intel’s Web site for financials, history, and news.
1.4.2 CompuServe Forums
Intel maintains several C o mpuServe forums that provide a means for you to gather information,
share discoveries, and debate issues. Type “go intel” for access. The INTELC forum is set up to
support designers using variou s Intel components. For info rmation about Comp uServe access and
service fees, call CompuServe at 1-800-848-8199 (U.S.) or 614-529-1340 (outside the U.S.).
1-7
8XC251SA, SB, SP, SQ USER’S MANUAL
1.4.3 FaxBack Service
The FaxBack service is an on-demand publishing system that sends documents to your fax machine. You can get product announcements, ch ange notifications, pro duct literatu re, d evice ch aracteristics, design recommendations, and quality and reliability information from FaxBack 24
hours a day, 7 days a week.
Think of the FaxBack service as a library of technical documents that you can access with your
phone. Just dial the telephone number and respo nd to the system prompts. After y ou select a document, the system sends a copy to y our fax machine.
Each document is assigned an order number and is listed in a subject catalog. The first time you
use FaxBack, you should order the appropriate subject catalogs to get a complete listing of document order numbers. Catalogs are updated twice monthly. In addition, daily update catalogs list
the title, status, and order number of each document that has b een added, revised, or deleted during the past eight weeks. The daily update catalogs are numbered with the subject catalog number
followed by a zero. For example, for the complete mic rocontroller and flash catalog, request d ocument number 2; for the daily update to the microcontroller and flash catalog, request docu ment
number 20.
The following catalogs and information are available at the time of publication:
1. Solutions OEM subscription for m
2. Microcontroller and flash catalog
3. Development tools catalog
4. Systems catalog
5. Multimedia catalog
6. Multib us and iRMX
®
software catalog and BBS file listings
7. Microprocessor, PCI, and peripheral catalog
8. Quality and reliability and change notifica tion catalog
9. iAL (Intel Architecture Labs) technology catalog
1.4.4 Bulletin Board System (BBS)
Intel’ s Brand Products and Applications Support bulletin board system (BBS) lets you download
files to your PC. The BBS has the latest ApBUILDER software, hypertext manuals and
datasheets, software drivers, firmware upgrades, application notes and utilities, and quality and
reliability data.
1-8
GUIDE TO THIS MANUAL
Any customer with a PC and modem can access the BBS. The system provide s automatic conf iguration support for 1200- through 19200-baud modems. Use these modem settings: no parity, 8
data bits, and 1 stop bit (N, 8, 1).
T o access the BBS, just dial the telephone nu mber (see Table 1-1 on page 1-7) and r espond to the
system prompts. During your first session, the system asks you to register with the system operator by entering your name and location. The system o perator will set up your access account
within 24 hours. At that time, you can access the files on the BBS.
NOTE
In the U.S. and Canada, you can get a BBS user’s guide, a master list of BBS
files, and lists of FaxBack documents by calling 1-800-525-3019. Use these
modem settings: no parity, 8 data bits, and 1 stop bit (N, 8, 1).
1-9
Architectural
Overview
2
CHAPTER 2
ARCHITECTURAL OVERVIEW
The 8XC25 1S x is the first member of the MCS®251 microcontroller family. This family of 8-bit
microcontrollers is a high-performance upgrade of the widely-used MCS 51
It extends features and performance while maintaining binary-code compatibility and pin compatibility with the 8XC51FX, so the impact on existing hardware and software is minimal. Typical control applications for the 8XC251 Sx include copiers, scan ners, CD ROMs, and tape drives.
It is also well suited for communications applications, such as phone terminals, business/feature
phones, and phone switching and transmission systems.
This manual covers all memor y options of the 8XC251SA, SB, SP, SQ and these options are listed
in Table 2-1.
All MCS 251 microcontrollers share a set of common features:
®
microcontrollers.
• 24-bit linear addressing and up to 16 Mbytes of memory
• a register-based CPU with registers accessible as bytes, words, and double words
• a page mode for accelerating external instruction fetches
• an instruction pipeline
• an enriched instruction set, including 16-bit arithmetic and logic instructions
• a 64-Kbyte extended stack sp ace
• a minimum instruction-execution time of two clocks (vs. 12 clocks for MCS 51 microcon-
trollers)
• three types of wait state solutions: real-time, RD#/WR#/PSEN#, and ALE
• binary-code compatibility with MCS 51 microcontrollers
Several benefits are derived from these features:
• preservation of code written for MCS 51 microcontrollers
• a significant increase in core execution speed in comparison with MCS
at the same clock rate
• suppor t for lar g er programs and more data
• increased efficiency for code written in C
• dynamic bus control through real-time wait state operations
51 microcontrollers
2-1
8XC251SA, SB, SP, SQ USER’S MANUAL
System Bus and I/O Ports
P0.7:0
Port 0
Drivers
Code Bus (16)
SRC1 (8)
SRC2 (8)
ALU
P2.7:0
Port 2
Drivers
Memory Data (16)
Memory Address (16)
Bus Interface
Instruction Sequencer
Register
File
Code
OTPROM/ROM
8 Kbytes
or
16 Kbytes
Code Address (24)
Data
Memory
Interface
Data Address (24)
Data Bus (8)
Data RAM
512 Bytes
or
1024 Bytes
Peripheral
Interface
Interrupt
Handler
Clock
&
Reset
I/O Ports and
Peripheral Signals
P1.7:0
Port 1
Drivers
IB Bus (8)
P3.7:0
Port 3
Drivers
Watchdog
Timer
Timer/
Counters
PCA
Serial I/O
Peripherals
2-2
DST (16)
®
MCS
251 Microcontroller Core
Clock & Reset
8XC251SA/SB/SP/SQ Microcontroller
Figure 2-1. Functional Block Diagram of the 8XC251SA, SB, SP, SQ
A4214-01
ARCHITECTURAL OVERVIEW
2.1 8XC251SA, SB, SP, SQ ARCHITECTURE
Figure 2-1 is a functional block diagram of the 8XC251SA, S B, SP, SQ. The core, which is common to all MCS 251 microcontrollers, is described in section 2.2, “MCS 251 Microcontroller
Core.” Each microcontroller type in the f amily has its own on-chip periph erals, I/O ports, external
system bus, size of on-chip RAM, and type and size of on-chip program memory. Table 2-1 lists
the distinguishing features of the product.
The 8XC251Sx peripherals include a dedicated watchdog timer, a timer/counter unit, a programmable counter array (PCA), and a serial I/O u nit. The 8XC251 Sx has four 8-bit I /O ports, P0–P3.
Each port pin can be individually p rogrammed as a gener al I/O signal or as a special-fun ction signal that supports the external bus or one of the on-chip peripherals. Ports P0 and P2 comprise a
16-line external bus, which transmits a 16-bit address multiplexed with 8 data bits. (You can also
configure the 8XC251Sx to have a 17- bit or an 18-bit external ad dress bus. See section 4.5, “Co nfiguring the External Memory Interface.” Ports P1 and P3 carry bus-control and peripheral signals.
Table 2-1. 8XC251SA, SB, SP, SQ Features
On-chip Memory
Device
Number
80C251SB 0 0 1024
80C251SQ 0 0 512
83C251SA 0 8 1024
83C251SB 0 16 1024
83C251SP 0 8 512
83C251SQ 0 16 512
87C251SA 8 0 1024
87C251SB 16 0 1024
87C251SP 8 0 512
87C251SQ 16 0 512
Common features:
Address space 512 Kbytes
External Address bus 16-bit, 17-bit, or 18-bit
Register file 40 bytes
I/O lines 32
Interrupt sources 11
OTPROM/EPROM
(Kbytes)
ROM
(Kbytes)
RAM
(Bytes)
2-3
8XC251SA, SB, SP, SQ USER’S MANUAL
The 8XC251Sx has two power-saving modes. I n idle mode, the CPU clock is stopped, while
clocks to the peripherals continue to run. In powerdown mode, the on-chip oscillator is stopped,
and the chip enters a static state. An enabled interru pt or a hardware re set can b ring the ch ip back
to its normal operating mode from idle or powerdown. See Chapter 12, “Special Operating
Modes,” for details on the power-saving modes.
MCS 251 microcontrollers use an instruction set that has been expanded to include new operations, addressing modes, and operands. Many instructions can operate on 8-, 16-, or 32-bit operands, providing easier and more efficient programming in high-level languages such as C.
Additional new features include the TRAP instruction, a new displacement add ressing mode, and
several conditional jump instructions. Chapter 5, “Programming,” describes the instruction set
and compares it with the instruction set for MCS 51 microcontrollers.
You can configure the 8XC251Sx to run in binary mode or source mode. Either mode executes
all of the MCS 51 architecture instructions and all of the MCS 251 architecture instructions. However, source mode is more efficient for MCS 2 51 architecture instructions, and binary mode is
more efficient for MCS 51 architecture instructions. In binary mode, object code for an MCS 51
microcontroller runs on the 8XC251Sx without recompiling.
If a system was originally developed using an MCS 51 microcontroller, and if the new
8XC251Sx-based system will run code written for the MCS 51 microcontroller , performance will
be better with the 8XC251Sx running in binary mode. Object code written for the MCS 51 microcontroller runs faster on the 8XC 251Sx.
However, if mo st of the code is rewritten using the new instruc tion set, performance will be better
with the 8XC251Sx running in source mode. In this case the 8XC251Sx can r un significantly faster than the MCS 51 microcontroller. See Chapter 4, “Device Configuration,” for a discussion of
binary mode and source mode.
MCS 251 microcontrollers store both code and data in a single, linear 16-Mbyte memory space.
The 8XC251Sx can address up to 256 Kbytes of ex ternal memory. The special function registers
(SFRs) and the register file have separate address spaces. See Chapter 3, “Address Spaces,” for a
description.
2.2 MCS 251 MICROCONTROLLER CORE
The MCS 251 microcontroller core contains the C P U, the clock and r e set unit, the interr upt h andler, the bus interface, and the peripheral interface. The CPU contains the instruction sequencer,
ALU, register file, and data memory interface.
2-4
ARCHITECTURAL OVERVIEW
2.2.1 CPU
Figure 2-2 is a functional block diagram of the CPU (central processor unit). The 8XC251Sx
fetches instructions from on-chip code memory two bytes at a time, or from external memory in
single bytes. The instructions are sent over the 16-bit co de bus to the execution unit. You can configure the 8XC251Sx to operate in page mode for accelerated instruction fetches from external
memory. In page mode, if an instruction fet ch is to the same 256-byte “page” as the previous
fetch, the fetch requires one state (two clocks) rather than two states (four clocks).
The 8XC251Sx register file has forty registers, which can be accessed as bytes, word s, and double
words. As in the MCS 51 architecture, registers 0–7 consist of four banks of eight registers each,
where the active bank is selected by the program status word (PSW) for fast context switches.
The 8XC251Sx is a single-pipeline machine. When the pipeline is full and cod e is executing from
on-chip code memory, an instruction is completed every state time. When the pipeline is full and
code is executing from external memory (with no wait states and no extension of the ALE signal),
an instruction is completed every two state times.
Code Bus
SRC1
SRC2
ALU
DST
24
8
8
File
Code Address
16
Instruction Sequencer
Register
16
Figure 2-2. The CPU
Data
Memory
Interface
Interrupt
Handler
Data Bus
8
24
Data Address
2-5
8XC251SA, SB, SP, SQ USER’S MANUAL
2.2.2 Clock and Reset Unit
The timing source for the 8XC251Sx can be an external oscillator or an internal oscillator with
an external crystal/resonator (see Chapter 11, “Minimum Hardware Setup”). The basic unit of
time in MCS 251 microcontrollers i s the sta te time (or state), which is two o scillator period s (see
Figure 2-3). The state time is divided into phase 1 and phase 2.
The 8XC251Sx peripherals operate on a peripheral cycle, which is six state times. (This periph -
eral cycle is particular to the 8XC251Sx and not a characteristic of th e MCS 25 1 architecture.) A
one-clock interval in a peripheral cycle is denoted by its state and phase. For example, the PCA
timer is incremented once each peripheral cycle in phase 2 of state 5 (denoted as S5P2).
The reset unit places the 8XC251Sx into a known state. A chip reset is initiated by asserting the
RST pin or allowing the watchdog timer to time out (see Chapter 11, “Minimum Hardware Setup”).
Phase 1 Phase 2
P1
XTAL1
P2
2-6
XTAL1
State 1
P1
P2
T
OSC
2 T
= State Time
OSC
State 2
P1
P2
State 3
P2
P1
Peripheral Cycle
State 4
P1
P2
Figure 2-3. Clocking Definitions
State 5
P1
P2
State 6
P1
P2
A2604-02
ARCHITECTURAL OVERVIEW
2.2.3 Interrupt Handler
The interrupt handler can receive interru pt requests from eleven sources: seven maskable sour ces
and the TRAP instruction. When the interrupt handler grants an interrupt request, the CPU discontinues the normal flow of instructions and branches to a routine that services the source that
requested the interrupt. You can enable or disable the interrupts individually (except for TRAP)
and you can assign one of four priority levels to each interrupt. See Chapter 6, “Interr upt System,”
for a detailed description.
2.2.4 On-chip Code Memory
For 83C251SA (ROM) and 87C251SA (OTPROM/EPROM) devices, memory locations
FF:0000H–FF:1FFFH are implemented with 8-Kbytes of on-chip code memory. For 83C251SB
and 87C251SB devices, memory locations FF:0000H–FF:3FFFH are implemented with 16Kbytes of on-chip code memory.
Following a reset, the first instruction is fetched from location FF:0000H. For 80C251Sx (no
ROM/OTPROM/EPROM) devices, location FF:0000H is always in external memory.
2.2.5 On-chip RAM
The 8XC251SA and 8XC251SB have 1-Kbyte of on-chip data RAM at locations 20H–4 1FH. The
8XC251SP and 8XC251SQ have 512 bytes of on-chip data RAM at locations 20H–21FH. Th ese
RAM locations can be accessed with direct, indirect, and displacement addressing. Ninety-six of
these locations (20H–7FH) are bit address able. An additional 32 bytes of on-chip RAM (00H–
1FH) provide storage for the fo u r banks of registers R0–R7.
2.3 ON-CHIP PERIPHERALS
The on-chip peripherals, which lie outside the core, perform specialized functions. Software accesses the peripherals via their special function reg isters (SFRs). The 8XC251S x has four peripherals: the watchdog timer, the timer/counters, the programmable counter array (PCA), and the
serial I/O port.
2.3.1 Timer/Counters and Watchdog Timer
The timer/counter unit has three timer/cou nters, wh ich can be clocked by the oscillator ( for timer
operation) or by an external input (for counter operation). You can set up an 8-bit, 13-bit, or 16bit timer/counter, and you can program them for special applications, such as capturing the time
of an event on an external pin, outputting a programmable clock signal on an ex ternal pin, or generating a baud rate for the serial I/O port. Timer/counter events can generate interrupt requests.
2-7
8XC251SA, SB, SP, SQ USER’S MANUAL
The watchdog timer is a circuit that auto matically resets the 8XC251S x in the event of a hardware
or software upset. When enabled by software, the watchdog timer begins running, and unless
software intervenes, the timer reaches a maximum count and initiates a chip reset. In normal operation, software periodically clears th e tim er register to p reven t the reset. If an upset occurs and
software fails to clear the timer, the resulting chip reset di sables the timer and retu rns the sy stem
to a known state. The watchdog and the timer/counters are described in Chapter 8, “Timer/Counters and WatchDog Timer.”
2.3.2 Programmable Counter Array (PCA)
The programmable counter array (PCA) has its own timer and five cap ture/compare modules that
perform several functions: capturing (storing ) the timer value in response to a transition on an input pin; generating an interr upt requ est when the timer matche s a stored value; to ggling an output
pin when the timer matches a stored v alue; gen erating a programmable PWM (pu lse wid th mo dulator) signal on an output pin; and serving as a software watchdog timer. Chapter 9, “Programmable Counter Array,” describes this peripheral in detail.
2.3.3 Serial I/O Port
The serial I/O port provides one synchronous and three asynchronous communication modes.
The synchronous mode (mode 0) is half-duplex: the serial port outputs a clock signal on one pin
and transmits or receives data on another pin.
The asynchronous modes (modes 1–3) are full-duplex (i.e., the port can send and receive simultaneously). Mode 1 uses a serial frame of 10 bits: a start bit, 8 data bits, and a stop bit. The baud
rate is generated by overflow of timer 1 or timer 2. Modes 2 and 3 use a serial fr ame of 11 bits: a
start bit, eight data bits, a programmable ninth data bit, and a stop bit. The ninth bit can be used
for parity checking or to specify that the frame contains an address and data. In mode 2, you can
use a baud rate of 1/32 or 1/64 of the oscillator frequency. In mode 3, you can use the overflow
from timer 1 or timer 2 to determine the baud rate.
In its synchronous modes (modes 1–3) the serial port can operate as a slave in an environment
where multiple slaves share a single serial line. It can accept a message intended for itself or a
message that is being broadcast to all of the slaves, and it can ignore a message sent to another
slave.
2-8
Address Spaces
3
CHAPTER 3
ADDRESS SPACES
MCS® 251 microcontrollers have three address spaces: a memory space, a special function register (SFR) space, and a register file. This chapter describes these address spaces as they apply to
all MCS 251 microcontrollers and to the 8XC251Sx in particular. It also discusses the compatibility of the MCS 251 architecture and the MCS
®
51 architecture in terms of their address spaces.
3.1 ADDRESS SPACES FOR MCS
®
251 MICROCONTROLLERS
Figure 3-1 shows the memory space, th e SFR space, and the register file for M CS251 microcontrollers. (The address spaces are depicted as being eight bytes wide with addresses increasing
from left to right and from bottom to top.)
Memory Address Space
16 Mbytes
FF:FFFFH
SFR Space
512 Bytes
S:1FFH
S:000H
Register File
64 Bytes
S:007H
63
00:0000H
Figure 3-1. Address Spaces for MCS
00:0007H
0
®
251 Microcontrollers
7
A4100-01
3-1
8XC251SA, SB, SP, SQ USER’S MANUAL
It is convenient to v iew the unsegmented, 16-Mb yte memory space as consisting of 256 64-Kbyte
regions, numbered 00: to FF:.
NOTE
The memory space in the MCS 251 architecture is unsegmented. The 64Kbyte “regions” 00:, 01:, ..., FF : are introduced only as a convenience for
discussions. Addressing in the MCS 251 architecture is linear; there are no
segment registers.
MCS 251 microcontrollers can hav e up to 64 Kbytes of on -chip code memo ry in region FF:. Onchip data RAM begins at location 00:0000H. The first 32 bytes (00:0000H–00:001FH) provide
storage for a part of the register file. On-chip, general-purpose data RAM begins at 00:0020H.
The sizes of the on-chip code memory and on-chip RAM depend on the particular device.
The register file has its own address space (Figure 3-1). The 64 locations in the register file are
numbered decimally from 0 to 63. Locations 0–7 represent one of four switchable register banks,
each having 8 registers. The 32 bytes required for these banks occupy locations 00:0000H–
00:001FH in the memory sp ace. Register file locations 8– 63 do no t appear in the memory space.
See “8XC251SA, SB, SP, SQ Register File” on page 3-10 for a further description of the register
file.
The SFR space can accommodate up to 512 8-bit special function registers with addresses
S:000H–S:1FFH. Some of these locations may be unimplemented in a particular device. In the
MCS 251 architecture, the prefix “S:” is used with SFR addresses to distinguish them from the
memory space addresses 00:0000H–0 0:01FFH. See “Special Function Registers (SFRs)” on page
3-16 for details on the SFR space.
®
3.1.1 Compatibility with the MCS
51 Architecture
The address spaces in the MCS 51 architecture† are mapped into the address spaces in the MCS
251 architecture. This mapping allows code written for MCS 51 microco ntro llers to run on MCS
251 microcontrollers. (Chapter 5, “Programming ,” discusses the compatibility of the two instruction sets.)
Figure 3-2 shows the address spaces for the MCS 51 architecture. Internal data mem ory locations
00H–7FH can be addre ssed directly and indirectly. Internal data location s 80H–FFH can only be
addressed indirectly. Directly addressing these locations accesses the SFRs. The 64-Kbyte code
memory has a separate memory space. Data in the code memory can be accessed only with the
MOVC instruction. Similarly, the 64-Kbyte external data memory can be accessed only with the
MOVX instruction.
† MCS®51 Microcontroller Family User’s Manual
3-2
ADDRESS SPACES
The register file (registers R0–R7) comprises four switchable register banks, each having eight
registers. The 32 bytes required for the fou r banks occupy locations 00H–1FH in the on -chip data
memory.
Figure 3-3 shows how the address spaces in the MCS 51 architectu re map into the addre ss spaces
in the MCS 251 architecture; details are listed in Table 3-1.
The 64-Kbyte code memory for MCS 51 microcontrollers maps into region FF: of the memory
space for MCS 251 microcontrollers. Assemblers for MCS 251 microcontrollers assemble code
for MCS 51 microcontrollers into region FF:, and data accesses to code memory are directed to
this region. The assembler also maps the interrupt vectors to region FF:. This mapping is transparent to the user; code executes just as before, without modification.
FFFFH
Code
(MOVC)
0000H
0000H
80H
00H
FFFFH
External Data
(MOVX)
FFH
Internal Data
(indirect)
80H
7FH
Internal Data
(direct, indirect)
Register File
SFRs
(direct)
Figure 3-2. Address Spaces for the MCS® 51 Architecture
R7R0
FFH
A4139-01
3-3
8XC251SA, SB, SP, SQ USER’S MANUAL
Memory Address Space
16 Mbytes
FFFFH
SFR Space
512 Bytes
S:1FFH
FF:0000H
MCS 51 Architecture
Code Memory
0000H
S:100H
FFH
MCS 51 Architecture
SFRs
S:07FH
02:0000H
80H
FFFFH
S:000H
MCS 51 Architecture
External Data Memory
01:0000H
0000H
Register File
64 Bytes
63
FFH
8
MCS 51 Architecture R. F.
0
0
7
A4133-01
00:0000H
MCS 51 Architecture
Internal Data Memory
00H
Figure 3-3. Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture
Table 3-1. Address Mappings
®
51 Architecture MCS® 251 Architecture
MCS
Memory Type
Code 64 Kbytes 0000H–FFFFH
External Data 64 Kbyt es 0000H–FFFFH
Internal Data
SFRs 128 bytes S:80H–S:FFH Direct S:080H–S:0FFH
Register File 8 bytes R0–R7 Register R0–R7
Size Location
128 bytes 00H–7FH Direct, Indirect 00: 0000H–00: 007FH
128 bytes 80H–FFH Indirect 00:0080H–00:00FFH
Data
Addressing
Indirect using
MOVC instr.
Indirect using
MOVX instr.
Location
FF:0000H–FF:FFFFH
01:0000H–01:FFFFH
3-4
ADDRESS SPACES
The 64-Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory
region specified by bits 16–23 of the data pointer DPX, i.e., DPXL. DPXL is accessible as register
file location 57 and also as the SFR at S:084H (see “Dedicated Registers” on page 3-13). The reset value of DPXL is 01H, which maps the external memory to re gion 01: as shown in Figure 3-3.
You can change this mapping by writing a different value to DPXL. A mapping of the MCS 51
microcontroller external data memory into any 64-Kbyte memory region in the MCS 251 architecture provides complete run-time compatibility because the lower 16 address bits are identical
in the two address spaces.
The 256 bytes of on-chip data memory for MCS 51 microcontrollers (00H-FFH) are mapped to
addresses 00:0000H-00:00 FFH to ensur e complete r un- tim e compatibility. In the MCS 51 ar chitecture, the lower 128 bytes (00H-7FH) are directly and indirectly addressable; however the upper 128 bytes are accessible by indirect addressing only. In the MCS 251 architecture, all
locations in region 00: are accessible by direct, indirect, and displacement addressing (see
“8XC251SA, SB, SP, SQ Memory Space” on page 3-5).
The 128-byte SFR space for M CS 51 micro contr ollers is mapped into the 51 2-byte SFR space of
the MCS 251 architecture starting at address S:080H, as shown in Figure 3-3. This pro vides complete compatibility with direct addressing of MCS 51 microcontroller SFRs (including bit addressing). The SFR addresses are unchanged in the new architecture. In the MCS 251
architecture, SFRs A, B, DPL, DPH, and SP (as well as the new SFRs DPXL and SPH) reside in
the register file for high performance. However, to maintain compatibility, they are also mapped
into the SFR space at the same addresses as in the MCS 51 architecture.
3.2 8XC251SA, SB, SP, SQ MEMORY SPACE
Figure 3-4 shows the logical memory space for the 8XC251S x microcon troller. The usable memory space of the 8XC251Sx consists of four 64-Kbyte regions: 00:, 01:, FE:, and FF:. Code can
execute from all four r egions; code execution begins at FF:0000H. Region s 02:–FD: are reserv ed.
Reading a location in the reserved area return s an unspecified value. Sof tware can execute a write
to the reserved area, but nothing is actually written.
All four regions of the memory space are available at the same time. The maximum number of
external address lines is 18, which limits external memory to a maximum of four regions (256
Kbytes). See “Configuring the External Memory Interface” on page 4-8 and “External Memory
Design Examples” on page 13-18.
3-5
8XC251SA, SB, SP, SQ USER’S MANUAL
Memory Address Space
FF:0000H
FE:0000H
16 Mbytes
Regions 02–FD
are Reserved
FF:FFFFH
FE:FFFFH
Indirect and
Displacement
Addressing
(16 Mbytes)
3-6
Register Addressing
(32 Bytes)
Figure 3-4. 8XC251SA, SB, SP, SQ Address Space
01:0000H
00:0080H
00:0020H
00:0000H
01:FFFFH
00:FFFFH
00:007FH
00:001FH
Direct Addressing
(64 Kbytes)
Bit Addressing
(96 Bytes)
A4385-01
†
FF:0000H
FE:0000H
External Memory
On-chip ROM
8 or 16 Kbytes
External Memory
Regions 02–FD
are Reserved
ADDRESS SPACES
FF:FFF7H
FE:FFFFH
01:FFFFH
External Memory
01:0000H
00:FFFFH
External Memory
On-chip RAM
512 or 1024 Bytes
††
00:0000H
†
Eight-byte configuration array (FF:FFF8H - FF:FFFFH)
††
Four banks of registers R0-R7 (32 bytes, 00:0000H - 00:001FH)
Registers R0-R7
A4382-02
Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space
3-7
8XC251SA, SB, SP, SQ USER’S MANUAL
Locations FF:FFF8H–FF:FFFFH are reserved for the configuration array (see Chap ter 4, “Device
Configuration”). The two configuration bytes for the 8XC251Sx are accessed at locations
FF:FFF8H and FF:FFF9H; locations FF:FFFAH–FF:FFFFH are reserved for configuration bytes
in future products. Do not attempt to execute code from locations FF:FFF8H–FF:FFFFH. Also,
see the caution on page 4-2 regarding execution of code from locations immediately below the
configuration array.
Figure 3-4 also indicates the addressing modes that can be used to access dif feren t areas of memory. The first 64 Kbytes can be directly addressed. The first 96 bytes of general-purpose RAM
(00:0020H–00:007FH) are bit addressable. Chapter 5, “Programming,” discusses addressing
modes.
Figure 3-5 on page 3-7 shows how areas of the memory space are implemented by on-chip RAM,
on-chip ROM/OTPROM/EPROM, and external memory. The first 32 bytes of on-chip RAM
store banks 0–3 of the register file (see “8XC251SA, SB, SP, SQ Register File” on page 3-10).
3.2.1 On-chip General-purpose Data RAM
On-chip RAM (512 bytes or 1 Kbyte) is provided for general data storage (Figure 3-5). Instructions cannot execute from on-chip data RAM. The data is accessible by direct, indirect, and displacement addressing. Locations 00:0020H–00:007FH are also bit addressable.
3.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ)
The 8XC251Sx is available with 8 Kbytes or 16 Kbytes of on-chip ROM (83C251Sx) or
OTPROM/EPROM (87C251Sx) as well as without on-chip code memor y (Figure 3-5). Table 2-1
on page 2-3 lists the amount of on-chip code memory for each device. The on-chip
ROM/OTPROM/EPROM is intended primarily for code storage, although its contents can also
be read as data with the indirect and displacement addressing modes. Following a chip reset, program execution begins at FF:0000H. Chapter 14, “Programming and Verifying Nonvolatile
Memory,” describes programming and verification of the ROM/OTPROM/EPROM.
A code fetch within the address range of the on-chip ROM/OTPROM/EPROM accesses the onchip ROM/OTPROM/EPROM only if EA# = 1. For EA# = 0, a code fetch in this address range
accesses external memory. The value of EA# is latched when the chip leaves the reset state. Code
is fetched faster from on-chip code memory than from external memory. Table 3-2 lists the minimum times to fetch two bytes of code from on-chip memory and external memory.
3-8
ADDRESS SPACES
Table 3-2. Minimum Times to Fetch Two Bytes of Code
Type of Code Memory State Times
On-chip Code Memory 1
External Memory (page mode) 2
External Memory (nonpage mode) 4
NOTE
If your program executes exclusively from on-chip ROM/OTPROM/EPROM
(not from external memory), beware of executing code from the upper eight
bytes of the on-chip ROM/OTPROM/EPROM (FF:1FF8H–FF:1FFFH for 8
Kbytes, FF:3FF8H–FF:3FFFH for 16 Kbytes). Because of its pipeline
capability , the 8XC251 Sx may a ttemp t to prefetch code from external memory
(at an address above FF:1FFFH/FF:3FFFH) and thereby disrupt I/O ports 0
and 2. Fetching code constants from these eight bytes does not affect ports 0
and 2.
If your program executes from both on-chip ROM/OTPROM/EPROM and
external memory, your code can be placed in the upper eight bytes of the onchip ROM/OTPROM/EPROM. As the 8XC251Sx fetches bytes above the top
address in the on-chip ROM/OTPROM/EPROM, the code fetches automatically become external bus cycles. In other words, the rollover from on-chip
ROM/OTPROM/EPROM to external code memory is transparent to the user.
3.2.2.1 Accessing On-chip Code Memory in Region 00:
The 87C251SB, SQ and the 83C251S B, SQ can be configured so that the upper half of the 16Kbyte on-chip code memory can also be read as data at locations in the top of region 00: (see
“Configuration Bytes” on page 14-7). Th at is, locations FF:2000H–FF:3FFFH can also be accessed at locations 00:E000H–00:FFFFH. This is useful for accessing code constants stored in
ROM/OTPROM/EPROM. Note, however, that all of the following three conditions must hold for
this mapping to be effective:
• The device is configured with EMAP# = 0 in the UCONFIG1 regi ster (See Chapter 4).
• EA# = 1.
• The access to this area of region 00: is a data read, not a code fetch.
If one or more of th ese cond itions do not h old, accesses to the lo cations in reg ion 00: ar e refer red
to external memory.
NOTE
Remapping does not apply to the 87C251SA, SP and the 83C251SA, SP.
3-9
8XC251SA, SB, SP, SQ USER’S MANUAL
3.2.3 External Memory
Regions 01:, FE:, and portions of regi ons 00: and FF: of the memory space are implemented as
external memory (Figure 3-5 on page 3-7). For discussion s of external memo ry see “Configuring
the External Memory Interface” on page 4-8 and Chapter 13, “External Memory Interface.”
3.3 8XC251SA, SB, SP, SQ REGISTER FILE
The 8XC251Sx register file consists of 40 locations: 0–31 and 56–63, as shown in Figure 3 -6.
These locations are accessible as bytes, words, and dwords, as described in “Byte, Word, and
Dword Registers” on page 3-13. Several locations are dedicated to special registers (see “Dedicated Registers” on page 3-13); the others are general-purpose registers.
3-10
ADDRESS SPACES
Byte Registers
Note: R10 = B
R11 = ACC
R15R14R13R12R11R10R9R8
R7R6R5R4R3R2R1R0
Register File
Locations 32-55 are Reserved
76543210
Banks 0-3
Figure 3-6. The Register File
Word Registers
6362616059585756
3130292827262524
2322212019181716
15141312111098
76543210
WR30WR28WR26WR24
WR22WR20WR18WR16
WR14WR12WR10WR8
WR6WR4WR2WR0
Dword Registers
DR60 = SPXDR56 = DPX
DR28DR24
DR20DR16
DR12DR8
DR4DR0
A4099-01
3-11
8XC251SA, SB, SP, SQ USER’S MANUAL
Register file locations 0–7 actually consist of four switchable banks of eight registers each, as illustrated in Figure 3-7. Th e four bank s are implem ented as the first 32 bytes of on -chip RAM an d
are always accessible as locations 00:0000H–00:001FH in the memory add ress space.† Only one
of the four banks is accessible via the register file at a given time. The accessible, or “active,”
bank is selected by bits RS1 and RS0 in the PSW register, as shown in Table 3-3. (The PSW is
described in “Program Status Words” on page 5-16.) This bank selection can be used for fast context switches.
Register file locations 8–31 and 56–63 are always accessible. These locations are implemented
as registers in the CPU. Register file locations 32–55 are reserved and cannot be accessed.
PSW bits RS1:0
select one bank
to be accessed via
the register file.
Register File
8
01234567
0 1234567
01234567
01234567
01234567
Banks 0–3
63
Memory Address Space
00:0020H
18H 1FH
10H 17H
08H 0FH
00H 07H
Figure 3-7. Register File Locations 0–7
Table 3-3. Register Bank Selection
Bank Address Range
Bank 0 00H–07H 0 0
Bank 1 08H–0FH 0 1
Bank 2 10H–17H 1 0
Bank 3 18H–1FH 1 1
PSW Selection Bits
RS1 RS0
FF:FFFFH
Banks 0–3
accessible
in memory
address space
A4215-01
† Because these locations are dedicated to the register file, they are not considered a part of the general-
purpose, 1-Kbyte, on-chip RAM (locations 00:0020H–00:041FH).
3-12
ADDRESS SPACES
3.3.1 Byte, Word, and Dword Registers
Depending on its location in the register file, a register is addressable as a byte, a word, and/or a
dword, as shown on the right side of Figure 3-6. A register is named for its lowest numbered byte
location. For example:
R4 is the byte register consisting of location 4.
WR4 is the word register consisting of registers 4 and 5.
DR4 is the dword register consisting of registers 4–7.
Locations R0–R15 are addressable as bytes, words, or dwords. Locations 16–31 are addressable
only as words or dwords. Locations 56–63 are addressable only as dwords. Registers are addressed only by the names shown in Figure 3-6 — except for the 32 registers that comprise the
four banks of registers R0–R7, which can also be accessed as locations 00:0000H–00:001FH in
the memory space.
3.3.2 Dedicated Registers
The register file has four dedicated registers:
• R10 is the B-register
• R11 is the accumulator (ACC)
• DR56 is the extended data pointer, DPX
• DR60 is the extended stack pointer, SPX
These registers are located in the register file; however, R10, R11, and some bytes of DR56 and
DR60 are also accessible as SFRs. The bytes of DPX and SPX can be accessed in the register file
only by addressing the dword registers. The dedicated registers in the register file and their corresponding SFRs are illustrated in Figure 3-8 and listed in Table 3-4.
3.3.2.1 Accumulator and B Register
The 8-bit accumulator (ACC) is byte register R11, which is also accessible in the SFR space as
ACC at S:E0H (Figure 3-8). The B register , used in multiplies and divides, is register R10, which
is also accessible in the SFR space as B at S:F0H. Accessing ACC or B as a register is one state
faster than accessing them as SFRs.
3-13
8XC251SA, SB, SP, SQ USER’S MANUAL
Instructions in the MCS 51 architecture use the accumulator as the primary register for data
moves and calculations. However, in the MCS 251 architecture, any of registers R1–R15 can
serve for these tasks†. As a result, the accumulator does not play the central role that it has in
MCS 51 microcontrollers.
Register File
Stack Pointer, High
SPH
60
DR60 = Extended Stack Pointer, SPX
56
DR56 = Extended Data Pointer, DPX
R10, B Register
61
Data Pointer Extended, Low
DPXL
57
B
62
Data Pointer, High
DPH
58
ACC
R11, Accumulator, ACC
SP
63
DPL
Stack Pointer
Data Pointer, Low
59
SFRs
SPH
SP
DPXL
DPH
DPL
B
ACC
S:BEH
S:81H
S:84H
S:83H
S:82H
S:F0H
S:E0H
A4152-02
Figure 3-8. Dedicated Registers in the Register File and their Corresponding SFRs
† Bits in the PSW and PSW1 registers reflect the status of the accumulator. There are no equivalent status
indicators for the other registers.
3-14
ADDRESS SPACES
3.3.2.2 Extended Data Pointer, DPX
Dword register DR56 is the extended data pointer, DPX (Figure 3-8). The lower three bytes of
DPX (DPL, DPH, and DPXL) are accessible as SFRs. DPL and DPH comprise the 16-bit data
pointer DPTR. While instructions in the MCS 51 architecture always use DP TR as the data pointer, instructions in the MCS 251 architecture can use any word or dword register as a data pointer.
DPXL, the byte in location 57, specifies the region of memory (00:–FF:) that maps into the 64Kbyte external data memory space in the MCS 51 architecture. In other words, the MOVX instruction addresses the region specified by DPXL when it moves data to and from external memory. The reset value of DPXL is 01H.
3.3.2.3 Extended Stack Pointer, SPX
Dword register DR60 is the stack pointer, SPX (Figure 3-8). The byte at locat ion 63 is the 8-bit
stack pointer, SP, in the MCS 51 architecture. The byte at location 62 is the stack pointer high,
SPH. The two bytes allow the stack to extend to the top of memory region 00:. SP and SPH can
be accessed as SFRs.
Two instructions, PUSH and POP directly address the stack pointer. Subroutine calls (ACALL,
ECALL, LCALL) and returns (ERET, RET, RETI) also use the stack pointer. To preserve the
stack, do not use DR60 as a general-purpose register.
Table 3-4. Dedicated Registers in the Register File and their Corresponding SFRs
Register File SFRs
Name Mnemonic Reg. Location Mnemonic Address
——
Stack
Pointer
(SPX)
Data
Pointer
(DPX)
Accumulator (A Register) A R11 11 ACC S:E0H
B Register B R10 10 B S:F0H
Stack Pointer, High SPH 62 SPH S:BEH
Stack Pointer, Low SP 63 SP S:81H
Data Pointer, Extended Low DPXL 57 DPXL S:84H
DPTR
——61——
——
Data Pointer, High DPH 58 DPH S:83H
Data Pointer, Low DPL 59 DPL S:82H
DR60
DR56
60 — —
56 — —
3-15
8XC251SA, SB, SP, SQ USER’S MANUAL
3.4 SPECIAL FUNCTION REGISTERS (SFRS)
The special function registers (SFRs) reside in their associated on-chip perip herals or in the core.
T able 3-5 shows the S FR address space with the SFR mnemonics and reset values. S FR addresses
are preceded by “S:” to differentiate them from addresses in the memory space. Unoccupi ed locations in the SFR space (the shaded locations in Table 3-5) are unimplemented, i.e., no register
exists. If an instruction attempts to write to an unimplemented S FR location , the instruction executes, but nothing is actually written. If an unimplemented SFR location is read, it returns an unspecified value.
NOTE
SFRs may be accessed only as bytes; they may not be accessed as words or
dwords.
3-16
F8
F0
E8
E0
D8
D0
C8
ADDRESS SPACES
T a ble 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Va lues
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
B
00000000
ACC
00000000
CCON
00x00000
PSW
00000000
T2CON
00000000
CH
00000000
CL
00000000
CMOD
00xxx000
PSW1
00000000
T2MOD
xxxxxx00
CCAP0H
xxxxxxxx
CCAP0L
xxxxxxxx
CCAPM0
x0000000
RCAP2L
00000000
CCAP1H
xxxxxxxx
CCAP1L
xxxxxxxx
CCAPM1
x0000000
RCAP2H
00000000
CCAP2H
xxxxxxxx
CCAP2L
xxxxxxxx
CCAPM2
x0000000
TL2
00000000
CCAP3H
xxxxxxxx
CCAP3L
xxxxxxxx
CCAPM3
x0000000
TH2
00000000
CCAP4H
xxxxxxxx
CCAP4L
xxxxxxxx
CCAPM4
x0000000
FF
F7
EF
E7
DF
D7
CF
C0
IPL0
B8
x0000000
B0
A8
A0
98
90
88
80
P3
11111111
IE0
00000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111SP00000111
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
NOTE: Shaded areas represent unimplemented SFR locations. Locations S:000H –S:07FH and
SADEN
00000000
SADDR
00000000
SBUF
xxxxxxxx
TMOD
00000000
S:100H–S:1FFH are also unimplemented.
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
TH0
00000000
DPXL
00000001
SPH
00000000
WDTRST
xxxxxxxx
TH1
00000000
IPH0
x0000000
WCON
xxxxxx00
PCON
00xx0000
C7
BF
B7
AF
A7
9F
97
8F
87
3-17
8XC251SA, SB, SP, SQ USER’S MANUAL
The following tables list the mnemonics, names, and addresses of the SFRs:
Table 3-6 — Core SFRs
Table 3-7 — I/O Port SFRs
Table 3-8 — Serial I/O SFRs
Table 3-9 — Timer/Counter and Watchdog Timer SFRs
Table 3-10 — Programmable Counter Array (PCA) SFRs
Table 3-6. Core SFRs
Mnemonic Name Address
†
ACC
†
B
PSW Progr am Status Word S:D0H
PSW1 Program Status Word 1 S:D1H
†
SP
†
SPH
†
DPTR
DPL
DPH
†
DPXL
PCON Power Control S:87H
IE0 Interrupt Enable Control 0 S:A8H
IPH0 Interrupt Priority Control High 0 S:B7H
IPL0 Interrupt Priority Control Low 0 S:B8H
†
These SFRs can also be accessed by their corresponding registers in the
register file (see Table 3-4 on page 3-15).
Accumulator S:E0H
B Register S:F0H
Stack Pointer – LSB of SPX S:81H
Stack Pointer High – MSB of SPX S:BEH
Data Pointer (2 bytes) —
†
†
Low Byte of DPTR S:82H
High Byte of DPTR S:83H
Data Pointer, Extended Low S:84H
3-18
Table 3-7. I/O Port SFRs
Mnemonic Name Address
P0 Port 0 S:80H
P1 Port 1 S:90H
P2 Port 2 S:A0H
P3 Port 3 S:B0H
ADDRESS SPACES
Table 3-8. Serial I/O SFRs
Mnemonic Name Address
SCON Serial Control S:98H
SBUF Serial Data Buffer S:99H
SADEN Slave Address Mask S:B9H
SADDR Slave Address S:A9H
Table 3-9. Timer/Counter and Watchdog Timer SFRs
Mnemonic Name Address
TL0 Timer/Counter 0 Low Byte S:8AH
TH0 Timer/Counter 0 High Byte S:8CH
TL1 Timer/Counter 1 Low Byte S:8BH
TH1 Timer/Counter 1 High Byte S:8DH
TL2 Timer/Counter 2 Low Byte S:CCH
TH2 Timer/Counter 2 High Byte S:CDH
TCON Timer/Counter 0 and 1 Control S:88H
TMOD Timer/Counter 0 and 1 Mode Control S:89H
T2CON Timer/Counter 2 Control S:C8H
T2MOD Tim er/ Counter 2 Mode Control S:C9H
RCAP2L Timer 2 Reload/Capture Low Byte S:CAH
RCAP2H Timer 2 Reload/Capture High Byte S:CBH
WDTRST WatchDog Timer Reset S:A6H
Table 3-10. Programmable Counter Array (PCA) SFRs
Mnemonic Name Address
CCON PCA Timer/Counter Control S:D8H
CMOD PCA Timer/Counter Mode S:D9H
CCAPM0 PCA Timer/Counter Mode 0 S:DAH
CCAPM1 PCA Timer/Counter Mode 1 S:DBH
CCAPM2 PCA Timer/Counter Mode 2 S:DCH
CCAPM3 PCA Timer/Counter Mode 3 S:DDH
CCAPM4 PCA Timer/Counter Mode 4 S:DEH
3-19
8XC251SA, SB, SP, SQ USER’S MANUAL
Table 3-10. Programmable Counter Array (PCA) SFRs (Continued)
Mnemonic Name Address
CL PCA Timer/Counter Low Byte S:E9H
CH PCA Timer/Counter High Byte S:F9H
CCAP0L PCA Compare/Capture Module 0 Low Byte S:EAH
CCAP1L PCA Compare/Capture Module 1 Low Byte S:EBH
CCAP2L PCA Compare/Capture Module 2 Low Byte S:ECH
CCAP3L PCA Compare/Capture Module 3 Low Byte S:EDH
CCAP4L PCA Compare/Capture Module 4 Low Byte S:EEH
CCAP0H PCA Compare/Capture Module 0 High Byte S:FAH
CCAP1H PCA Compare/Capture Module 1 High Byte S:FBH
CCAP2H PCA Compare/Capture Module 2 High Byte S:FCH
CCAP3H PCA Compare/Capture Module 3 High Byte S:FDH
CCAP4H PCA Compare/Capture Module 4 High Byte S:FEH
3-20
Device
Configuration
4
CHAPTER 4
DEVICE CONFIGURAT IO N
The 8XC251Sx provides user design flexibility by configuring certain operating features at device reset. These features fall into the following categories:
• external memory interface (page mode, address bits, pre-programmed wait states and the
address range for RD#, WR#, and PSEN#)
• source mode/binary mode opcodes
• selection of bytes stored on the stack by an interrupt
• mapping of the upper portion of on-chip code memory to region 00:
You can specify a 16-bit, 17-bit, or 18-bit external address bus (256 Kbyte external address
space). Wait state configurations provide pre-programmed 0, 1, 2, or 3 wait states.
This chapter provides a detailed discussion of 8XC251Sx device configuration. It describes the
configuration bytes and provides information to aid you in selecting a suitable configuration for
your application. It discusses the choices involved in configuring the external memory interface
and shows how the internal memory maps into the external memory. See 4.5, “Configuring the
External Memory Interface.” Section 4.6, “Opcode Configurations (SRC),” discusses the choice
of source mode or binary mode opcode arrangements.
4.1 CONFIGURATION OVERVIEW
®
The configuration of the MCS
information stored in configuration bytes. The 8XC251Sx microcontrollers store configuration
information in two configuration bytes located in code memory. Devices with no on-chip code
memory fetch configuration data from external memory. Factory programmed ROM devices use
customer provided configuration data supplied on floppy disc.
4.2 DEVICE CONFIGURATION
The 8XC251Sx reserves the top eight b ytes of the memo ry addr ess map (FF:FFF8H–FF:FFFFH)
for an eight-byte configu ration array (Figure 4-1). The two lowest bytes of the configuration ar ray
are assigned to the user configuration bytes UCONFIG0 (FF:FFF8H) and UCONFIG1
(FF:FFF9H). For ROM/OTPROM/EPROM devices, configuration information is stored in onchip non-volatile memory at these addresses. For devices without on-chip
ROM/OTPROM/EPROM, configuration information is accessed from external memory .
251 microcontroller is established by the res et routine based on
4-1
8XC251SA, SB, SP, SQ USER’S MANUAL
For ROM/OTPROM/EPROM devices, user configuration bytes UCONFIG0 and UCONFIG1
can be programmed at the factory or on-site using the procedures provided in Chapter 14, “Programming and Verifying Nonvolatile Memory.” For devices without ROM/OTPROM/ EPROM,
the designer should store configuration information in an eight-byte configurat ion array located
at the highest addresses implemented in external code memory. See Table 4-1 and Figure 4-2.
Bit definitions of UCONFIG0 and UCONFIG1 are provided in Figures 4-3 and 4-4. The upper 6
bytes of the configuration ar ray are reserved for future use. When EA# = 1, the 8XC25 1Sx obtains
configuration information at reset from on-chip no n-volatile memory at addresses FF:FFF8H and
FF:FFF9H. When EA# = 0, the microcontroller obtains configuration information at reset from
the external memory system using internal addresses FF:FFF8H and FF:FFF9H.
CAUTION
The eight highest addresses in the memory address space (FF:FFF8H–
FF:FFFFH) are reserved for the configuration array. Do not read or write these
locations. These addresses are also used to access the configuration array in
external memory, so the same restrictions apply to the eight highest addresses
implemented in external memory. Instructions that might inadvertently cause
these addresses to be accessed due to call returns or prefetches should not be
located at addresses immediately below the configuration array. Use an EJMP
instruction, five or more addresses below the configuration array, to continue
execution in other areas of memory.
83C251SA, SP
87C251SA, SP
8 Kbytes
For EA# = 1, the 8XC251Sx obtains configuration information
from on-chip nonvolatile memory at addresses FF:FFF8H
and FF:FFF9H.
16 Kbytes
83C251SB, SQ
87C251SB, SQ
FF:FF:
Figure 4-1. Configuration Array (On-chip)
4-2
FF:FFFFH
FF:FFFEH
FF:FFFDH
FF:FFFCH
FF:FFFBH
FF:FFFAH
FF:FFF9H
FF:FFF8H
Detail. On-chip configuration array.
Reserved
UCONFIG1
UCONFIG0
A4237-01
DEVICE CONFIGURATION
FFF9H
FFF8H
x
:xFFFH
x
:xFFEH
x
:xFFDH
x
:xFFCH
x
:xFFBH
x
:xFFAH
x
:xFF9H
x
:xFF8H
64 Kbytes
Reserved
UCONFIG1
UCONFIG0
1FF9H
1FF8H
1:FFF9H
1:FFF8H
8 Kbytes
128 Kbytes
3FF9H
3FF8H
3:FFF9H
3:FFF8H
16 Kbytes
256 Kbytes
7FF9H
7FF8H
32 Kbytes
Detail.
Configuration array in external memory.
This figure shows the addresses of configuration bytes UCONFIG1 and UCONFIG0 in external memory for
several memory implementations. For EA# = 0, the 8XC251Sx obtains configuration information from configuration
bytes in external memory using internal addresses FF:FFF8H and FF:FFF9H. In external memory, the eight-byte
configuration array is located at the highest addresses implemented.
A4236-01
Figure 4-2. Configuration Array (External)
4-3
8XC251SA, SB, SP, SQ USER’S MANUAL
Table 4-1. External Addresses for Configuration Array
Size of External
Address Bus
(Bits)
16 FFF8H–FFFFH UCONFIG1: FFF9H
17 1FFF8H–1FFFFH UCONFIG1: 1FFF9H
18 3FFF8H–3FFFFH UCONFIG1: 3FFF9H
NOTES:
1. W hen EA # = 0, the reset rout ine r etrieves UCO NF IG0 and UCO NF IG1 f rom
external memory using internal addresses FF:FFF8H and FF:FFF 9H, which
appear on the microcontroller external address bus (A17, A16, A15:0).
2. The upper six bytes of the configuration array are reserved for future use.
Address of
Configuration Array on
External Bus (2)
Address of
Configuration Bytes
on External Bus (1)
UCONFIG0: FFF8H
UCONFIG0: 1FFF8H
UCONFIG0: 3FFF8H
4.3 THE CONFIGURATION BITS
This section provides a brief description of the configuration bits contained in the configuration
bytes (Figures 4-3 and 4-4). UCONFIG0 and UCONFIG1 have five wait state bits: WSA1:0#,
WSB1:0#, and WSB.
• UCON. Configuration byte location selector.
• SRC. Selects source mode or binary mode opcode configuration.
• INTR. Selects the bytes pushed onto the stack by interrupts.
• EMAP#. Maps on-chip code memory (16-Kbyte devices only) to memory region 00:.
The following bits configure the external memory interface.
• PAGE#. Selects page/nonpage mode and specifies the data port.
• RD1:0. Selects the number of external address bus pins and th e address rang e for RD#, WR,
and PSEN#. See Table 4-2.
• XALE#. Extends the ALE pulse.
• WSA1:0#. Selects 0, 1, 2, or 3 pre-programmed wait states for all regions except 01:.
• WSB1:0#. Selects 0 - 3 pre-programmed wait states for memory region 01:.
• EMAP#. Affects the external memory interface in that, when asserted, addresses in the
range 00:E000H–00:FFFH access on-chip memory.
4-4
DEVICE CONFIGURATION
4.4 CONFIGURATION BYTE LOCATION SELECTOR (UCON)
The Configuration Byte Location Selecto r (UCON) applies only to OTPROM and EPROM products. In conjunction with EA#, UCON specifies whether the configu ration array is accessed from
on-chip memory or external memory.
If the UCON bit is clear (e.g., UCON=0), the configuration array is fetched from on-ch ip nonvolatile memory at addresses FF:FFF8H to FF:FFFFH. The configuration bytes are located at locations FF:FFF8H and FF:FFF9H.
If UCON is set (e.g., UCON=1), the state of the EA# pin at device reset determines whether the
configuration array is accessed from on-chip memory or external memory. If EA# is connected
to V
FF:FFF8H through FF:FFFFH (same as for UCON=0). If EA# is connected to V
, the configuration array is accessed from on-chip nonvolatile memory at addresses
CC
, the configu-
SS
ration array is obtained from external memory (e.g., a 27512 EPROM).
4-5
8XC251SA, SB, SP, SQ USER’S MANUAL
UCONFIG0
Address:FF:FFF8H (2)
(1), (3)
7 0
UCON WSA1# WSA0# XALE# RD1 RD0 PAGE# SRC
Bit
Number
7 UCON
Bit
Mnemonic
87C251Sx
Function
Configuration Byte Location Selector (OTPROM/EPRO M products only):
Clearing this bit causes the 8XC251S
from on-chip memory. Leaving this bit unprogrammed (logic 1) causes the
8XC251S
x
to fetch configuration information from on-chip memory if EA# =
x
to fetch configuration information
1 or from external memory if EA# = 0.
—
80C251Sx
Reserved:
Write a 1 to this bit when programming UCONFIG0.
83C251Sx
6:5 WSA1:0# Wait State A (all regions except 01:):
For external memory accesses, selects the number of wait states for RD#,
WR#, and PSEN#.
WSA1# WSA0#
0 0 Inserts 3 wait states for all regions except 01:
0 1 Inserts 2 wait states for all regions except 01:
1 0 Inserts 1 wait state for all regions except 01:
1 1 Zero wait states for all regions except 01:
4 XALE # Extend ALE:
Set this bit for ALE = T
Clear this bit for ALE = 3T
.
OSC
(adds one external wait state).
OSC
3:2 RD1:0 Memory Signal Selection:
RD1:0 bit codes specify an 18-bit, 17-bit, or 16-bit external address bus and
address ranges for RD#, WR#, and PSEN#. See Table 4-2.
1 PAGE# Page Mode Select:
Clear this bit for page mode enabled with A15:8/D7:0 on P2 and A7:0 on P0.
Set this bit for page mode disabled with A15:8 on P2 and A7:0/D7:0 on P0
(compatible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers).
0 SRC Source Mode/Binary Mode Select:
Clear this bit for binary mode (compatible with MCS 51 microcontrollers).
Set this bit for source mode.
NOTES:
1. User conf igu ration byt es UCO NFI G0 and UCONF IG1 define the conf igurat ion of the 8XC251S
x
.
2. Addres s. UCONFIG0 is the second-lowest byte of the 8-byte configuration array. As determined by
UCON and EA#, the 8XC251S
x
fetches configuration information from o n-chip nonvolatile memory at
addresses FF:FFF8H and FF:FFF9H or from external mem ory using these same addresses. In external memory, configuration information is obtained from an 8-byte configuration array located at the
highest addresses implemented. The location of the configuration array in external memory dep ends
on the size and decode arrangement of the external memory (Table 4-1 and Figure 4-2).
3. Inst ruct ions for programm ing and verifying on-chip configurat ion bytes are given in Chapter 14.
Figure 4-3. Configuration Byte UCONFIG0
4-6
DEVICE CONFIGURATION
UCONFIG1
(1), (3)
7 0
— — — INTR WSB WSB1# WSB0# EMAP#
Bit
Number
7:5 — Reserved for internal or future use. Set these bits when programming
4 INTR Interrupt Mode:
3 WSB Wait State B. Use only for A-step compatibility:
2:1 WSB1:0# External Wait State B (Region 01:):
0 EMAP# EPROM Map:
NOTES:
1. User conf igu ration byt es UCO NFI G0 and UCONF IG1 define the conf igurat ion of the 8XC251S
2. Addres s. UCONFIG1 is the second-lowest byte of the 8-byte configuration array. As determined by
UCON and EA#, the 8XC251SA, SB, SP, SQ fetches configuration information from on-chip nonvolatile
memory at addresses FF:FFF8H and FF:FFF9H or from external memory using these same
addresses. In external memory, configuration information is obtained from an 8-byte configuration
array located at the highest addresses implemented. The physical location of the configuration array in
external memory depends on the size and decode arrangement of the external memory (Table 4-1 and
Figure 4-2).
3. Inst ruct ions for programm ing and verifying on-chip configurat ion bytes are given in Chapter 14.
Bit
Mnemonic
Function
UCONFIG1.
If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the PC
and PSW1). If this bit is clear, interrupts push the 2 lower bytes of the PC
onto the stack. See 4.8, “Interrupt Mode (INTR).”
Clear this bit to generate one external wait state for memory region 01:. Set
this bit for no wait states for region 01:.
WSB1# WSB0#
0 0 Inserts 3 wait states for region 01:
0 1 Inserts 2 wait states for region 01:
1 0 Inserts 1 wait state for region 01:
1 1 Zero wait states for region 01:
For devices with 16 Kbytes of on-chip code memory , clear this bit to map the
upper half of on-chip code memory to region 00: (data memory). Maps
FF:2000H–FF:3FFFH to 00:E000H–00:FFFFH. If this bit is set, mapping
does not occur and addresses in the range 00:E000H–00:FFFFH
external RAM. See 4.7, “Mapping On-chip Code Memory to Data Memory
(EMAP#).”
Address:FF:FFF9H (2)
access
x
.
Figure 4-4. Configuration Byte UCONFIG1
4-7
8XC251SA, SB, SP, SQ USER’S MANUAL
Table 4-2. Memory Signal Selections (RD1:0)
RD1:0
0 0 A17 A16 Asserted for
0 1 P1.7/CEX4/
1 0 P1.7/CEX4/
1 1 P1.7/CEX4/
P1.7/CEX/
A17/WCLK
WCLK
WCLK
WCLK
P3.7/RD#/A16 PSEN# WR# Features
all addresses
A16 Asserted for
P3.7 only Asserted for
RD# asserted
for addresses
≤ 7F:FFFFH
all addresses
all addresses
Asserted for
≥ 80:0000H
Asserted for writes to
all memory locations
Asserted for writes to
all memory locations
Asserted for writes to
all memory locations
Asserted only for
writes to MCS 51
microcontroller data
memory locations.
256-Kbyte external
memory
128-Kbyte external
memory
64-Kbyte external
memory. One
additional port pin.
64-Kbyte external
memory. Compatible
with MCS 51 microcontrollers.
4.5 CONFIGURING THE EXTERNAL MEMORY INTERFACE
This section describes the configuration options that affect the external memory i nterface. The
configuration bits described here determine the following interface features:
• page mode or nonpage mode (PAGE#)
• the number of external address pins (16, 17, or 18) (RD1:0)
• the memory regions assigned to the read signals RD# and PSEN# (RD1:0)
• the external wait states (WSA1:0#, WSB1:0#, XALE#)
• mapping a portion of on-chip code memory to data memory (EMAP#)
4.5.1 Page Mode and Nonpage Mode (PAGE#)
The PAGE# bit (UCONFIG0.1) determines whether code fetches use page mode or nonpage
mode and whether data is transmitted on P2 or P0. See Figure 13-1 on page 13-1 and section
13.2.3, “Page Mode Bu s Cycles,” for a description of the bus structure and page mode o peration.
• Nonpage mode: PAGE# = 1. The bus structure is the same as for the MCS 51 architecture
with data D7:0 multiplexed with A7:0 on P0. External code fetches require two state times
).
(4T
OSC
• Page mode: PAGE# = 0. The bus structure differs from the bus structure in MCS 51
controllers. Data D7:0 is multiplexed with A15:8 on P2. Under certain conditions, external
code fetches require only one state time (2T
4-8
OSC
).
DEVICE CONFIGURATION
4.5.2 Configuration Bits RD1:0
The RD1:0 configuration bits (UCONFIG0.3:2) determin e the number of external address signals
and the address ranges for asserting the read signals PSEN#/RD# and the write signal WR#.
selections o ffer different ways of addressing external memory. Figures 4-5 and 4-6 show
These
how internal memory maps into ex ternal memory for the fou r values of RD1:0. Section 13.8, “E xternal Memory Design Examples,” provides examples of external memory designs for each
choice of RD1:0.
A key to the memory interface is the relationship between internal memory addresses and external memory addresses. While the 8XC251 S x has 24 internal addr ess bits, the number of ex ternal
address lines is less than 24 (i.e., 16, 17, or 18 depending on the values of RD1:0). This means
that reads/writes to different internal memory addresses can access the same location in external
memory.
For example, if the 8XC251Sx is configured for 17 external address lines, a write to location
01:6000H and a write to location FF:6 000H accesses the same 17-bit extern al address (1:600 0H)
because A16 = 1 for both internal addresses. In other words, regions 01: and FF: map into the
same 64-Kbyte region in external memory.
In some situations, however , a mu ltiple mapping from internal mem ory to extern al memory do es
not preclude using more than one region. For example, for a device with on-chip ROM/
OTPROM/EPROM configured for 17 address bits and with EA# = 1, an access to FF:0000H–
FF:3FFFH (16 Kbytes) accesses the on-chip ROM/OTPROM/EPROM, while an access to
01:0000H–01:3FFFH is to external memory. In this case, you could execute code from these locations in region FF: and store data in the corresponding locations in region 0 1: witho ut conflict.
See Figure 4-5 and section 13.8.3, “Example 3: RD1:0 = 01, 17-bit Bus, Ext e rnal RAM.”
4.5.2.1 RD1:0 = 00 (18 External Address Bits)
The selection RD1:0 = 00 provides 18 external address bits: A15:0 (ports P0 and P2), A16 (from
P3.7/RD#/A16), and A17 (from P1.7/CEX4/A17/WCLK). Bits A16 and A17 can select four 64Kbyte regions of external memory for a total of 256 Kbytes (top half of Figure 4- 5). This is the
largest possible external memory space. See section 13.8 .1, “Example 1: RD1:0 = 00, 1 8-bit Bus,
External Flash and RAM.”
4.5.2.2 RD1:0 = 01 (17 External Address Bits)
The selection RD1:0 = 01 provides 17 external address bits: A15:0 (ports P0 and P2) and A16
(from P3.7/RD#/A16). Bit A16 can select two 64-Kbyte regions of external memory for a total
of 128 Kbytes (bottom half of Figure 4-5). Regions 00: and FE: (each having A16 = 0) map into
the same 64-Kbyte region in external memory. This duplication also occurs for regions 01: and
FF:
4-9
8XC251SA, SB, SP, SQ USER’S MANUAL
This selection provides a 128-Kbyte external address space. The advantage of this selection, in
comparison with the 256-Kbyte external memory space with RD1:0 = 00, is the availability of
pin P1.7/CEX4/A17/WCLK for general I/O, PCA I/O, and real-time wait clock output. I/O P3.7
is unavailable. All four 64-Kbyte regions are strobed by PSEN# and WR#. Sections 13.8.2 and
13.8.3 show examples of memory designs with this option.
RD1:0 = 00
18 external address bits:
P0, P2, A16, A17
Notes:
1. Maximum external
memory
2. Single read signal
RD1:0 = 01
17 external address bits:
P0, P2, A16
Note:
Single read signal
Internal Memory with
Read/Write Signals
PSEN#, WR#
PSEN#, WR#
Internal Memory with
Read/Write Signals
PSEN#, WR#
PSEN#, WR#
FF:
FE:
01:
00:
FF:
FE:
01:
00:
A17:16
1 1
1 0
0 1
0 0
A16
1
0
External
Memory
256 Kbytes
FF:
FE:
01
00
External
Memory
128 Kbytes
01:, FF:
00:, FE:
4-10
A4218-02
Figure 4-5. Internal/External Address Mapping (RD1:0 = 00 and 01)
RD1:0 = 10
DEVICE CONFIGURATION
16 external address bits:
P0, P2
Notes:
1. Single read signal
2. P3.7/RD#/A16 functions
only as P3.7
RD1:0 = 11
16 external address bits:
P0, P2
Note:
1. Compatible with MCS
microcontrollers
2. Cannot write to regions FC:–FF:
®
51
Internal Memory with
Read/Write Signals
PSEN#, WR#
PSEN#, WR#
Internal Memory with
Read/Write Signals
PSEN#
RD#, WR#
FF:
FE:
01:
00:
FF:
FE:
01:
00:
External
Memory
64 Kbytes
00:, 01:, FE:, FF:
External
Memory
128 Kbytes
FE:, FF:
00:, 01:
Figure 4-6. Internal/External Address Mapping (RD1:0 = 10 and 11)
A4217-02
4-11
8XC251SA, SB, SP, SQ USER’S MANUAL
4.5.2.3 RD1:0 = 10 (16 External Address Bits)
For RD1:0 = 10, the 16 external address bits (A15:0 on ports P0 and P2) provide a single 64Kbyte region in external memory (top of Figure 4-6). This selection provides the smallest external memory space; however, pin P3.7/RD#/A16 is available for general I/O and pin
P1.7/CEX4/A17/WCLK is available for general I/O, PCA I/O, and real-time wait clock output.
This selection is useful when the avai lability of these pins is required and/or a small amount o f
external memory is sufficient.
4.5.2.4 RD1:0 = 11 (Compat ible with MCS 51 Microcontrolle rs )
The selection RD1:0 = 11 provides only 16 external address bits (A15:0 on ports P0 and P2).
However , PSEN# is the read signal for regions FE:–FF:, while RD# is the read signal for regions
00:–01: (bottom of Figure 4- 6). The two read signals effectively expand the external memory
space to two 64-Kbyte regions. WR# is asser ted only for writes to regions 0 0:–01:. This selection
provides compatibility with MCS 51 microcontrollers, which have separate ext ernal memor y
spaces for code and data.
4.5.3 Wait State Configuration Bits
You can add wait states to external bus cycles by extending the RD#/WR#/PSEN# pulse and/or
extending the ALE pulse. Each additional wait state extends the pulse by 2T
. A separate wait
OSC
state specification for external accesses via region 01: permits a slow external device to be addressed in region 01: without slowing accesses to other external devices. Table 4-3 summarizes
the wait state selections for RD#,WR#,PSEN#. For waveform diagrams showing wait states, see
section 13.4, “External Bus Cycles with Configurable Wait States.”
4.5.3.1 Configuration Bits WSA1:0#, WSB1:#
The WSA1:0# wait state bits (UCONFIG0.6:5) permit RD#, WR#, and PSEN# to be extended by
1, 2, or 3 wait states for accesses to external memory via all regions except region 01:. The
WSB1:0# wait state bits (UCONFIG1.2:1) permit RD#, WR#, and PSEN# to be extended by 1,
2, or 3 wait states for accesses to external memory via region 01:.
4.5.3.2 Configuration Bit WSB
Use the WSB bit only for A-stepping compatibility. The WSB wait state bit (UCONFIG1.3) permits RD#, WR#, and PSEN# to be extended by one wait state for accesses to external memor y
via region 01:.
4-12
4.5.3.3 Configuration Bit XALE#
DEVICE CONFIGURATION
Clearing XALE# (UCONFIG0.4) extends the time ALE is asserted from T
OSC
to 3T
. This ac-
OSC
commodates an address latch that is too slow for the normal ALE signal. Section 13.4.2, “Extending ALE,” shows an external bus cycle with ALE extended.
Table 4-3. RD#, WR#, PSEN# External Wait States
8XC251S
Regions
00: FE: FF:
Region 01: WSB1# WSB0#
WSA1# WSA0#
x
00
01
10
11
00
01
10
11
3 Wait States
2 Wait States
1 Wait State
0 Wait States
3 Wait States
2 Wait States
1 Wait State
0 Wait States
4.6 OPCODE CONFIGURATIONS (SRC)
The SRC configuration bit (UCONFIG0.0) selects the source mode or binary mode opcode arrangement. Opcodes for the MCS 251 architecture are listed in Table A-6 on page A-4 and Table
A-7 on page A-5. Note that in Table A-6 every opcode (00H–FFH), is used for an instruction except A5H (ESC) which provides an alternative set of opcodes for columns 6H through F H. The
SRC bit selects which set of opcodes is assigned to columns 6H through FH and which set is the
alternative.
Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for
the MCS 251 architecture. One of these modes must be selected when the chip is configured. Depending on the application, binary mode or source mode may produce more efficient code. This
section describes the binary and source modes and provides some guidelines for selecting the
mode for your application.
The MCS 251 architecture has two types of instructions :
• instructions that originate in the MCS 51 architecture
• instructions that are unique to the MCS 251 architecture
4-13
8XC251SA, SB, SP, SQ USER’S MANUAL
Figure 4-7 shows the opcode map for binary mode. Area I (columns 1 through 5 in Table A-6 on
page A-4) and area II (columns 6 through F) make up the opcode map for the instructions that
originate in the MCS 51 architecture. Area III in Figure 4-7 represents the opcode map for the
instructions that are uniqu e to the MCS 251 architecture (Table A-7 on page A-5). Note that some
of these opcodes are reserved for future instructions. The opcode values for areas II and III are
identical (06H–FFH). To distinguish between the two areas in binary mode, the opcodes in area
III are given the prefix A5H. The area III opcodes are thus A506H–A5FFH.
Figure 4-8 shows the opcode map for source mode. Areas II and III have switched places (compare with Figure 4-7). I n sou rce m ode, opcodes f or instr uctions in area II require the A5F escape
prefix while opcodes for instructions in area III (MCS 251 architecture) do not.
T o illu strate the dif ference between the bin ary-mode and source-mo de opcodes, Table 4-4 shows
the opcode assignments for three sample instructions.
Table 4-4. Examples of Opcodes in Binary and Source Modes
Instruction
Binary Mode Source Mode
DEC A 14H 14H
SUBB A,R4 9CH A59CH
SUB R4,R4 A59CH 9CH
Opcode
4.6.1 Selecting Binary Mode or Source Mode
If you have code that was written for an MCS 51 microcontroller and you want to run it unmodified on an MCS 251 microcontroller, choose binary mode. You can use the object code without
reassembling the source code. You can also assemble the source code with an assembler for the
MCS 251 architecture and have it produce object code that is binary-compatible with MCS 51
microcontrollers. The remainder of this section discusses the selection of binary mode or source
mode for code that may contain instructions from both architectures.
An instruction with a prefixed o pcode requires on e more byte for code stor age, and if an additional fetch is required for the extra byte , the execution time is increased by one state. This means that
using fewer prefixed opcodes produces more efficient code.
If a program uses only instructions from the MCS 51 architecture, the binary-mode code is more
efficient because it uses no prefixes. On the other hand , if a program uses many more new instructions than instructions from the MCS 51 architecture, source mode is likely to produce more efficient code. For a program where the choice is not clear, the better mode can be found by
experimenting with a simulator.
4-14
0H 5H FH6H
0H
DEVICE CONFIGURATION
A5H Prefix
6H FH
0H
I II
FH
®
MCS
51
Architecture
0H 5H FH6H
0H
I III
FH
FH
MCS 51
Architecture
Figure 4-7. Binary Mode Opcode Map
6H FH
0H
FH
III
MCS 251
Architecture
A4131-01
A5H Prefix
II
®
MCS
51
Architecture
MCS 251
Architecture
Figure 4-8. Source Mode Opcode Map
MCS 51
Architecture
A4130-01
4-15
8XC251SA, SB, SP, SQ USER’S MANUAL
4.7 MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#)
For devices with 16 Kbytes of on-chip code memory (87C251SB, SQ and 83C251SB, SQ), the
EMAP# bit (UCONFIG1.0) provides the option of accessing the upper half of on-chip code memory as data memory. This allows code constants to be accessed as data in region 00: using direct
addressing. See section 3.2.2.1, “Accessing On-ch ip Co de Memory in Region 00:,” for the exact
conditions required for this mapping to be effective.
EMAP# = 0. For 87C251SB/83C251SB and 87C251SQ/83C251SQ, the upper 8 Kbytes of onchip code memory (FF:2000–FF:3FFFH) are mapped to locations 00:E000H–00:FFFFH.
EMAP# = 1. Mapping of on-chip code memory to region 00: does not occur. Addresses in the
range 00:E000H–00:FFFFH access external RAM.
4.8 INTERRUPT MODE (INTR)
The INTR bit (UCONFIG1.4) determines what bytes are stored on the stack when an interrupt
occurs and how the RETI (Return from Interrupt) instruction restores operation.
For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the following
order: PC.7:0, PC.15:8. The RETI instruction pops these two bytes in the reverse order and uses
them as the 16-bit return address in region FF:.
For INTR = 1, an interrupt pushes the three PC bytes and the PSW1 register onto the stack in the
following order: PSW1, PC.23:16, PC.7:0, PC.15:8. The RETI instruction pops these four bytes
and then returns to the specified 24-bit address, which can be anywhere in the 16-Mbyte address
space.
4-16
Programming
5
CHAPTER 5
PROGRAMMING
The instruction set for the MCS® 251 architecture is a superset of the instruction set for the
®
51 architecture. This chapter describes the addressing modes and summarizes the instruc-
MCS
tion set, which is divided into data instru ctions, b it in stru ctions, and control instructions. Appendix A, “Instruction Set Reference,” contains an opcode map and a detailed description of each
instruction. The program status words PSW and PSW1 are also described.
NOTE
The instruction execution times given in Appendix A are for code executing
from on-chip code memory and for data that is read from and written to onchip RAM. Execution times are increased by executing code from external
memory, accessing peripher al SFRs, accessing data in external memory, using
real time wait states, using RD#/WR#/PSEN# preprogrammed wait states, or
extending the ALE pulse.
For some instructions, accessing the port SFRs (Px, x = 3:0) increases the
execution time. These cases are noted individually in the tables in Appendix A.
5.1 SOURCE MODE OR BINARY MODE OPCODES
Source mode and Binary mode refer to the two ways of assigning opcodes to the instruction set
of the MCS 251 architecture. Depending on the application, one mode or the other may produce
more efficient code. The mode is established during device reset based on the value of the SRC
bit in configuration byte UCONFIG0. For information regarding the selection of the opcode
mode, see section 4.6, “Opcode Configurations (SRC).”
5.2 PROGRAMMING FEATURES OF THE MCS
The instruction set for MCS 251 microcontrollers provides the user with new instru ctions that exploit the features of the architecture while maintaining compatibility with the instruction set for
MCS 51 microcontrollers. Many of the new instructions operate on 8-bit, 16-bit, or 32-bit operands. (In comparison with 8-bit and 16-bit operands, 32-b it operands are accessed with fewer addressing modes.) This capability increas es the ease and efficiency of programming MCS 251
microcontrollers in a high-level language such as C.
The instruction set is divided into data (refer to section 5.3, “Data Instructions”), bits (see section
5.4, “Bit Instructions”), and control instructions (see section 5.5, “Control Instructions”). Data instructions process 8-bit, 16-bit, and 32-bit data; bit instructions manipulate bits; and control instructions manage program flow.
®
251 ARCHITECTURE
5-1
8XC251SA, SB, SP, SQ USER’S MANUAL
5.2.1 Data Types
Table 5-1 lists the data types that are addressed by the instruction set. Words or dwords (double
words) can be in stored mem ory s tar tin g at any byte address; alignment on two-byte or four - byte
boundaries is not required. Words and dwords are stored in memory and the register file in big
endien form.
Table 5-1. Data Ty pes
Data Type Number of Bits
Bit 1
Byte 8
Word 16
Dword (Double Word) 32
5.2.1.1 Order of Byte Storage for Words and Double Words
MCS 251 microcontrollers store words (2 bytes ) and double words (4 bytes) in memory and in
the register file in big endien form. In memory storage, the most significant byte (MSB) of the
word or double word is stored in the memory byte specified in the instruction; the remaining bytes
are stored at higher addresses, with the least significant byte (LSB) at the highest address. Words
and double words can be stored in memory starting at any byte address. In the register file, the
MSB is stored in the lowest byte of the register specified in the instruction. For a description of
the register file, see section 3.3, “8XC251SA, SB, SP, SQ Register File.” The code fragment in
Figure 5-1 illustrates the storage of words and double words in big endien form.
5.2.2 Register Notation
In register-addressing instructions, specific indices denote the registers that can be used in that
instruction. For example, the instruction ADD A,Rn uses “Rn” to denote any one of R0, R1, ...,
R7; i.e., the range of n is 0–7. The instruction ADD Rm,#data uses “Rm” to denote R0, R1, ...,
R15; i.e., the range of m is 0–15. Table 5-2 summarizes the notation used for the register indices.
When an instruction contain s two registers of the same ty pe (e.g., MOV Rmd,Rms) th e first index
“d” denotes “destination” and the second index “s” denotes “source.”
5.2.3 Address Notation
In the MCS 251 architecture, memory addresses include a region number (00:, 01:, ..., FF:) (Figure 3-4 on page 3-6). SFR addresses have a prefix “S:” (S:000H–S:1FFH). The distinction between memory addresses and SFR addresses is necessary because memory locations 00:0000H–
00:01FFH and SFR locations S:000H–S:1FFH can both be directly addressed in an instruction.
5-2
Memory
201H
200H
A3H
Register File
0
A3H
B6H
PROGRAMMING
203H
202H
B6H
1
3
2
00H 00H
5
4
MOV WR0,#A3B6H
MOV 00:0201H,WR0
MOV DR4,#0000C4D7H
7
6
D7H
C4H
WR0
Contents of register file and memory after execution
DR4
A4242-01
Figure 5-1. Word and Double-word Storage in Big Endien Form
Table 5-2. Notation for Byte Registers, Word Registers, and Dword Registers
Register
Type
Byte
Word WRj WRjd WRjs WR0, WR2, WR4, ..., WR30
Dword DRk DRkd DRks DR0, DR4, DR8, ..., DR28, DR56, DR60
Register
Symbol
Ri — — R0, R1
Rn — — R0–R7
Rm Rmd Rms R0–R15
Destination
Register
Source
Register
Register Range
Instructions in the MCS 51 architecture use 80H–FFH as addresses for both memory locations
and SFRs, because memory locations are addressed only indirectly and S FR locations are addressed only directly. For compatibility, software tools for MCS 251 controllers recognize this
notation for instructions in the MCS 51 architecture. No change is necessary in any code written
for MCS 51 controllers.
For new instructions in the MCS 251 architecture, the memory region prefixes (00:, 01, ..., FF:)
and the SFR prefix (S:) are required. Also, software tools for the MCS 251 architecture permit
00: to be used for memory addresses 00H–FFH and permit the prefix S: to be used for SFR addresses in instructions in the MCS 51 architecture.
5-3
8XC251SA, SB, SP, SQ USER’S MANUAL
5.2.4 Addressing Modes
The MCS 251 architecture supports the following addressing modes:
• register addressing: The instruction specifies the register that contains the operand.
• immediate addressing: The instruction contains the operand.
• direct addressing: The instruction contains the operand address.
• indirect addressing: The instruction specifies the register that contains the operand address.
• displacement addressing: The instruction specifies a register and an offset. The operand
address is the sum of the register contents (the base address) and the offset.
• relative addres sing: The instruction contains the signed offset from the next instruction to
the target address (the address for transfer of control, e.g., the jump address).
• bit addressing: The instruction contains the bit address.
More detailed descriptions of the addressing modes are given in sections 5.3.1, “Data Addressing
Modes," 5.4.1, “Bit Addressing," and 5.5.1, “Addressing Modes for Control Instructions.”
5.3 DATA INSTRUCTIONS
Data instructions consist of arithmetic, logical, and data-transfer instructions for 8-bit, 16-bit, and
32-bit data. This section describes the data addressing modes and the set of data instructions.
5.3.1 Data Addressing Modes
This section describes the data-addressing modes, which are summar ized in two tables: Table 5-3
for the instructions that are native to the MCS 51 architecture, and Table 5-4 for the new data instructions in the MCS 251 architecture.
NOTE
References to registers R0–R7, WR0–WR6, DR0, and DR2 always refer to the
register bank that is currently selected by the PSW and PSW1 registers (see
section 5.6, “Program Status Words”). Registers in all banks (active and
inactive) can be accessed as memory locations in the range 00H–1FH.
Instructions from the MCS 51 architecture access external memory through the
region of memory specified by byte DPXL in the extended data pointer
register, DPX (DR56). Following reset, DPXL contains 01H, which maps the
external memory to region 01:. You can specify a different region by writing to
DR56 or the DPXL SFR. See section 3.3.2, “Dedicated Registers.”
5-4
PROGRAMMING
5.3.1.1 Register Addressing
Both architectures address registers directly.
• MCS 251 architecture. In the register addressing mode, the operand(s) in a data instructi on
are in byte registers (R0–R15), word registers (WR0, WR2, ..., WR30), or dword registers
(DR0, DR4, ..., DR28, DR56, DR60).
• MCS 51 architecture. Instructions address registers R0–R7 only.
5.3.1.2 Immediate
Both architectures use immediate addressing.
• MCS 251 architecture. In the immediate addressing mode, the instruction contains the data
operand itself. Byte operations use 8-bit immediate data (#data); word operations use 16-bit
immediate data (#data16). Dword operations use 16-bit immediate data in the lower word,
and either zeros in the upper word (denoted by #0data16), or ones in the upper word
(denoted by #1data16). MOV instructions that place 16-bit immediate data into a dword
register (DRk), place the data either into the upper word while leaving the lower word
unchanged, or into the l ower word with a sign extension or a zero extension.
The increment and decrement instructions contain immediate data (#short = 1, 2, or 4) that
specifies the amount of the increment/decrement.
• MCS 51 architecture. Instructions use only 8-bit immediate data (#data).
5.3.1.3 Direct
• MCS 251 architecture. In the direct addressing mo de, the in stru ctio n contains the address of
the data operand. The 8-bit direct mode addresses on-chip RAM (dir8 = 00:0000H–
00:007FH) as both bytes and words, and addresses the SFRs (dir8 = S:080H–S:1FFH) as
bytes only. (See the notes in section 5.3.1, “Data Addressing Modes,” reg ardin g SF Rs in the
MCS 251 architecture.) The 16-bit direct mode addresses b oth bytes and words in memory
(dir16 = 00:0000H–00:FFFFH).
• MCS 51 architecture. The 8-bit direct mode addresses 256 bytes of on-chip RAM ( dir8 =
00H–7FH) as bytes only and the SFRs (dir8 = 80H–FFH) as bytes only.
5-5
8XC251SA, SB, SP, SQ USER’S MANUAL
Table 5-3. Addressing Modes for Data Instructions in the MCS® 51 Architecture
Mode
Register 00H
Immediate Operand in Instruction #data = #00H
Direct
Indirect
Address Range of
Operand
–1FH
00H–7FH dir8 = 00H
SFRs
00H–FFH @R0, @R1
0000H–FFFFH @DPTR, @A+DPTR
0000H–FFFFH @A+DPTR, @A+PC
Assembly Language
Reference
R0–R7
(Bank selected by PSW)
–#FFH
–7FH On-chip RAM
dir8 = 80H
–FFH
or SFR mnemonic.
Comments
SFR address
Accesses on-chip RAM or the
lowest 256 bytes of external
data memory (MOVX).
Accesses external data
memory (MOVX).
Accesses region FF: of code
memory (MOVC).
5.3.1.4 Indirect
In arithmetic and logical instructions that use indirect add ressing , the sou rce operand is always a
byte, and the destination is either the accumu lator or a byte register (R0–R15). The source add ress
is a byte, word, or dword. The two architectures do indirect addressing via different registers:
• MCS 251 architecture. Memory is indirectly addressed via word and dword registers:
— Word register (@WRj, j = 0, 2, 4, ..., 30). The 16-bit address in WRj can access
locations 00:0000H–00:FFFFH.
— Dword register (@DRk, k = 0, 4, 8, ..., 28, 56, and 60). The 24 least significant bits can
access the entire 16-Mbyte address space. The upper eight bits of DRk must be 0. If
you use DR60 as a general data pointer, be aware that DR60 is the extended stack
pointer register SPX.
• MCS 51 architecture. Instructions use indirect addressing to access on-chip RAM, code
memory, and external data RAM. See the notes in section 5.3.1, “Data Addressing Modes,”
regarding the region of external data RAM that is addressed by instructions in the MCS 51
architecture.
— Byte register (@Ri, i = 1, 2). Registers R0 and R1 indirectly address on-chip memory
locations 00H–FFH and the lowest 256 bytes of external data RAM.
— 16-bit data pointer (@DPTR or @A+DPTR). The MOVC and MOVX instructions use
these indirect modes to access code memory and external data RAM.
— 16-bit program counter (@A+PC). The MOVC instruction uses this indirect mode to
access code memory.
5-6
PROGRAMMING
Table 5-4. Addressing Modes for Data Instructions in the MCS® 251 Architecture
Mode
Register
Immediate,
2 bits
Immediate,
8 bits
Immediate,
16 bits
Direct,
8 address bits
Direct,
16 address bits
Indirect,
16 address bits
Indirect,
24 address bits
Displacement,
16 address bits
Displacement,
24 address bits
NOTES:
1. T hese registers are accessible in the memory space as w ell as in the register file (see section 3.3,
“8XC251SA, SB, SP, SQ Register File.”
2. T he MCS 251 architecture suppo rts SFRs in locations S:000H–S:1F FH; however, in the 8XC251S
all SFRs are in the range S:080H–S:0FFH.
Address Range of
Operand
00:0000H
(R0–R7, WR0–WR3,
DR0, DR2) (1)
N.A. (Operand is in the
N.A. (Operand is in the
N.A. (Operand is in the
00:0000H–00:007FH dir8 = 00:0000H–00:007FH On-chip RAM
SFRs
00:0000H–00:FFFFH dir16 = 00:0000H–00: FFF FH
00:0000H–00:FFFFH @WR0–@WR30
00:0000H–FF:FFFFH
00:0000H–00:FFFFH
00:0000H
–00:001FH
instruction)
instruction)
instruction)
–FF:FFFFH
Assembly Language
Notation
R0
–R15, WR0–WR30,
DR0
–DR28, DR56, DR60
#short = 1, 2, or 4
#data8 = #00H–#FFH
#data16 = #0000H
dir8 = S:080H
or SFR mnemonic
@DR0–@DR30, @DR56,
@DR60
@WRj + dis16 =
@WR0 + 0H through
@WR30 + FFFFH
@DRk + dis24 =
@DR0 + 0H through
@DR28 + FFFFH,
@DR56 + (0H–FFFFH),
@DR60 + (0H–FFFFH)
–#FFFFH
–S:1FFH (2)
Comments
R0
–R7, WR0–WR6, DR0, and
DR2 are in the register bank
currently selected by the
PSW and PSW1.
Used only in increment and
decrement instructions.
SFR address
Upper 8 bits of DRk must be
00H.
Offset is signed; address
wraps around in region 00:.
Offset is signed, upper 8 bits
of DRk must be 00H.
x
,
5-7
8XC251SA, SB, SP, SQ USER’S MANUAL
5.3.1.5 Displacement
Several move instructions use displacement addressing to move bytes or words from a source to
a destination. Sixteen-bit displacement addressing (@WRj+dis16) accesses indirectly the lowest
64 Kbytes in memory . The base add ress can be in any word reg ister WRj. The instruction con tains
a 16-bit signed offset which is added to the base address. Only the lowest 16 bits of the sum are
used to compute the oper and address. I f the sum o f the base add ress and a po sitive of fset exceed s
FFFFH, the computed address wraps around within region 00: (e.g. F000H + 2005H becomes
1005H). Similarly, if the sum of the base address and a negative offset is less than zero, the computed address wraps around the top of region 00: (e.g., 2005H + F000H becomes 1005H).
T wenty-four -bit displacement addressing (@DRk+dis24) accesses indirectly the entire 16-Mbyte
address space. The base address must be in DR0, DR4, ..., DR24, DR28, DR56, or DR60. The
upper byte in the dword register must be zero. The instruction contains a 16-bit signed offset
which is added to the base address.
5.3.2 Arithmetic Instructions
The set of arithmetic instructions is greatly exp anded in the MCS 25 1 architecture. The ADD and
SUB instructions (Table A-19 on page A-14) operate on byte and word data that is accessed in
several ways:
• as the contents of the accumulator, a byte register (Rn), or a word register (WRj)
• in the instruction itself (immediate data)
• in memory via direct or indirect addressing
The ADDC and SUBB instructions (Table A-19) are the same as those f or MCS 51 microcon trollers.
The CMP (compare) instruction (Table A-20 on page A-15) calculates the dif ference of two bytes
or words and then writes to flags CY, OV, AC, N, and Z in the PSW and PSW1 registers. The
difference is not stored. The op erand s can b e add ressed in a variety of modes. The most frequent
use of CMP is to compare data or addresses preceding a conditional jump instruction.
Table A-21 on page A-16 lists the INC (increment) and DEC (decrement) instructions. The instructions for MCS 51 microcontrollers are supplemented by instructions that can address byte,
word, and dword registers and increment or decrement them by 1, 2, or 4 (denoted by #short).
These instructions are supplied primarily for register-based address pointers and loop counters.
5-8
PROGRAMMING
The MCS 251 architecture provides the MUL (multiply) and DIV (divide) instructions for unsigned 8-bit and 16-bit data (Table A-22 on page A-16). Signed multiply and divide are left for
the user to manage through a conversion process. The following operations are implemented:
• eight-bit multiplication: 8 bits × 8 bits → 16 bits
• sixteen-bit multiplication: 16 bits × 16 bits → 32 bits
• eight-bit division: 8 bits
÷
8 bits → 16 bits (8-bit quotient, 8-bit remainder)
• sixteen-bit division: 16 bits ÷ 16 bits → 32 bits (16-bit quotient, 16-bit remainder)
These instructions operate on pairs of byte registers (Rmd,Rms), word registers (WRjd,WRjs), or
the accumulator and B reg ister (A,B). Fo r 8-bit register multiplies, the result is stored in the wo rd
register that contains the first operand register. For example, the product from an instruction
MUL R3,R8 is s tored in WR2. Similarly, for 16-bit multiplies, the result is stored in the dwor d
register that contains the first operand register. For example, the product from the instruction
MULWR6,WR18 is stored in DR4.
For 8-bit divides, the operands are byte registers. The result is stored in the word register that contains the first operand register . The quotient is stored in the lower b yte, and the remainder is stored
in the higher byte. A 16-b it divide is similar. The first operand is a word register , and th e result is
stored in the double word register that contains that word register. If the second operand (the divisor) is zero, the overflow flag (OV) is set and the other bits in PSW and PSW1 are meaningless.
5.3.3 Logical Instructions
The MCS 251 architecture provides a set of instructions that perform logical operations. The
ANL, ORL, and XRL (logical AND, logical OR, and logical exclusive OR) instructions operate
on bytes and words that are accessed via several addressing modes (Table A-23 on page A-17).
A byte register, word register, o r the accumulator can be logically combined with a register, immediate data, or data that is addressed directly or indirectly . These instructions af fect the Z and N
flags.
In addition to the CLR (clear), C PL (complement), SWAP (swap), and four rotate instructions that
operate on the accumulator, MCS 251 microcontrollers have three shift commands for byte and
word registers:
• SLL (Shift Left Logical) shifts the register one bit left and replaces the LSB with 0
• SRL (Shift Right Logical) shifts the register one bit right and replaces the MSB with 0
• SRA (Shift Right Arithmetic) shifts the register one bit right; the MSB is unchanged
5-9
8XC251SA, SB, SP, SQ USER’S MANUAL
5.3.4 Data Transfer Ins tructions
Data transfer instructions copy data from one register or memory location to another. These instructions include the move instruction s ( Table A-24 on page A-19) an d th e exchange, push, and
pop instructions (Table A-25 on page A-22). Instructions that move only a single bit are listed
with the other bit instructions in Table A-26 on page A-23.
MOV (Move) is the most versatile instruction, and its addressing modes are expanded in the
MCS 251 architecture. MOV can transfer a byte, word, or dword between any two registers or
between a register and any location in the address space.
The MOVX (Move External) in structio n moves a b yte from ex ternal m emory to th e accum ulator
or from the accumulator to memory. The external memory is in the region specified by DPXL,
whose reset value is 01H. See section 3.3.2, “Dedicated Registers.”
The MOVC (Move Code) instruction moves a byte from code memory (regi on FF:) to the accumulator.
MOVS (Move with Sign Extension) and MOVZ (Move with Zero Extension) move the contents
of an 8-bit register to the lower byte of a 16-bit register. The upper byte is filled with the sign bit
(MOVS) or zeros (MOVZ). The MOVH (Move to High Word) instruction places 16-bit im mediate data into the high word of a dword register.
The XCH (Exchange) instruction interchanges the contents of the accumulator with a register or
memory location. The XCHD (Exchange D igit) instruction interchanges the lower nibble of the
accumulator with the lower nibble of a byte in on-chip RAM. XCHD is useful for BCD (binary
coded decimal) operations.
The PUSH and POP instructions facilitate storing information (PUSH) and then retrieving it
(POP) in reverse order . Push can push a byte, a word, or a dword onto the stack, using the immediate, direct, or register addressing modes. POP can pop a byte or a word from the stack to a register or to memory.
5-10
PROGRAMMING
5.4 BIT INSTRUCTIONS
A bit instruction addresses a specific bit in a memory location or SFR. There are four categories
of bit instructions:
• SETB (Set Bit), CLR (Clear Bit), CPL (Complement Bit). These instructions can set, clear
or complement any addressable bit.
• ANL (And Logical), ANL/ (And Logical Complement), ORL (OR Logical), ORL/ (Or
Logical Complement). These instructions allow ANDing and ORing of any addressable bit
or its complement with the CY flag.
• MOV (Move) instructions transfer any addressable bit to the carry (CY) bit or vice versa.
• Bit-conditional jump instructions execute a jump if the bit has a specified state. The bit-
conditional jump instructions are classified with the control instructions and are described
in section 5.5.2, “Conditional Jumps.”
5.4.1 Bit Addressing
The bits that can be individually add ressed are in the on-ch ip RAM and the S FRs (T able 5- 5). The
bit instructions that are unique to the MCS 251 architecture can ad dress a wider ran ge of bits than
the instructions from the MCS 51 architecture.
There are some differen ces in the way the instructions from the two architectu res address bits. In
the MCS 51 architecture, a bit (denoted by bit51) can be specified in terms of its location within
a certain register, or it can be specified by a bit address in the range 00H–7FH. The MCS 251
architecture does not have bit addresses as such. A bit can be addressed by name or by its location
within a certain register, but not by a bit address.
Table 5-6 illustrates bit addressing in the two architectures by using two sample bits:
• RAMBIT is bit 5 in RAMREG, which is location 23H. “RAMBIT” and “RAMREG” are
assumed to be defined in user code.
• IT1 is bit 2 in TCON, which is an SFR at location 88H.
Table 5-5. Bit-addressable Locations
Architecture
®
251 Architecture 20H–7FH All defined SFRs
MCS
MCS 51 Architecture 20H–2FH
On-chip RAM SFRs
Bit-addressable Locations
SFRs with addresses ending in 0H or 8H:
80H, 88H, 90H, 98H, ..., F8H
5-11
8XC251SA, SB, SP, SQ USER’S MANUAL
T able 5-7 lists the addressing modes for bit instru ctions and T able A-26 on page A-2 3 summarizes
the bit instructions. “Bit” denotes a bit that is addressed by a new instruction in the MCS 251 architecture and “bit51” deno tes a bit that is addressed by an instru ction in the MCS 51 architecture.
Table 5-6. Addressing Two Sample Bits
Location
On-chip RAM
SFR
Addressing
Mode
Register Name RAMREG .5 RAMREG.5
Register Address 23H.5 23H.5
Bit Name RAMBIT RAMBIT
Bit Address 1DH NA
Register Name TCON.2 TCON.2
Register Address 88.2H S:88.2H
Bit Name IT1 IT1
Bit Address 8A NA
®
MCS
51
Architecture
MCS 251
Architecture
Table 5-7. Addressing Modes for Bit Instructions
Architecture Variants Bit Address Memo ry/ SFR Address Comments
®
MCS
251
Architecture
(bit)
MCS 51
Architecture
(bit51)
Memory NA 20H.0
SFR NA All defined SFRs
Memory 00H–7FH 20H.0
SFR 80H–F8H
–7FH.7
–7FH.7
XXH.0–XXH.7, where XX = 80,
88, 90, 98, ..., F0, F8.
SFRs are not defined
at all bit-addressable
locations.
5.5 CONTROL INSTRUCTIONS
Control instructions—instructions that change program flow—include calls, returns, and conditional and unconditional jumps (see Table A-27 on page A-24). Instead of executing the next instruction in the queue, the processor ex ecutes a target instruction. The control instruction pr ovides
the address of a target instruction either implicitly, as in a return from a subroutine, or explicitly,
in the form of a relative, direct, or indirect address.
MCS 251 microcontrollers hav e a 24-b it prog ram counter (PC), wh ich allows a target instruction
to be anywhere in the 16-Mbyte address space. However , as discussed in this section, some control instructions restrict the target addres s to the current 2-Kbyte or 64-Kbyte address range by
allowing only the lowest 11 or lowest 16 bits of the program counter to change.
5-12
PROGRAMMING
5.5.1 Addressing Modes for Control Instructions
Table 5-8 lists the addressing modes for the control instructions.
• Relative addressing: The control instruction provides the target address as an 8-bit signed
offset (rel) from the address of the next instruction.
• Direct addressing: The control instruction prov ides a tar get address, which can have 11 bits
(addr11), 16 bits (ad dr16), or 24 bits (addr24). The target address is written to the PC.
— addr1 1: Only the lo wer 11 bits of the PC are changed; i.e., the tar get add ress must be in
the current 2-Kbyte block (the 2-Kbyte block that includes the first byte of the next
instruction).
— addr16: Only the lower 16 bits of th e PC are chan ged; i.e., the tar g et addr e ss must be in
the current 64-Kbyte region (the 6 4-Kby te r egion that in cludes the first byte of th e next
instruction).
— addr24: The target address can be anywhere in the 16-Mbyte address space.
• Indirect addressing: There are two types of indirect addressing for control instructions:
— For the instructions LCALL @WRj and LJMP @WRj, the target address is in the
current 64-Kbyte region. The 16- bit address in WRj is placed in the lower 16 bits of the
PC. The upper eight bits of the PC remain unchanged from the address of the next
instruction.
— For the instruction JMP @A+DP TR, the sum of the accumulator an d DPTR is placed in
the lower 16 bits of the PC, and the upper eight bits of the PC are FF:, which restricts
the target address to the code memory space of the MCS 51 architecture.
Table 5-8. Addressing Modes for Control Instructions
Description
Relative, 8-bit relative address (rel) 8 -128 to +127 from first byte of next instruction
Direct, 11-bit t arget addres s (addr11) 11 Current 2 Kbytes
Direct, 16-bit target address (addr16) 16 Current 64 Kbytes
Direct, 24-bit target address (addr24)
Indirect (@WRj)
Indirect (@A+DPTR) 16
†
These modes are not used by instructions in the MCS® 51 architecture.
†
Address Bits
Provided
†
24 00: 0000H–FF:FFFFH
16 Curre nt 64 Kbytes
64-Kbyte region specified by DPXL (reset
value = 01H)
Address Range
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8XC251SA, SB, SP, SQ USER’S MANUAL
5.5.2 Conditional Jumps
The MCS 251 architecture supports bit-conditional jumps, compare-conditional jumps, and
jumps based on the value of the accumu lator . A bit-cond itional jump is ba sed on the state of a bit.
In a compare-conditional jump, the jump is based on a comparison of two operands. All conditional jumps are relative, and the target address (rel) must be in the current 256-byte block of
code. The instruction set includes three kinds of bit-conditional jumps:
• JB (Jump on Bit): Jump if the bit is set.
• JNB (Jump on Not Bit): Jump if the bit is clear.
• JBC (Jump on Bit then Clear it): Jump if the bit is set; then clear it.
Section 5.4.1, “Bit Addressing,” describes the bit addressing used in these instructions.
Compare-conditional jumps test a condition resulting from a compare (CMP) instruction that is
assumed to precede the jump instruction. The jump instruction examines the PSW and PSW1 registers and interprets their flags as though they wer e set or cleared by a comp are (CMP) instruction.
Actually, the state of each flag is determined by the last instruction that could have affected that
flag.
The condition flags are used to test one of the following six relations between the operands:
• equal (=), not equal (≠)
• greater than (>), less than (<)
• greater than or equal (≥), less than or equal (≤)
For each relation there are two instructions, one for signed operands and one for unsigned operands (Table 5-9).
Table 5-9. Compare-conditional Jump Instructions
Operand
Type
Unsigned
Signed JSG JSL JSGE JSLE
5-14
=≠><≥≤
JE JNE
Relation
JG JL JGE JLE
PROGRAMMING
5.5.3 Unconditional Jumps
There are five unconditional jumps. NOP and SJMP jump to addresses relative to the program
counter. AJMP, LJMP, and EJMP jump to direct or indirect addresses.
• NOP (No Operation) is an unconditional jump to the next instruction.
• SJMP (Short Jump) jumps to any instruction within -128 to 127 of the next instruction.
• AJMP (Absolute Jump) changes the lowest 11 bits of the PC to jump anywhere within the
current 2-Kbyte block of memory. The address can be direct or indirect.
• LJMP (Long Jump) changes the lowest 16 bits of the PC to jump anywhere within the
current 64-Kbyte region.
• EJMP (Extended Jump) changes all 24 bits of the PC to jump anywhere in the 16-Mbyte
address space. The address can be direct or indirect.
5.5.4 Calls and Returns
The MCS 251 architecture provides relative, direct, and indirect calls and returns.
ACALL (Absolute Call) pushes the lower 16 bits of the next instruction address onto the stack
and then changes the lower 11 bits of the PC to the 11-bit address specified by the instruction.
The call is to an address that is in the same 2-Kbyte block of memory as the address of the next
instruction.
LCALL (Long Call) pushes the lower 16 bits of the next-instruction address onto the stack and
then changes the lower 16 bits of the PC to the 16-bit address specified by the instruction. The
call is to an address in the sam e 64-Kby te bloc k of memory as the address of the next in stru ction.
ECALL (Extended Call) pushes the 24 bits of the next instruction address onto th e stack and then
changes the 24 bits of the PC to the 24-bit address specified by the instruction. The call is to an
address anywhere in the 16-Mbyte memory space.
RET (Return) pops the top two bytes from the stack to return to the instruction following a subroutine call. The return address must be in the same 64-Kbyte region.
ERET (Extended Return) pops the top three bytes from the stack to return to the address following a subroutine call. The return address can be anywhere in the 16-Mbyte address space.
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8XC251SA, SB, SP, SQ USER’S MANUAL
RETI (Return from Interrupt) provides a return from an interrupt service routine. The operation
of RETI depends on the INTR bit in the UCONFIG1 or CONFIG1 configuration byte:
• For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the
following order: PC.7:0, PC.15:8. The RETI instruction pops these two bytes and uses them
as the 16-bit return address in region FF:. RETI also restores the interrupt logic to accept
additional interrupts at the same priority level as the one just processed.
• For INTR = 1, an interrupt pushes the three PC bytes and PSW1 onto the stack in the
following order: PSW1, PC.23:16, PC.7:0, PC.15:8. The RETI instruction pops these four
bytes and then returns to the specified 24-bit address, which can be anywhere in the 16Mbyte address space. RETI also clears the interrupt request line. (See the note in Ta ble 5-8
regarding compatibility with code written for MCS 51 microcontrollers.)
The TRAP instruction is useful for the development of emulations of an MCS 251 microcon troller .
5.6 PROGRAM STATUS WORDS
The Program Status W ord (PSW) re gister and the Program Status Word 1 (PSW1) register contain
four types of bits (Figures 5-2 and 5-3):
• CY, AC, OV, N, and Z are flags set by hardware to indicate the result of an operation.
• The P bit indicates the parity of the accumulator.
• Bits RS0 and RS1 are programmed by software to select the active register bank for
registers R0–R7.
• F0 and UD are available to the user as general-purpose flags.
The PSW and PSW1 registers are read/write registers; however, the parity bit in the PSW is not
affected by a write. Individual bits can be addressed with the bit instructions (section 5.4, “Bit
Instructions”). The PSW and PSW1 bits are used implicitly in the conditional jump instructions
(section 5.5.2, “Conditional Jumps”).
The PSW register is identical to the PSW register in MCS 51 microcontrollers. The PSW1 register exists only in MCS 251 microcontrollers. Bits CY, AC, RS0, RS1, and OV in PSW1 are identical to the corresponding bits in PSW; i.e., the same bit can be accessed in either register. Table
5-10 lists the instructions that affect the CY, AC, OV, N, and Z bits.
5-16
PROGRAMMING
Table 5-10. The Effects of Instructions on the PSW and PSW1 Flags
Instruction Type Instruction
ADD, ADDC, SUB,
SUBB, CMP
Arithmetic
Logical
Program Control
NOTES:
1. X = the flag can be affected by the instruction.
0 = the flag is cleared by the instruction.
2. The AC flag is affected only by operations on 8-bit operands.
3. If the divisor is zero, the OV flag is set and the other bits are meaningless.
4. F or SR L, SLL, and SRA instruc tions, the last bit shifted out is stored in the CY bit.
5. T he parity bit (PSW.0) is set or cleared by instructions that change the contents of the
accumulator (ACC, Register R11).
INC, DEC X X
MUL, DIV (3) 0 X X X
DA X X X
ANL, ORL, XRL, CLR A,
CPL A, RL, RR, SWAP
RLC, RRC, SRL, SLL,
SRA (4)
CJNE X X X
DJNE X X
Flags Affected (1), (5)
CY OV AC (2) N Z
XXXXX
XX
XXX
5-17
8XC251SA, SB, SP, SQ USER’S MANUAL
.
PSW
Address: S:D0H
Reset State: 0000 0000B
7 0
CY AC F0 RS1 RS0 OV UD P
Bit
Number
Bit
Mnemonic
Function
7 CY Carry Flag:
The carry flag is set by an addition instruction (ADD, ADDC) if there is a
carry out of the MSB. It is set by a subtraction (SUB, SUBB) or compare
(CMP) if a borrow is needed for the MSB. The carry flag is also affected
by some rotate and shift instructions, logical bit instructions, bit move
instructions, and the multiply (MUL) and decimal adjust (DA) instructions
(see Table 5-10).
6 A C Auxiliary Carry Flag:
The auxiliary carry flag is affected only by instructions that address 8-bit
operands. The AC flag is set if an arithmetic instruction with an 8-bit
operand produces a carry out of bit 3 (from addition) or a borrow into bit
3 (from subtraction). Otherwise, it is cleared. This flag is useful for BCD
arithmetic (see Table 5-10).
5 F0 Flag 0:
This general-purpose flag is available to the user.
4:3 RS1:0 Register Bank Select Bits 1 and 0:
These bits select the memory locations that comprise the active bank of
the register file (registers R0–R7).
RS1 RS0 Bank Address
0 0 0 00H–07H
0 1 1 08H–0FH
1 0 2 10H–17H
1 1 3 18H–1FH
2 OV Overflow F lag:
This bit is set if an addition or subtraction of signed variables results in
an overflow error (i.e., if the magnitude of the sum or difference is too
great for the seven LSBs in 2’s-complement representation). The
overflow flag is also set if a multiplication product overflows one byte or if
a division by zero is attempted.
1 UD User-definable Flag:
This general-purpose flag is available to the user.
0 P Par it y Bit :
This bit indicates the parity of the accumulator. It is set if an odd number
of bits in the accumulator are set. Otherwise, it is cleared. Not all instructions update the parity bit. The parity bit is set or cleared by instructions
that change the contents of the accumulator (ACC, Register R11).
5-18
Figure 5-2. Program Status Word Register
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