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Intel 8XC251SQ, 8XC251SB, 8XC251SP, 8XC251SA User Manual 2

8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ Embedded Microcontroller Users Manual
8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ
Embedded Microcontroller
User’s Manual
May 1996 Order Number 272795-002
Information in this docu men t is pro vided in con nection with Intel products. Intel assumes no liability whatsoe ver, including in­fringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Intel retains the right to make changes to these specifications at any time, with ou t not ice. M icroco ntroller products may have minor variations to this specification known as errata.
*Other brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. Copies of documents which have an orderin g number and ar e refere nced in this docum ent, or other Intel literat ure, may be
obtained from:
Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
COPYRIGHT © INTEL CORPORATION, 1996

CONTENTS

CHAPTER 1
GUIDE TO THIS MANUAL
1.1 MANUAL CONTENTS................................................................................................... 1-1
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY................................................ 1-3
1.3 RELATED DOCUMENTS.............................................................................................. 1-5
1.3.1 Data Sheet ................................................................................................................1-6
1.3.2 Application Notes ......................................................................................................1-6
1.4 APPLICATION SUPPORT SERVICES.......................................................................... 1-7
1.4.1 World Wide Web .......................................................................................................1-7
1.4.2 CompuServe Forums ................................................................................................1-7
1.4.3 FaxBack Service .......................................................................................................1-8
1.4.4 Bulletin Board System (BBS) ....................................................................................1-8
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1 8XC251SA, SB, SP, SQ ARCHITECTURE................................................................... 2-3
2.2 MCS 251 MICROCONTROLLER CORE....................................................................... 2-4
2.2.1 CPU ..........................................................................................................................2-5
2.2.2 Clock and Reset Unit ................................................................................................2-6
2.2.3 Interrupt Handler ........................................................................... ..... ...... ...... ...........2-7
2.2.4 On-chip Code Memory ..............................................................................................2-7
2.2.5 On-chip RAM ............................................................................................................2-7
2.3 ON-CHIP PERIPHERALS.............................................................................................. 2-7
2.3.1 Timer/Counters and Watchd og Timer .......................................................................2-7
2.3.2 Programmable Counter Array (PCA) ........................................................................2-8
2.3.3 Serial I/O Port ...........................................................................................................2-8
CHAPTER 3
ADDRESS SPACES
3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS................................... 3-1
3.1.1 Compatibility with the MCS® 51 Architecture ...........................................................3-2
3.2 8XC251SA, SB, SP, SQ MEMORY SPACE.................................................................. 3-5
3.2.1 On-chip General-purpose Data RAM ........................................................................3-8
3.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ) .............3-8
3.2.2.1 Accessing On-chip Code Memory in Region 00: ..................................................3-9
3.2.3 External Memory ......................................... ........................................................ ....3-10
3.3 8XC251SA, SB, SP, SQ REGISTER FILE.................................................................. 3-10
3.3.1 Byte, Word, and Dword Registers ...........................................................................3-13
3.3.2 Dedicated Registers ................................................................................................3-13
3.3.2.1 Accumulator and B Register ..............................................................................3-13
3.3.2.2 Extended Data Pointer, DPX ..............................................................................3-15
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8XC251SA, SB, SP, SQ USER’S MANUAL
3.3.2.3 Extended Stack Pointer, SPX ............................................................................3-15
3.4 SPECIAL FUNCTION REGISTERS (SFRS)............................................................... 3-16
CHAPTER 4
DEVICE CONFIGURATION
4.1 CONFIGURATION OVERVIEW .................................................................................... 4-1
4.2 DEVICE CONFIGURATION............................. ...... ....................................................... 4-1
4.3 THE CONFIGURATION BITS........................................................................................ 4-4
4.4 CONFIGURATION BYTE LOCATION SELECTOR (UCON)......................................... 4-5
4.5 CONFIGURING THE EXTERNAL MEMORY INTERFACE........................................... 4-8
4.5.1 Page Mode and Nonpage Mode (PAGE#) ................................................................4-8
4.5.2 Configuration Bits RD1:0 ..........................................................................................4-9
4.5.2.1 RD1:0 = 00 (18 External Address Bits) .................................... ..... .......................4-9
4.5.2.2 RD1:0 = 01 (17 External Address Bits) .................................... ..... .......................4-9
4.5.2.3 RD1:0 = 10 (16 External Address Bits) .................................... ..... .....................4-12
4.5.2.4 RD1:0 = 11 (Compatible with MCS 51 Microcontrollers) ..................... ...............4-12
4.5.3 Wait State Configuration Bits ..................................................................................4-12
4.5.3.1 Configuration Bits WSA1:0#, WSB1:# ...............................................................4-12
4.5.3.2 Configuration Bit WSB .......................................................................................4-12
4.5.3.3 Configuration Bit XALE# ....................................................................................4-13
4.6 OPCODE CONFIGURATIONS (SRC)......................................................................... 4-13
4.6.1 Selecting Binary Mode or Source Mode ..................................................................4-14
4.7 MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#)...................... 4-16
4.8 INTERRUPT MODE (INTR)......................................................................................... 4-16
CHAPTER 5
PROGRAMMING
5.1 SOURCE MODE OR BINARY MODE OPCODES........................................................ 5-1
5.2 PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE......................... 5-1
5.2.1 Data Types ................................................................................................................5-2
5.2.1.1 Order of Byte Storage for Words and Double Words ...........................................5-2
5.2.2 Register Notation ........................................ ...... ..... ...... .............................................5-2
5.2.3 Address Notation ......................................................................................................5-2
5.2.4 Addressing Mode s ................................. ........................................................ ...........5-4
5.3 DATA INSTRUCTIONS................................................................................................. 5-4
5.3.1 Data Addressing Modes ............................................................................................5-4
5.3.1.1 Register Addressing .............................................................................................5-5
5.3.1.2 Immediate ............................................................................................................5-5
5.3.1.3 Direct ....................................................................................................................5-5
5.3.1.4 Indirect .................................................................................................................5-6
5.3.1.5 Displacement .......................................................................................................5-8
5.3.2 Arithmetic Instructions ............................ ..... ...... ..... ...................................................5-8
5.3.3 Logical Instructions ...................................................................................................5-9
5.3.4 Data Transfer Instructions .......................................................................................5-10
iv
CONTENTS
5.4 BIT INSTRUCTIONS................................................................................................... 5-11
5.4.1 Bit Addressing .........................................................................................................5-11
5.5 CONTROL INSTRUCTIONS....................................................................................... 5-12
5.5.1 Addressing Modes for Control Instructions .............................................................5-13
5.5.2 Conditional Jumps .................................................................................................. 5-14
5.5.3 Unconditional Jumps ...............................................................................................5-15
5.5.4 Calls and Returns ...................................................................................................5-15
5.6 PROGRAM STATUS WORDS .................................................................................... 5-16
CHAPTER 6
INTERRUPT SYSTEM
6.1 OVERVIEW ................................................................................................................... 6-1
6.2 8XC251SA, SB, SP, SQ INTERRUPT SOURCES........................................................ 6-3
6.2.1 External Interrupts .....................................................................................................6-3
6.2.2 Timer Interrupts .........................................................................................................6-4
6.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT........................................ 6-5
6.4 SERIAL PORT INTERRUPT.......................................................................................... 6-5
6.5 INTERRUPT ENABLE................................................................................................... 6-5
6.6 INTERRUPT PRIORITIES............................................................................................. 6-7
6.7 INTERRUPT PROCESSING......................................................................................... 6-9
6.7.1 Minimum Fixed Interrupt Time ................................................................................6-10
6.7.2 Variable Interrupt Parameters .................................................................................6-10
6.7.2.1 Response Time Variables ..................................................................................6-10
6.7.2.2 Computation of Worst-case Latency With Variables ..........................................6-12
6.7.2.3 Latency Calculations ..........................................................................................6-13
6.7.2.4 Blocking Conditions ............................................................................................6-14
6.7.2.5 Interrupt Vector Cycle .................................. ..... ...... ...... .....................................6-14
6.7.3 ISRs in Process ......................................................................................................6-15
CHAPTER 7
INPUT/OUTPUT PORTS
7.1 INPUT/OUTPUT PORT OVERVIEW............................................................................. 7-1
7.2 I/O CONFIGURATIONS................... ...... ...... ............................................................. ..... 7-2
7.3 PORT 1 AND PORT 3................................................................................................... 7-2
7.4 PORT 0 AND PORT 2................................................................................................... 7-2
7.5 READ-MODIFY-WRITE INSTRUCTIONS..................................................................... 7-5
7.6 QUASI-BIDIRECTIONAL PORT OPERATION.............................................................. 7-6
7.7 PORT LOADING............................................................................................................ 7-7
7.8 EXTERNAL MEMORY ACCESS................................................................................... 7-7
CHAPTER 8
TIMER/COUNTERS AND WATCHDOG TIMER
8.1 TIMER/COUNTER OVERVIEW..................................................................................... 8-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
8.2 TIMER/COUNTER OPERATION................................................................................... 8-1
8.3 TIMER 0......................................................................................................................... 8-3
8.3.1 Mode 0 (13-bit Timer) ...............................................................................................8-4
8.3.2 Mode 1 (16-bit Timer) ...............................................................................................8-4
8.3.3 Mode 2 (8-bit Timer With Auto-reload) ......................................................................8-5
8.3.4 Mode 3 (Two 8-bit Timers) ........................................................................................8-5
8.4 TIMER 1......................................................................................................................... 8-5
8.4.1 Mode 0 (13-bit Timer) ...............................................................................................8-9
8.4.2 Mode 1 (16-bit Timer) ...............................................................................................8-9
8.4.3 Mode 2 (8-bit Timer with Auto-reload) .......................................................................8-9
8.4.4 Mode 3 (Halt) ............................................................................................................8-9
8.5 TIMER 0/1 APPLICATIONS........................................................................................... 8-9
8.5.1 Auto-load Setup Example .........................................................................................8-9
8.5.2 Pulse Width Measurements ....................................................................................8-10
8.6 TIMER 2....................................................................................................................... 8-10
8.6.1 Capture Mode .........................................................................................................8-11
8.6.2 Auto-reload Mode ...................................................................................................8-12
8.6.2.1 Up Counter Operation ........................................................................................8-12
8.6.2.2 Up/Down Counter Operation ..............................................................................8-13
8.6.3 Baud Rate Generator Mode ............................................... ..... ...... ..... .....................8-14
8.6.4 Clock-out Mode .......................................................................................................8-14
8.7 WATCHDOG TIMER................................................................................................... 8-16
8.7.1 Description ..............................................................................................................8-16
8.7.2 Using the WDT ........................................................................................................8-18
8.7.3 WDT During Idle Mode ...........................................................................................8-18
8.7.4 WDT During PowerDown ........................................................................................8-18
CHAPTER 9
PROGRAMMABLE COUNTER ARRAY
9.1 PCA DESCRIPTION...................................................................................................... 9-1
9.1.1 Alternate Port Usage .................................................................................................9-2
9.2 PCA TIMER/COUNTER................................................................................................. 9-2
9.3 PCA COMPARE/CAPTURE MODULES ....................................................................... 9-5
9.3.1 16-bit Capture Mode .................................................................................................9-5
9.3.2 Compare Modes .......................................................................................................9-7
9.3.3 16-bit Software Timer Mode ......................................................................................9-7
9.3.4 High-speed Output Mode ................................................... .......................................9-8
9.3.5 PCA Watchdog Timer Mode .....................................................................................9-9
9.3.6 Pulse Width Modulation Mode ................................................................................9-11
CHAPTER 10
SERIAL I/O PORT
10.1 OVERVIEW ................................................................................................................. 10-1
vi
CONTENTS
10.2 MODES OF OPERATION............................................................................................ 10-4
10.2.1 Synchronous Mode (Mode 0) ..................................................................................10-4
10.2.1.1 Transmission (Mode 0) ......................................................................................10-4
10.2.1.2 Reception (Mode 0) ............................................................................................10-5
10.2.2 Asynchronous Modes (Mode s 1, 2, and 3) .............................................................10-6
10.2.2.1 Transmission (Modes 1, 2, 3) .............................................................................10-6
10.2.2.2 Reception (Modes 1, 2, 3) ..................................................................................10-6
10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)...................................... 10-7
10.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3).................................... 10-7
10.5 AUTOMATIC ADDRESS RECOGNITION................................................................... 10-7
10.5.1 Given Address ........................................................................................................10-8
10.5.2 Broadcast Address ..................................................................................................10-9
10.5.3 Reset Addresses ...................................................................................................10-10
10.6 BAUD RATES............................................................................................................ 10-10
10.6.1 Baud Rate for Mode 0 ...................... ........................................................ ...... ..... ..10-10
10.6.2 Baud Rates for Mode 2 .........................................................................................10-10
10.6.3 Baud Rates for Modes 1 and 3 .............................................................................10-10
10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) ............................................10-11
10.6.3.2 Selecting Timer 1 as the Baud Rate Generator ...............................................10-11
10.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3) ............................................10-12
10.6.3.4 Selecting Timer 2 as the Baud Rate Generator ...............................................10-12
CHAPTER 11
MINIMUM HARDWARE SETUP
11.1 MINIMUM HARDWARE SETUP............ .............................................................. ..... ... 11-1
11.2 ELECTRICAL ENVIRONMENT......................................... .......................................... 11-2
11.2.1 Power and Ground Pins ..........................................................................................11-2
11.2.2 Unused Pins ............................................................................................................11-2
11.2.3 Noise Considerations ..............................................................................................11-2
11.3 CLOCK SOURCES...................................................................................................... 11-3
11.3.1 On-chip Oscillator (Crystal) .....................................................................................11-3
11.3.2 On-chip Oscillator (Ceramic Resonator) .................................................................11-4
11.3.3 External Clock .........................................................................................................11-4
11.4 RESET......................................................................................................................... 11-5
11.4.1 Externally Initiated Re sets .......................... ...... ..... .................................................11-6
11.4.2 WDT Initiated Resets ..............................................................................................11-6
11.4.3 Reset Operation ......................................................................................................11-6
11.4.4 Power-on Reset ......................................................................................................11-7
CHAPTER 12
SPECIAL OPERATING MODES
12.1 GENERAL.................................................................................................................... 12-1
12.2 POWER CONTROL REGISTER ....................................... ...... ..... ............................... 12-1
12.2.1 Serial I/O Control Bits .............................................................................................12-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
12.2.2 Power Off Flag ........................................................................................................12-1
12.3 IDLE MODE................................................................................................................. 12-4
12.3.1 Entering Idle Mode ....................................................... ...........................................12-4
12.3.2 Exiting Idle Mode ....................................................................................................12-5
12.4 POWERDOWN MODE................................................................................................ 12-5
12.4.1 Entering Powerdown Mode .....................................................................................12-6
12.4.2 Exiting Powerdown Mode .......................................................................................12-6
12.5 ON-CIRCUIT EMULATION (ONCE) MODE................................................................ 12-7
12.5.1 Entering ONCE Mode .................................................. ...... ..... ...... ..... .....................12-7
12.5.2 Exiting ONCE Mode ................................................................ ................................12-7
CHAPTER 13
EXTERNAL MEMORY INTERFACE
13.1 OVERVIEW ................................................................................................................. 13-1
13.2 EXTERNAL BUS CYCLES.......................................................................................... 13-3
13.2.1 Bus Cycle Definition s ..............................................................................................13-3
13.2.2 Nonpage Mode Bus Cycles ................................... ...... ...... .....................................13-4
13.2.3 Page Mode Bus Cycles ....................................................................................... ....13-5
13.3 WAIT STATES............................................................................................................. 13-8
13.4 EXTERNAL BUS CYCLES WITH CONFIGURABLE WAIT STATES.......................... 13-8
13.4.1 Extending RD#/WR#/PSEN# ..................................................................................13-8
13.4.2 Extending ALE ......................................................................................................13-10
13.5 EXTERNAL BUS CYCLES WITH REAL-TIME WAIT STATES................................. 13-10
13.5.1 Real-time WAIT# Enable (RTWE) .........................................................................13-12
13.5.2 Real-time WAIT CLOCK Enable (RTWCE) ...........................................................13-12
13.5.3 Real-time Wait State Bus Cycle Diagrams ............................................................13-12
13.6 CONFIGURATION BYTE BUS CYCLES................................................................... 13-15
13.7 PORT 0 AND PORT 2 STATUS................................................................................ 13-16
13.7.1 Port 0 and Port 2 Pin Status in Nonpage Mode ....................................................13-16
13.7.2 Port 0 and Port 2 Pin Status in Page Mode ..........................................................13-17
13.8 EXTERNAL MEMORY DESIGN EXAMPLES............................................................ 13-18
13.8.1 Example 1: RD1:0 = 00, 18-bit Bus, External Flash and RAM ..............................13-18
13.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAM ..............................13-20
13.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAM ..............................................13-22
13.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAM ..............................................13-24
13.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM .........................13-26
13.8.5.1 An Application Requiring Fast Access to the Stack .........................................13-26
13.8.5.2 An Application Requiring Fast Access to Data .................................................13-26
13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAM .........................13-29
13.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External Flash ..............................................13-30
viii
CONTENTS
CHAPTER 14
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY
14.1 GENERAL.................................................................................................................... 14-1
14.1.1 Programming Considerations for On-chip Code Memory .......................................14-2
14.1.2 EPROM Devices .....................................................................................................14-3
14.2 PROGRAMMING AND VERIFYING MODES.............................................................. 14-3
14.3 GENERAL SETUP.................................................. ..... ................................................ 14-3
14.4 PROGRAMMING ALGORITHM................................................................................... 14-5
14.5 VERIFY ALGORITHM.................................................................................................. 14-6
14.6 PROGRAMMABLE FUNCTIONS................................................. ...... ..... ...... .............. 14-6
14.6.1 On-chip Code Memory ............................................................................................ 14-7
14.6.2 Configuration Bytes .................................................................................................14-7
14.6.3 Lock Bit System ......................................................................................................14-7
14.6.4 Encryption Array .................................... ........................................................ ..... ....14-8
14.6.5 Signature Bytes .......................................................................................................14-8
14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM)...................................................... 14-9
APPENDIX A
INSTRUCTION SET REFERENCE
A.1 NOTATION FOR INSTRUCTION OPERANDS............................................................ A-2
A.2 OPCODE MAP AND SUPPORTING TABLES............................................................. A-4
A.3 INSTRUCTION SET SUMMARY................................................................................ A-11
A.3.1 Execution Times for Instructions that Access the Port SFRs ............ .................... A-11
A.3.2 Instruction Summaries ..........................................................................................A-14
APPENDIX B
SIGNAL DESCRIPTIONS
APPENDIX C
REGISTERS
GLOSSARY
INDEX
ix
8XC251SA, SB, SP, SQ USER’S MANUAL
FIGURES
Figure Page
2-1 Functional Block Diagram of the 8XC251SA, SB, SP, SQ...........................................2-2
2-2 The CPU.......................................................................................................................2-5
2-3 Clocking Definitions......................................................................................................2-6
3-1 Address Spaces for MCS® 251 Microcontrollers.........................................................3-1
3-2 Address Spaces for the MCS® 51 Architecture ...........................................................3-3
3-3 Address Space Mappi ngs MCS ® 51 Arch itec tu re to MCS® 251 Arch ite cture.............3-4
3-4 8XC251SA, SB, SP, SQ Address Space .....................................................................3-6
3-5 Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space.................3-7
3-6 The Register File........................................................................................................3-11
3-7 Register File Locations 0–7........................................................................................3-12
3-8 Dedicated Registers in the Register File and their Corresponding SFRs...................3-14
4-1 Configuration Array (On-chip).......................................................................................4-2
4-2 Configuration Array (External)......................................................................................4-3
4-3 Configuration Byte UCONFIG0 ....................................................................................4-6
4-4 Configuration Byte UCONFIG1 ....................................................................................4-7
4-5 Internal/External Address Mapping (RD1:0 = 00 and 01)...........................................4-10
4-6 Internal/External Address Mapping (RD1:0 = 10 and 11)...........................................4-11
4-7 Binary Mode Opcode Map..........................................................................................4-15
4-8 Source Mode Opcode Map........................................................................................4-15
5-1 Word and Double-word Storage in Big Endien Form...................................................5-3
5-2 Program Status Word Register...................................................................................5-18
5-3 Program Status Word 1 Register................................................................................5-19
6-1 Interrupt Control System ...................................... ..... ...... .............................................6-2
6-2 Interrupt Enable Registe r.......................... ..... ...... ..... ...................................................6-6
6-3 Interrupt Priority High Register.....................................................................................6-8
6-4 Interrupt Priority Low Register.................................................... ..................................6-8
6-5 The Interrupt Process...................................................................................................6-9
6-6 Response Time Example #1......................................................................................6-11
6-7 Response Time Example #2......................................................................................6-12
7-1 Port 1 and Port 3 Structure...........................................................................................7-3
7-2 Port 0 Structure............................................................................................................7-3
7-3 Port 2 Structure............................................................................................................7-4
7-4 Internal Pullup Configurations ......................................................................................7-7
8-1 Basic Logic of the Timer/Counters ...............................................................................8-2
8-2 Timer 0/1 in Mode 0 and Mode 1 .................................................................................8-4
8-3 Timer 0/1 in Mode 2, Auto-Reload................................................................................8-5
8-4 Timer 0 in Mode 3, Two 8-bit Timers..................................... ..... ...... ..... ...... .................8-6
8-5 TMOD: Timer/Counter Mode Control Register.............................................................8-7
8-6 TCON: Timer/Counter Control Register.......................................................................8-8
8-7 Timer 2: Capture Mode ..............................................................................................8-11
8-8 Timer 2: Auto Reload Mode (DCEN = 0)....................................................................8-12
8-9 Timer 2: Auto Reload Mode (DCEN = 1)....................................................................8-13
8-10 Timer 2: Clock Out Mode............................................................................................8-15
8-11 T2MOD: Timer 2 Mode Control Register....................................................................8-16
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CONTENTS
FIGURES
Figure Page
8-12 T2CON: Timer 2 Control Register..............................................................................8-17
9-1 Programmable Counter Array.......................................................................................9-3
9-2 PCA 16-bit Capture Mode............................................................................................9-6
9-3 PCA Software Timer and High-speed Output Modes...................................................9-8
9-4 PCA Watchdog Timer Mode.......................................................................................9-10
9-5 PCA 8-bit PWM Mode................................................................................................9-11
9-6 PWM Variable Duty Cycle..........................................................................................9-12
9-7 CMOD: PCA Timer/Counter Mode Register...............................................................9-13
9-8 CCON: PCA Timer/Counter Control Register.............................................................9-14
9-9 CCAPMx: PCA Compare/Capture Module Mode Registers.......................................9-15
10-1 Serial Port Block Diagram..........................................................................................10-2
10-2 SCON: Serial Port Control Register...........................................................................10-3
10-3 Mode 0 Timing............................................................................................................10-5
10-4 Data Frame (Modes 1, 2, and 3)................................................................................10-6
10-5 Timer 2 in Baud Rate Generator Mode....................................................................10-13
11-1 Minimum Setup ..........................................................................................................11-1
11-2 CHMOS On-chip Oscillator.........................................................................................11-3
11-3 External Clock Connection.........................................................................................11-4
11-4 External Clock Drive Waveforms................................................................................11-5
11-5 Reset Timing Sequence.............................................................................................11-8
12-1 Power Control (PCON) Register.................................................................................12-2
12-2 Idle and Powerdown Clock Control............................................................................12-3
13-1 Bus Structure in Nonpage Mode and Page Mode......................................................13-1
13-2 External Code Fetch (Nonpage Mode).......................................................................13-4
13-3 External Data Read (Nonpage Mode)........................................................................13-4
13-4 External Data Write (Nonpage Mode) ........................................................................13-5
13-5 External Code Fetch (Page Mode).............................................................................13-6
13-6 External Data Read (Page Mode)..............................................................................13-7
13-7 External Data Write (Page Mode)...............................................................................13-7
13-8 External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) .......................13-9
13-9 External Data Write (Nonpage Mode, One WR# Wait State).....................................13-9
13-10 External Code Fetch (Nonpage Mode, One ALE Wait State)...................................13-10
13-11 Real-time Wait State Control Register (WCON).......................................................13-11
13-12 External Code Fetch/Data Read (Nonpage Mode, RT Wait State)..........................13-13
13-13 External Data Write (Nonpage Mode, R T Wait State)..............................................13-13
13-14 External Data Read (Page Mode, RT Wait State)....................................................13-14
13-15 External Data Write (Page Mode, RT Wait State)....................................................13-14
13-16 Configuration Byte Bus Cycles.................................................................................13-15
13-17 Bus Diagram for Example 1: 80C251SB in Page Mode...........................................13-18
13-18 Address Space for Example 1..................................................................................13-19
13-19 Bus Diagram for Example 2: 80C251SB in Page Mode...........................................13-20
13-20 Address Space for Example 2..................................................................................13-21
13-21 Bus Diagram for Example 3: 87C251SB/83C251SB in Nonpage Mode..................13-22
13-22 Address Space for Example 3..................................................................................13-23
xi
8XC251SA, SB, SP, SQ USER’S MANUAL
FIGURES
Figure Page
13-23 Bus Diagram for Example 4: 87C251SB/83C251SB in Nonpage Mode..................13-24
13-24 Address Space for Example 4..................................................................................13-25
13-25 Bus Diagram for Example 5: 80C251SB in Nonpage Mode.....................................13-27
13-26 Address Space for Examples 5 and 6......................................................................13-28
13-27 Bus Diagram for Example 6: 80C251SB in Page Mode...........................................13-29
13-28 Bus Diagram for Example 7: 80C251SB in Page Mode...........................................13-30
14-1 Setup for Programming and Verifying Nonvolatile Memory........ ...... ..........................14-5
14-2 Program/Verify Bus Cycles.........................................................................................14-6
B-1 8XC251SA, SB, SP, SQ 44-pin PLCC Package......................................................... B-1
B-2 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages ............................B-3
xii
CONTENTS
TABLES
Table Page
1-1 Intel Application Support Services................................................................................1-7
2-1 8XC251SA, SB, SP, SQ Features................................................................................2-3
3-1 Address Mapping s........................................................................................................3-4
3-2 Minimum Times to Fetch Two Bytes of Code...............................................................3-9
3-3 Register Bank Selectio n................ ........................................................ ...... ...... ..... ....3-12
3-4 Dedicated Registers in the Register File and their Corresponding SFRs...................3-15
3-5 8XC251SA, SB, SP, SQ SFR Map and Reset Values ...............................................3-17
3-6 Core SFRs..................................................................................................................3-18
3-7 I/O Port SFRs...................................... .............................................................. ..... ....3-18
3-8 Serial I/O SFRs ..........................................................................................................3-19
3-9 Timer/Counter and Watchdog Timer SFRs................................................................3-19
3-10 Programmable Counter Array (PCA) SFRs................................................................3-19
4-1 External Addresses for Configuration Array .................................................................4-4
4-2 Memory Signal Selections (RD1:0)..............................................................................4-8
4-3 RD#, WR#, PSEN# External Wait States...................................................................4-13
4-4 Examples of Opcodes in Binary and Source Modes..................................................4-14
5-1 Data Types...................................................................................................................5-2
5-2 Notation for Byte Registers, Word Registers, and Dword Registers............................5-3
5-3 Addressing Modes for Data Instructions in the MCS® 51 Architecture........................5-6
5-4 Addressing Modes for Data Instructions in the MCS® 251 Architecture......................5-7
5-5 Bit-addressable Locations..........................................................................................5-11
5-6 Addressing Two Sample Bits......................................................................................5-12
5-7 Addressing Modes for Bit Instructions........................................................................5-12
5-8 Addressing Modes for Control Instructions.................................................................5-13
5-9 Compare-condit ion al Jump Ins truc tions.................... .................................................5-14
5-10 The Effects of Instructions on the PSW and PSW1 Flags................................. ..... ....5-17
6-1 Interrupt System Pin Signals............... ...... ..... ...... ........................................................6-1
6-2 Interrupt System Special Function Regi ste rs................................... ..... ...... .................6-3
6-3 Interrupt Control Matrix........................................................................................... ......6-4
6-4 Level of Priority.............................................................................................................6-7
6-5 Interrupt Priority Within Level............................... ..... ...... ...... ..... ..................................6-7
6-6 Interrupt Latency Variable s................................................... ..... ...... ..... .....................6-13
6-7 Actual vs. Predicted Latency Calculations..................................................................6-13
7-1 Input/Output Port Pin Descriptions...............................................................................7-1
7-2 Instructions for External Data Moves............................................................................7-9
8-1 Timer/Counter and Watchdog Timer SFRs..................................................................8-2
8-2 External Signals...........................................................................................................8-3
8-3 Timer 2 Modes of Operation.......................................................................................8-15
9-1 PCA Special Function Registers (SFRs)......................................................................9-4
9-2 External Signals...........................................................................................................9-4
9-3 PCA Module Modes ...................................................................................................9-14
10-1 Serial Port Signals ......................................................................................................10-1
10-2 Serial Port Special Function Registers.......................................................................10-2
10-3 Summary of Baud Rates..........................................................................................10-10
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TABLES
Table Page
10-4 Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3..................................10-12
10-5 Selecting the Baud Rate Generator(s).....................................................................10-13
10-6 Timer 2 Generated Baud Rates...............................................................................10-14
12-1 Pin Conditions in Various Modes............... ..... ........................................................ ....12-3
13-1 External Memory Interface Signals.............................................................................13-2
13-2 Bus Cycle Definitions (No Wait States)......................................................................13-3
13-3 Port 0 and Port 2 Pin Status In Normal Operating Mode..........................................13-16
14-1 Programming and Verifying Modes............................................................................14-4
14-2 Lock Bit Function ........................................................................................................14-8
14-3 Contents of the Signature Bytes.................................................................................14-9
A-1 Notation for Register Operands................. ..... ........................................................ .....A-2
A-2 Notation for Direct Addresses... ........................................................ ..... ...... ...... .......... A-3
A-3 Notation for Immediate Addressing.............................................................................A-3
A-4 Notation for Bit Addressing..........................................................................................A-3
A-5 Notation for Destination s in Contro l Instru ct ion s................................... ...... ...... .......... A-3
A-6 Instructions for MCS® 51 Microcontro lle rs..................................................................A-4
A-7 New Instructions for the MCS® 251 Architecture........................................................A-5
A-8 Data Instructions.........................................................................................................A-6
A-9 High Nibble, Byte 0 of Data Instructions......................................................................A-6
A-10 Bit Instructions............................................................................................................. A-7
A-11 Byte 1 (High Nibble) for Bit Instructions.......................................................................A-7
A-12 PUSH/POP Instructions .............................................................................................. A-8
A-13 Control Instructions ....................................................................................................A-8
A-14 Disp lacement /Ext end ed MOVs. ............................................................. ...... ...... .......... A-9
A-15 INC/DEC.................. ...... ..... ...... ..... ...... ...... ............................................................. ...A-10
A-16 Encoding for INC/DEC .............................................................................................. A-10
A-17 Shifts.........................................................................................................................A-10
A-18 St ate Times to Acces s the Port SFRs.................. ..... ...... ..........................................A-12
A-19 Summary of Add and Subtract Instructions...............................................................A-14
A-20 Summary of Compare Instructions............................................................................A-15
A-21 Summary of Increment and Decrement Instructions.................................................A-16
A-22 Summary of Multiply, Divide, and Decimal-adjust Instructions..................................A-16
A-23 Summary of Logical Instructions ...............................................................................A-17
A-24 Summary of Move Instructions..................................................................................A-19
A-25 Summary of Exchange, Push, and Pop Instructions................................................. A-22
A-26 Summary of Bit Instructions.......................................................................................A-23
A-27 Summary of Control Instructions ...............................................................................A-24
A-28 Flag Symbols.............................................................................................................A-26
B-1 PLCC/DIP Pin Assignments Li sted by Functional Category........................................B-2
B-2 Signal Descriptions......................................................................................................B-3
B-3 Memory Signal Selections (RD1:0).............................................................................B-7
C-1 8XC251SA, SB, SP, SQ SFR Map..............................................................................C-2
C-2 Core SFRs...................................................................................................................C-3
C-3 I/O Port SFRs................ ..... .............................................................. ..... ......................C-3
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CONTENTS
TABLES
Table Page
C-4 Serial I/O SFRs ...........................................................................................................C-4
C-5 Timer/Counter and Watchdog Timer SFRs.................................................................C-4
C-6 Programmable Counter Array (PCA) SFRs.................................................................C-5
C-7 Register Fil e.................................. ...... ...... ..... ...... ..... ...... ............................................C-6
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Guide to This Manual
1
CHAPTER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC251SA, S B, SP, SQ† embedded microcontr oller , whic h is the first member of the Intel MCS software and hardware designers familiar with the principles of microcontrollers.

1.1 MANUAL CONTENTS

This manual contains 14 chapters and 3 appendices. This chapter, Chapter 1, provides an over­view of the manual. This section summarizes the contents of the remaining chapters and appen­dices. The remainder of this chapter describes notational conventions and terminology used throughout the manual and provides references to related documentation.
Chapter 2, “Architectural Overview” — provides an overview of device hardware. It covers core functions (pipelined CPU, clock and reset unit, and o n-ch ip memory) and on-chip peripher­als (timer/counters, watchdog timer, programmable counter array, and serial I/O port.)
Chapter 3, “Address Spaces” — describes the three address spaces of the MCS 251 microcon­troller: memory address space, special function register (SFR) space, and the register file. It also provides a map of the S F R space sh owing the lo catio n of the SF Rs an d th eir reset values and ex­plains the mapping of the address spaces of the MCS the MCS 251 architecture.
Chapter 4, “Device Configuration” — describes microcontroller f eatures that are con figured at device reset, including the external memory interface (the number of external address bits, the number of wait states, memory regions for asserting RD#, WR#, and PSEN#, pag e mode), binary/ source opcodes, interrupt mode, and the mapping of a portion of on-chip code memory to data memory. It describes the configuration bytes and how to program them for the desired configu­ration. It also describes how internal memory space maps into external memory.
®
251 microcontroller family. This manual is intended for use by both
®
51 architecture into the address spaces of
Chapter 5, “Programming” — prov ides an overview of the instruction set. It describes each in­struction type (control, arithmetic, logical, etc.) and lists the instructions in tabular form. This chapter also discusses the addressing modes, bit instructions, and the program status words. Appendix A provides a detailed description of each instructi on.
Chapter 6, “Interrupt System” — describes the 8XC251Sx interrupt circuitry which provides a TRAP instruction interrupt and seven maskable interrupts: two external interrupts, three timer interrupts, a PCA interrupt, and a serial port interrupt. This chapter also discusses the interrupt priority scheme, interrupt enable, interrupt processing, and interrupt response time.
† The 8XC251SA, SB, SP, SQ products are also collectively referred to as 8XC251Sx.
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8XC251SA, SB, SP, SQ USER’S MANUAL
Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discusses their configuration for general-purpose I/O, external memory accesses (ports 0, 2), and alterna­tive special functions.
Chapter 8, “Timer/Counters and WatchDog Timer” — describes the three on-chip tim­er/counters and discusses their application. This chapter also provides instructions for using the hardware watchdog timer (WDT) and describes the operation of the WDT during the idle and powerdown modes.
Chapter 9, “Programmable Counter Array” — describes the PCA o n-ch ip periph eral and ex­plains how to configure it for general-purpose applicatio ns (timers and counters) and special ap­plications (programmable WDT and pulse-width modulator).
Chapter 10, “Serial I/O Port” — describes the full-duplex serial I/O port and explains how to program it to communicate with external peripherals. This chapter also discusses baud rate gen­eration, framing error detection, multiprocessor communications, and automatic address recog­nition.
Chapter 11, “Minimum Hardware Setup” — describes the basic requirements for operating the 8XC251Sx in a system. It also discusses on-chip and external clock sources and describes de­vice resets, including power-on reset.
Chapter 12, “Special Operating Modes” — provides an overview of the idle, power down, an d on-circuit emulation (ONCE) modes and describes how to enter and exit each mode. This chapter also describes the power control (PCON) special function register and lists the status of the device pins during the special modes and reset (Table 12-1).
Chapter 13, “External Memory Interface” —describes the external memory signals and bus cycles and provides examples of external memory design. It provides waveform diagr ams for the bus cycles, bus cycles with wait states, and the configuration byte bus cycles. It also provides bus cycle diagrams with AC timing symbols and definitions of the symbols.
Chapter 14, “Programming and Verifying Nonvolatile Memory” — provides instructions for programming and verifying on-chip cod e memory, configuration bytes, signature bytes, lock bits and the encryption array.
Appendix A, “Instruction Set Reference” — provides reference in formation for the instruction set. It describes each instruction; defines the bits in the program status word regis ters (PSW, PSW1); shows the relationships between instructions and PSW flags; and l ists hexadecimal op­codes, instruction lengths, and execution times. Chapter 5, “Programming,” includes a general discussion of the instruction set.
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GUIDE TO THIS MANUAL
Appendix B, “Signal Descriptions” — describes the function(s) of each device pin. Descrip­tions are listed alphabetically by signal name. This appendix also provides a list of the signals grouped by functional category.
Appendix C, “Registers” — accumulates, for convenient reference, copies of the register defi­nition figures that appear throughout the manual.
A glossary has been included for your convenience.

1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY

The following notations and terminology are used in this manual. The Glossary defines other terms with special meanings.
# The pound symbol (#) has either of two meanings, depending on the
context. When used with a signal name, the symbol means that the signal is active low . When u sed in an instru ction, th e sy mbol prefix es an immediate value in immediate addressing mode.
italics Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible meanings.
Variables in registers and signal names are commonly represented by x and y, where x represents the first variable and y represents the second variable. For example, in register Px.y, x represents the variable [1–4] that identifies the specific port, and y represents the register bit variable [7:0]. Variables must be replaced with the correct values when configuring or programming registers or identifying signals.
XXXX Uppercase X (no italics) represents an unknown value or a “don’t
care” state or condition. The value may be either binary or hexadecimal, depending on the context. For example, 2XAFH (hex) indicates that bits 11:8 are unknown; 10XX in binary context indicates that the two LSBs are unknown.
Assert and Deassert The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suf fix; active-high s ignals have no suffix. To assert RD# is to drive it low; to assert ALE is to drive it high; to deassert RD# is to drive it high; to deassert ALE is to drive i t low .
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8XC251SA, SB, SP, SQ USER’S MANUAL
Instructions Instruction mnemonics are shown in upper case to avoid confusion.
When writing code, either upper case or lower case may be used.
Logic 0 (Low) An input voltage level equal to or less than the maximum value of
or an output voltage level equal to or less than the maximum
V
IL
value of V
. See data sheet for values.
OL
Logic 1 (High) An input voltage level equal to or greater than the minimum value of
V
or an output voltage level equal to or greater than the minimum
IH
value of V
. See data sheet for values.
OH
Numbers Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are represented by their customary notations. That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.
Register Bits Bit locations are indexed by 7:0 for byte registers, 15:0 for word
registers, and 31:0 for double-word (dword) registers, where bit 0 is the least-significant bit and 7, 15, or 31 is the most-significant bit. An individual bit is represented by the register name, followed by a period and the bit number. For example, PCON.4 is bit 4 of the power control register. In some discussions, bit names are used. For example, the name of PCON.4 is POF, the power-off flag.
Register Names Register names are shown in upper case. For example, PCON is the
power control register. If a register name contains a lowercase character, it represents more than one register. For example, CCAPMx represents the five registers: CCAPM0 through CCAPM4.
Reserved Bits Some registers contain reserved bits. These bits are not used in this
device, but they may be used in future implementations. Do not write a “1” to a reserved bit. The value read from a reserved bit is indeter­minate.
Set and Clear The terms set and clear refer to the value of a bit or the act of givi ng
it a value. If a bit is set, its value is “1;” setting a bit gives it a “1” value. If a bit is clear, its value is “0;” clearing a bit gives it a “0” value.
Signal Names Signal names are shown in upper case. When several signals share a
common name, an in dividual sig nal is repre sented by the sign al name followed by a number. Port pins are represented by the port abbrevi­ation, a period, and the pin number (e.g., P0.0, P0.1). A pound symbol (#) appended to a signal name identifies an active- low s ignal.
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GUIDE TO THIS MANUAL
Units of Measure The following abbrevi ations are used to represent units of measure:
A amps, amperes DCV direct current volts Kbyte kilobytes KΩ kilo-ohms mA milliamps, milliamperes Mbyte megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts
µA microamps, microamperes µF microfarads µs microseconds µW microwatts

1.3 RELATED DOCUMENTS

The following documents contain additional information that is useful in designing systems that incorporate the 8XC251Sx microcontroller. To order documents, please call Intel Literature Ful­fillment (1-800-548-4725 in the U.S. and Canada; +44(0) 793-431155 in Europe).
Embedded Microcontrollers Order Number 270646
Embedded Processors Order Number 272396
Embedded Applications Order Number 270648
Packaging Order Number 240800
1-5
8XC251SA, SB, SP, SQ USER’S MANUAL
1.3.1 Data Sheet
The data sheet is included in Embedded Microcontrollers and is also available individually.
8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller Order Number 272783 (Commercial/Express)
1.3.2 Application Notes
The following application notes apply to the MCS 251 microcontroller.
AP-125, Designing Microcontroller Systems Order Number 210313 for Electrically Noisy Environments
AP-155, Oscillators for Microcontrollers Order Number 230659
AP-708, Introducing the MCS
®
251 Microcontroller Order Number 272670
—the 8XC251SB
AP-709, Maximizing Performance Using MCS
®
251 Microcontroller Order Number 272671
—Programming the 8XC251SB
AP-710, Migrating from the MCS
®
51 Microcontroller to the MCS 251 Order Number 272672 Microcontroller (8XC251SB)—Software and Hardware Considerations
The following MCS 51 microcontroller applicati on notes also apply to the MCS 251 microcon­troller.
®
AP70, Using the Intel MCS
51 Boolean Processing Capabilities Order Number 203830
AP-223, 8051 Based CRT Terminal Controller Order Number 270032
AP-252, Designing With the 80C51BH Order Number 270068
AP-425, Small DC Motor Control Order Number 270622
AP-410, Enhanced Serial Port on the 83C51FA Order Number 270490
AP-415, 83C51FA/FB PCA Cookbook Order Number 270609
AP-476, How to Implement I
®
Using Intel MCS
1-6
51 Microcontrollers
2
C Serial Communication Order Number 272319
GUIDE TO THIS MANUAL

1.4 APPLICATION SUPPORT SERVICES

You can get up-to-date technical information from a variety of electronic support systems: the World Wide Web, CompuServe, the FaxBack* service, and Intel’s Brand Products and Applica­tions Support bulletin board service (BBS). These systems are available 2 4 hours a day, 7 days a week, providing technical information whenever you need it.
In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m. and 5 p.m. Pacific Standard T ime (PST). Out side the U.S. and Canada, please con­tact your local distributor. You can order product literature from Intel literature centers and sales offices.
Table 1-1 lists the information you need to access these services.
Table 1-1. Intel Application Support Services
Service U.S. and Canada Asia-Pacific and Japan Europe
World Wide Web URL: http://www.intel.com/ URL: htt p:/ /w ww.intel.com/ URL: htt p:/ /w w w.intel.com/ CompuServe go intel go intel go intel FaxBack* 800-525-3019 503-264-6835
916-356-3105
BBS 503-264-7999
916-356-3600
Help Desk 800-628-8686
916-356-7999
Literature 800-548-4725 708-296-9333
503-264-7999 916-356-3600
Please contact your local distributor.
+81(0)120 47 88 32
+44(0)1793-496646
+44(0)1793-432955
Please contact your local distributor.
+44(0)1793-431155 England +44(0)1793-421777 France +44(0)1793-421333 Germany
1.4.1 World Wide Web
We offer a variety of technical and product information through the World Wide Web (URL: ht­tp://www.intel.com/design/mcs96). Also visit Intel’s Web site for financials, history, and news.
1.4.2 CompuServe Forums
Intel maintains several C o mpuServe forums that provide a means for you to gather information, share discoveries, and debate issues. Type “go intel” for access. The INTELC forum is set up to support designers using variou s Intel components. For info rmation about Comp uServe access and service fees, call CompuServe at 1-800-848-8199 (U.S.) or 614-529-1340 (outside the U.S.).
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8XC251SA, SB, SP, SQ USER’S MANUAL
1.4.3 FaxBack Service
The FaxBack service is an on-demand publishing system that sends documents to your fax ma­chine. You can get product announcements, ch ange notifications, pro duct literatu re, d evice ch ar­acteristics, design recommendations, and quality and reliability information from FaxBack 24 hours a day, 7 days a week.
Think of the FaxBack service as a library of technical documents that you can access with your phone. Just dial the telephone number and respo nd to the system prompts. After y ou select a doc­ument, the system sends a copy to y our fax machine.
Each document is assigned an order number and is listed in a subject catalog. The first time you use FaxBack, you should order the appropriate subject catalogs to get a complete listing of doc­ument order numbers. Catalogs are updated twice monthly. In addition, daily update catalogs list the title, status, and order number of each document that has b een added, revised, or deleted dur­ing the past eight weeks. The daily update catalogs are numbered with the subject catalog number followed by a zero. For example, for the complete mic rocontroller and flash catalog, request d oc­ument number 2; for the daily update to the microcontroller and flash catalog, request docu ment number 20.
The following catalogs and information are available at the time of publication:
1. Solutions OEM subscription for m
2. Microcontroller and flash catalog
3. Development tools catalog
4. Systems catalog
5. Multimedia catalog
6. Multib us and iRMX
®
software catalog and BBS file listings
7. Microprocessor, PCI, and peripheral catalog
8. Quality and reliability and change notifica tion catalog
9. iAL (Intel Architecture Labs) technology catalog
1.4.4 Bulletin Board System (BBS)
Intel’ s Brand Products and Applications Support bulletin board system (BBS) lets you download files to your PC. The BBS has the latest ApBUILDER software, hypertext manuals and datasheets, software drivers, firmware upgrades, application notes and utilities, and quality and reliability data.
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GUIDE TO THIS MANUAL
Any customer with a PC and modem can access the BBS. The system provide s automatic conf ig­uration support for 1200- through 19200-baud modems. Use these modem settings: no parity, 8 data bits, and 1 stop bit (N, 8, 1).
T o access the BBS, just dial the telephone nu mber (see Table 1-1 on page 1-7) and r espond to the system prompts. During your first session, the system asks you to register with the system oper­ator by entering your name and location. The system o perator will set up your access account within 24 hours. At that time, you can access the files on the BBS.
NOTE
In the U.S. and Canada, you can get a BBS user’s guide, a master list of BBS files, and lists of FaxBack documents by calling 1-800-525-3019. Use these modem settings: no parity, 8 data bits, and 1 stop bit (N, 8, 1).
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