Support
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
■ Package Options (PDIP, PLCC, and
Ceramic DIP)
A member of the Intel fam ily of 8-bit MCS 251 microcontrollers, th e 8XC251SA/SB/SP/SQ is bina ry-code
compatibl e with MCS 51 microcont rollers and pin compati ble with 40 -pin PDIP a nd 44-pin PLC C MCS 51
microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and
efficient C-la nguage support. T he 8XC251SA/SB/S P/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.
A variety of features can be selected by new user-programmable configurations.
Information in this docum ent is provid ed in connectio n with Int el products. No license, express or implied, by
estoppel or o therwise , to any inte llectual pr operty righ ts is grante d by this d ocument. Except as p rovided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaim s any express or implie d warranty, relating to sale and/or use of Intel products incl uding liability or
warranties relating to fitness for a particular purpose, merchantability , or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-p art y brand s an d name s are the prope rty of the ir respective owner s.
Copies of d ocuments which have an orderin g number an d are referen ced in this do cument, or oth er Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-7 64
or call 1-800-548-4725
A17O18th Address Bit (A17). Output to memory as 18th external address
bit (A17) in extended bus applications, depending on the values of bits
RD0 and RD1 in configuration byte UCONFIG0 (see Chapte r 4,
“Device Configuration,” of the 8XC251SA/SB/SP/SQ Embedded
Microcontroller User ’s Man ual). See also RD# and PSEN# .
A16OAddress Line 16. See RD#.RD#
†
A15:8
AD7:0
OAddress Lines. Upper address lines for the external bus.P2.7:0
†
I/OAddress/Data Lines. Multiplexed lower address lines and data lines
for external memory.
ALEOAddress Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An externa l latch can use ALE to demulti pl ex the addre ss
from the address/data bus.
CEX4:0I/OProgrammable Counter Array (PCA) Input/Output Pins. These are
EA#IExternal Access. Directs program memory accesses to on-chip or off-
input signals for the PCA capture mode and output signals for the PCA
compare mo de and PCA PWM mo de .
chip code memory. For EA# = 0, all program memory accesses are offchip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if
the address is within the range of the on-chip
ROM/OTPROM/EP ROM; otherwise the acce ss is off-chip. The value
of EA# is latched at reset. For devices without on-chip
ROM/OTPROM/EPROM, EA# must be strapped to ground.
ECIIPCA External Clock Input. External clock input to the 16-bit PCA
INT1:0#IExternal Interrupts 0 and 1. These inp uts se t bits IE1: 0 in the TCON
timer.
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by
a falling edge on INT1 #/INT0#. If bits INT1:0 are clear, bits IE1:0 are
set by a low level on INT1:0#.
PROG#IProgramming Pulse. The program min g puls e is app li ed to thi s pin fo r
programming the on-chip OTPROM.
P0.7:0I/OPort 0. This is an 8-bit, open-d rain, bi directio na l I/O port .AD7:0
P1.0
P1.1
P1.2
P1.7:3
I/OPort 1. This is an 8-bit, bidirection al I/O port with in tern a l pullu ps.T2
P2.7:0I/OPort 2. This is an 8-bit, bidirection al I/O port with in tern a l pullu ps.A15: 8
†
The descripti ons of A15 :8 /P2 .7: 0 and AD7:0 /P0.7:0 are for the nonpa ge-mo de chip conf igu ra tio n (com patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontro llers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
I/OPort 3. This is an 8-bit, bid ire ctio na l I/O port with intern al pull ups.RXD
P3.7
PSEN#OProgram Store Enab le. Read signal output. This output is asserted
RD#ORead or 17th Address Bit (A16). Read signal ou tput to exte rna l data
for a memory address range that depends on bits RD0 and RD1 in
configuratio n byte UCONFIG0 (see RD# and Chapter 4, “Device Configuration,” in the 8XC251SA/SB/SP/SQ Embedded Microcontroller
User’s Manual) .
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and
Chapter 4, “Device Configuration,” in the 8XC251SA/SB/SP/SQ
Embedded Microcontroller User’s Manual).
RSTIReset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins
are driven to their reset condit ions when a volta ge great er tha n V
applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and V
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
CC
.
IH1
RXDI/OReceive Serial Data. RXD sends and receives data in serial I/O mode
0 and receives data in serial I/O mode s 1, 2, and 3.
T1:0I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
T2I/OTimer 2 Clock Input/Output. For the timer 2 capture mode, this signal
is the external clock input. For the clock-out mode, it is the timer 2
clock output.
T2EXITim e r 2 External Input. In timer 2 ca ptu re mo de , a fallin g ed ge ini-
TXDOTransmit Serial Data. TXD outputs the shift clock in serial I/O mode 0
V
CC
V
CC2
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
tiates a capture of the timer 2 registers. In auto-reload mode, a falling
edge causes the timer 2 registers to be reloaded. In the up-down
counter mode, this signal determ ines th e count dire ctio n: 1 = up, 0 =
down.
and tran smit s se ria l da ta in seria l I/O mo de s 1, 2, and 3.
PWR Supply Voltage. Connect this pin to the +5V supply voltage.—
PWR Secondary Supply Voltage 2. This supply voltage connection is pro-
vided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB
as a pin-for-pin replacement for the 8XC51FX, V
nected withou t loss of compati bility. (Not available on DIP)
can be uncon-
SS2
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, po rt 0 carries the lower addre ss bit s (A7: 0), and port 2 carries the upper address b its
(A15:8) and the data (D7:0).
IProgrammi ng Sup ply Voltage. The programming supply voltage is
applied to this pin for programming the on-chip OTPROM/EPROM.
GND Circuit Ground. Connect this pin to ground.—
GND Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground
is recommended. However, when using the 8XC251SA/SB/SP/SQ as
a pin-for-pin repla ce men t for the 8XC51 BH, V
without loss of compatibility. (Not available on DIP)
GND Secondary Ground 2. This ground is provided to reduce gro und
bounce and improve power supply bypassing. Connection of this pin to
ground is recomme nded . Howe ve r, when using the 8XC251 SB as a
pin-for-p in replacement for the 8XC5 1FX , V
without loss of compatibility. (Not available on DIP)
can be unconnected
SS1
can be unconnected
SS2
WAIT#IReal-time Wait State Input. The real-time WAIT# input is enabled by
writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal ‘system ready’ to the
microcontroller in real time by controlling the WAIT# input signal on the
por t 1.6 input.
WCLKOWait Clock Output. The real-time WCLK output is driven at port 1.7
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H.
When enabled, the WCLK output produces a square wave signal with
a period of one-half the oscillator frequency.
WR#OWrite. Write signal output to external memory. P3.6
XTAL1IInput to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, its output is connected to this pin. XTAL1
is the clock source for internal timing.
XTAL2OOutput of the On-chi p, Inv ertin g, Oscillator Amp lifi er. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
†
The descripti ons of A15 :8 /P2 .7: 0 and AD7:0 /P0.7:0 are for the nonpa ge-mo de chip conf igu ra tio n (com patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontro llers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
1.18 addres s lines are bo nded out (A15 :0 , A16:0, or A17:0 selecte d dur ing chip conf igu ra tio n).
2.The special functi on registe rs (SF Rs) and the regi ster file have se para te intern al address space s.
3.Data in this area is accessible by indirect addressing only .
4.Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information See EA#. See also UCONFIG1:0 bit definitions in the 8XC251SA/SB /SP/ SQ
Embedded Microcon tro ller User ’s Man ual.
5.The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map
into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal
ROM/OTPROM /EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte
ROM/OTPROM/EPROM devices.
6.This reserved area returns indet ermin at e values.
7.Data is accessible by direct and indirect addressing.
8.Data is accessible by direct, indirect, and bit addressing.
9.Data is accessible by direct, indirect, and register addressing.
10. Eight addresse s at the top of all external memor y maps are reser ved for current and future device
configuration byte information.
Reserved6
External Memory3
External memory or with configuration bit EMAP# = 0, addresses in this range
access on-chip code memory in region FF: (16 Kbyte devices only).
External Memory7
On-chip RAM (512 byte s 00:0020 H - 00:021FH, 102 4 bytes 00:00 20H -
Storage Temperature ................................... -65°C to +150°C
Voltage on EA#/V
Voltage on Any other Pin to V
per I/O Pin................................................................. 15 mA
I
OL
Power Dissipation .......................................................... 1.5 W
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias):
Commercial ................................................. 0°C to +70°C
Express ....................................................-40°C to +85°C
V
(Digital Supply Voltage) .............................. 4.5 V to 5.5 V
CC
..................................................................................... 0 V
V
SS
Pin to VSS......................... 0 V to +13.0 V
PP
..................... -0.5 V to +6.5 V
SS
†
NOTE
Maximum power dissipation is
based on package heat-transfer
limitations, not device power
consumption.
NOTICE: This document contains preliminary
information on new products in production. The
specifications are subject to change without notice.
Verify with your local Intel sale s office that you
have the latest datasheet before finalizing a
design.
†
WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device
reliability.
1.Under steady-state (non-transient) conditions, I
Maximum I
Maximum I
per port pin: 10 mA
OL
per 8-bit port:
OL
port 026 mA
must be externally limited as follows:
OL
ports 1–315 mA
Maximum Total I
all output pins 71 mA
If I
exceeds the test conditions, VOL may exceed the related specificati on. Pins are not guarante ed
OL
to sink current greater than the listed test conditions.
for
OL
2.Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change fro m high to low. In applications where capa citive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3.Capacitive loading on ports 0 and 2 causes the V
1.Under steady-state (non-transient) conditions, I
Maximum I
Maximum I
per port pin: 10 mA
OL
per 8-bit port:
OL
port 026 mA
must be externally limited as follows:
OL
ports 1–315 mA
Maximum Total I
all outp ut pins 71 mA
exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
If I
OL
to sink current great er tha n the listed test conditio ns.
for
OL
2.Capacitive loading on ports 0 and 2 may cause spurious noi se pulse s above 0.4 V on the low-leve l
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capa cita nce di scharg ing into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, th e noise pu lses on these signa ls may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3.Capacitive loading on ports 0 and 2 causes the V
Te st Condi tions: Capacitive load on all pins = 50 pF.
Table 11 lists AC timing parameters for the
8XC251SA/S B/SP/SQ with no wait sta tes. Externa l
wait states can be added by extending
PSEN#/RD#/ WR# and/or by extendin g ALE. In the
table, Notes 3 and 5 mark parameters affected by an
ALE wait state, and Notes 4 and 5 mark parameters
affected by a PSEN#/RD#/WR# wait state.
Figures 8–10 sho w the bus cycles with the timing
parame ters.
T able 11. AC Characteristics
SymbolParameter
F
OSC
T
OSC
XTAL1 FrequencyN/AN/A016MH z
1/F
OSC
@ 12 MHz
@ Max F
MinMaxMinMax
N/AN/A
(1)F
osc
@ 16 MHz
T
T
T
LHLL
AVLL
LLAX
ALE Pulse Width
@ 12 MHz
@ 16 MHz
Address Valid to ALE Low
@ 12 MHz
@ 16 MHz
Address Hold after AL E Low
@ 12 MHz
@ 16 MHz
73.3
52.5
58.3
37.5
15
1515
NOTES:
1.16 MHz .
2.Specifications for PSEN# are identical to those for RD#.
3.In the formula , M=N um be r of wait st ate s (0 or 1) for ALE.
4.In the formula, N=Numb er of wait states (0,1 ,2, or 3) for RD#/PSEN# /W R#.
5.“Typical” specifications are un teste d and not gua rantee d .
AC inputs during testing are driven at V
and 0.45 V for a logic 0. Timing measurements are made at
a min of V
for a logic 1 and V
IH
0.2 V
0.2 V
CC
CC
+ 0.9
– 0.1
OL
– 0.5V for a logic 1
CC
for a logic 0.
Outputs
V
MIN
IH
V
MAX
OL
Figure 19. AC Testing Input, Output Waveforms
T
CHCX
A4119-01
A4118-01
V
V
LOAD
V
LOAD
LOAD
+ 0.1 V
Timing Reference
Points
– 0.1 V
V
V
OH
OL
– 0.1 V
+ 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading V
All thermal impedance data is approximate for static
air conditio ns at 1 watt of power di ssipatio n. Values
change depending on operating conditions and
application requirements. The Intel
Handbook
thermal impedance test methodology.
(order n umber 240800) d escribes I ntel’s
Packaging
Table 16. The rm al Cha rac teristics
Package Typeθ
44-pin PLCC46°C/W16°C/W
40-pin PDIP45°C/W16°C/W
40-pin Cera mic DIP30.5°C/W10°C/W
JA
7.0NONV OL ATILE MEMORY PROGRAMMING AND V ERIFICATION
CHARACTERIS TICS
7.1Defin iti on of Nonvo lati le M emor y Sym b ols
Table 17. Nonvolatile Mem ory Timing Symb ol Defin itio ns
SignalsConditions
AAddressHHigh
DData I nLLow
QData OutVValid
SSupplyXNo Long er Valid
GPROG#ZFloating
EEnable
7.2Pro gram m in g and Verification Timing for Nonvo la til e Memo ry
Programming CycleVerification Cycle
P1, P3
P2
T
AVGL
Data In (8 Bits)
T
DVGL
T
GHGL
T
GHDX
T
GHAX
AddressAddress (16 Bits)
T
AVQV
Data Out
PROG#
EA#/V
PP
P0
5V
12.75V
T
GLGH
T
12345
SHGL
T
EHSH
Mode (8 Bits)
T
GHSL
T
ELQV
Mode
T
EHQZ
Figure 21. Timing for Progra mm ing and Verificatio n of Nonvo lati le Mem ory
Table 18. Nonvolatile Memory Programming and Verification Characteristics at
T
= 21 – 27 °C, VCC = 5 V, and VSS = 0 V
A
SymbolDefinitionMinMaxUnits
V
I
PP
F
T
T
T
T
T
T
T
T
PP
OSC
AVGL
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
Programming Supply Voltage12.513.5D.C. Volts
Programming Supply Current75mA
Oscil lator Frequency4.06.0MHz
Address Setup to PROG# Low48T
Address Hold after PROG#48T
Data Setup to PROG# Low48T
Data Hold after PROG#48T
ENABLE High to V
PP
48T
OSC
OSC
OSC
OSC
OSC
VPP Setup to PROG# Low10µs
VPP Hold after PROG#10µs
PROG# Width90110µs
Table 18. Nonvolatile Memory Programming and Verification Characteristics at
= 21 – 2 7 °C, VCC = 5 V, and VSS = 0 V(Continued)
T
A
T
T
T
T
AVQV
ELQV
EHQZ
GHGL
Address to Data Valid48T
ENABLE Low to Data Valid48T
Data Float after ENABLE048T
PROG# High to PROG# Low10µs
8.0ERRATA
There are no known errata for this product.
9.0REVIS ION HIS T ORY
This (-003) revision of the 8XC251SA/SB/SP/SQ
datasheet contains information on products with
“[M] [C] '94 '95 C” as the last line of the topside
marking. This datasheet replaces earlier product
inform atio n. The foll owing chang es appe ar in the 003 datasheet:
1.Real-time wait state operation is described in
the d atasheet.
2.Memory map reserved locations are newly
defined and the Memory Map is now referred
to as the “Address Map.”
3.AC Characteristics have been updated. The
following AC parameters have changed: T
, T
, T
, T
, T
AVRL
RHDZ1
, T
, T
AVWL1
RHDZ2
T
RLRH
WLWH
LLRL
T
, T
WHLH
AVDV1
, an d T
T
QVWH
4.DC Characteristi cs have be en upd ated. The
, T
WHAX
AVDV2
.
RLDV
, T
following DC specs have changed: I
typical, I
5.An I
6.Process information is no longer contained in
max, ICC typical, and ICC max.
DL
vs. Frequency graph is included.
CC
the d atasheet.
7.The section “Progra mmi ng and Verifying Nonvolatile Memory” has been deleted. See the
8XC251SA/SB/SP/SQ Embedded Microcontroller User’s Manual. Timing and Characteristics for Programming and Verifying Nonvolatile
, T
AVWL2
PD
LLAX
, T
RHLH2
,
max, IDL
OSC
OSC
OSC
memory have been retained in this datasheet.
8.Signature Byte information has been deleted.
See the 8XC251SA/SB/SP/SQ Embedded
Microcontroller User’s Manual.
9.Sections in the datasheet are numbered.
10. New sections have been create d to provide
better organization. These include “Nomenclature,” “Pinout,” “Signals,” “Address Map,”
“Electrical Characteristics,” “Thermal Characteristics,” “Nonvolatile Memory Programming
and Verification Characteristics”, “Errat a,” and
“Revision History”
1 1. Proliferation Options and Package Options are
in the Nomenclature section.
12. Temperature range is contained in the Electrical Characteristics section under “Oper ating
Conditions”
13. Bus timing diagrams have been organized into
subsections.
,
The (-002) revision of the 8XC251SA/SB/SP/SQ
,
datasheet contains information on products with
“[M] [C] '94 '95 B” as the last line of the topside
marking. This datasheet replaces earlier product
information. The following changes appear in the 002 datasheet:
1.A corrected PDIP diagram appears on page 7.
2.A corrected formula to calculate T
described on page 17.
3.The RD#/PSEN# waveform is changed in Figure 11 on page 25.
LHLL
is
PRELIMINARY35
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