Intel 8XC251SB, 8XC251SP, 8XC251SQ, 8XC251SA User Manual
8XC251SA/SB/SP/SQ
HIGH-PERFORMANCE
CHMOS MICROCONTROLLER
Commercial/Express
PRELIMINARY
■ Real-time and Programmed Wait State
Bus Operation
®
■ Binary-code Compatible with MCS
■ Pin Compatible with 44-pin PLCC and 40-
pin PDIP MCS 51 Sockets
®
■ Register-based MCS
— 40-byte Register File
— Registers Accessible as Bytes, Words,
or Double Words
■ Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
■ Linear Addressing
■ 256-Kbyte Expanded External Code/Data
Memory Space
■ ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
■ 16-bit Internal Code Fetch
■ 64-Kbyte Extended Stack Space
■ On-chip Data RAM Options:
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
■ 8-bit, 2-clock External Code Fetch in
Page Mode
■ Fast MCS 251 Instruction Pipeline
251 Architect u r e
51
■ User-selectable Configurations:
— External Wait States (0-3 wait states)
— Address Range & Memory Mapping
— Page Mode
■ 32 Programmable I/O Lines
■ Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
■ Three Flexible 16-bit Timer/counters
■ Hardware Watchdog Timer
■ Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
■ Programmable Serial I/O Port
— Framing Error Detection
— Automatic Address Recognition
■ High-performance CHMOS Technology
■ Static Standby to 16-MHz Operation
■ Complete System Development
Support
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
■ Package Options (PDIP, PLCC, and
Ceramic DIP)
A member of the Intel fam ily of 8-bit MCS 251 microcontrollers, th e 8XC251SA/SB/SP/SQ is bina ry-code
compatibl e with MCS 51 microcont rollers and pin compati ble with 40 -pin PDIP a nd 44-pin PLC C MCS 51
microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and
efficient C-la nguage support. T he 8XC251SA/SB/S P/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.
A variety of features can be selected by new user-programmable configurations.
COPYRIGHT © INTEL CORPORATION, 1996 May 1996 Order Number: 272783-003
Information in this docum ent is provid ed in connectio n with Int el products. No license, express or implied, by
estoppel or o therwise , to any inte llectual pr operty righ ts is grante d by this d ocument. Except as p rovided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaim s any express or implie d warranty, relating to sale and/or use of Intel products incl uding liability or
warranties relating to fitness for a particular purpose, merchantability , or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-p art y brand s an d name s are the prope rty of the ir respective owner s.
Copies of d ocuments which have an orderin g number an d are referen ced in this do cument, or oth er Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-7 64
or call 1-800-548-4725
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
System Bus and I/O Ports
P0.7:0
Port 0
Drivers
Code Bus (16)
SRC1 (8)
SRC2 (8)
ALU
P2.7:0
Port 2
Drivers
Memory Data (16)
Memory Address (16)
Bus Interface
Instruction Sequencer
Register
File
Code
OTPROM/ROM
8 Kbytes
or
16 Kbytes
Code Address (24)
Data
Memory
Interface
Data Address (24)
Data Bus (8)
Data RAM
512 Bytes
or
1024 Bytes
Peripheral
Interface
Interrupt
Handler
Clock
&
Reset
I/O Ports and
Peripheral Signals
P1.7:0
Port 1
Drivers
IB Bus (8)
P3.7:0
Port 3
Drivers
Watchdog
Timer
Timer/
Counters
PCA
Serial I/O
Peripherals
DST (16)
®
MCS
251 Microcontroller Core
Clock & Reset
8XC251SA/SB/SP/SQ Microcontroller
A4214-01
Figure 1. 8XC251SA/SB/SP/SQ Block Diagram
PRELIMINARY 3
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
1.0 NOMENCLATURE
XXXXX XXXX8XXX
Program-memory Options
Packaging Options
Temperature and Burn-in Options
Figure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature
Table 1. Descriptio n of Pro duc t Nomenc lat ure
Parame ter Options Descript ion
Temperature and Burn-in
Options
Packaging Options N 44-pin Plastic Leaded Chip Carrier (PLCC)
Program Memory Options 0 Without ROM/OTPROM/EPROM
Process Information C CHMOS
Product Family 251 8-bit control architecture
Device Memory Options SA 1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM
Device Speed 16 External clock frequency
no mark Commercial operating temperature range (0°C to 70°C) with
T Express operat ing tempe rat ure range (-40 °C to 85°C) with
P 40-pin Plastic Dual In-line Package (PDIP)
C 40-pin Ceramic Dual In-lin e Package (Cera mic DIP)
3ROM
7 User programmable OTPROM/EPROM
SB 1-Kbyte RAM/16-Kb yt e ROM/OT PROM /EPROM or withou t
SP 512-byte RAM/8-Kbyte ROM/OTPROM/EPROM
SQ 512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without
Process Information
Intel stan dard bu rn-in.
Intel stan dard bu rn-in.
ROM/OTPROM/EPROM
ROM/OTPROM/EPROM
Product Family
Device Speed
A2815-01
4 PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 2 lists the proliferation op tions. See Figure 2 for the 8XC2 51 SA/S B/SP/ SQ fam ily nome ncla tu re.
.
Table 3 lists the 8XC251SA/SB/SP/SQ packages.
N 44 ld. PLCC 0°C to +70°C
P 40 ld. Plastic DIP 0°C to +70°C
C 40 ld. Ceramic DIP 0°C to +70°C
TN 44 ld. PLCC -40°C to +85°C
TP 40 ld. Plastic DIP -40°C to +85°C
Table 2. Proliferation Options
8XC251SA/SB /SP/ SQ
(0 – 16 MHz; 5 V ±10%)
80C251SB16 C PU-on ly
80C251SQ1 6 CPU-only
83C251 SA1 6 ROM
83C251 SB1 6 ROM
83C251 SP1 6 ROM
83C251 SQ1 6 ROM
87C251SA16 OTPROM/EPROM
87C251SB16 OTPROM/EPROM
87C251SP16 OTPROM/EPROM
87C251SQ16 OTPROM/EPROM
T able 3. Package Information
Pkg. Definitio n Tempera ture
PRELIMINARY 5
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
EA# / V
PP
V
SS2
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
P1.4 / CEX1
P1.3 / CEX0
P1.2 / ECI
P1.1 / T2EX
P1.0 / T2
V
SS1
V
CC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
A4205-02
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
P3.0 / RXD
V
CC2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
P3.5 / T1
39
38
37
36
35
34
33
32
31
30
29
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
View of component as
mounted on PC board
7
8
9
10
11
12
13
14
15
16
17
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
V
SS
V
SS2
A8 / P2.0
A9 / P2.1
A10 / P2.2
A11 / P2.3
A12 / P2.4
18
19
20
21
22
23
24
25
26
27
28
65432
1
44
43
42
41
40
2.0 PINOUT
Figure 3. 8XC251SA/SB/SP /SQ 44-p in PLCC Package
6 PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
P1.0 / T2
P1.1 / T2EX
P1.2 / ECI
P1.3 / CEX0
P1.4 / CEX1
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
P3.0 / RXD
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
P3.5 / T1
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
V
1
2
3
4
5
8XC251SA
6
8XC251SB
7
8XC251SP
8
8XC251SQ
9
10
11
12
13
14
15
16
17
18
19
20
SS
View of
component
as mounted
on PC board
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
V
EA# /
PP
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
A12 / P2.4
A11 / P2.3
A10 / P2.2
A9 / P2.1
A8 / P2.0
Figure 4. 8XC251SA/ SB/SP /SQ 40-pin PDIP an d Ceram ic DIP Package s
A4206-03
PRELIMINARY 7
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 4. 8XC251SA/SB/S P/SQ Pin Ass ignme nt
PLCC DIP Name PLCC DIP Name
1
2 1 P1.0/T2 24 21 A8/P2.0
3 2 P1.1/T2EX 25 22 A9/P2.1
4 3 P1.2/ECI 26 23 A10/P2.2
5 4 P1.3/CEX0 27 24 A11/P2.3
6 5 P1.4/CEX1 28 25 A12/P2.4
7 6 P1.5/CEX2 29 26 A13/P2.5
8 7 P1.6/CEX3/WAIT# 30 27 A14/P2.6
9 8 P1.7/CEX4/A17/WCLK 31 28 A15/P2.7
10 9 RST 32 29 PSEN#
11 10 P3.0/RXD 33 30 ALE/PROG#
12
13 11 P3.1/TXD 35 31 EA#/V
14 12 P3.2/INT0# 36 32 AD7/P0.7
15 13 P3.3/INT1# 37 33 AD6/P0.6
16 14 P3.4/T0 38 34 AD5/P0.5
17 15 P3.5/T1 39 35 AD4/P0.4
18 16 P3.6/WR# 40 36 AD3/P0.3
19 17 P3.7/RD#/A16 41 37 AD2/P0.2
20 18 XTAL2 42 38 AD1/P0.1
21 19 XTAL1 43 39 AD0/P0.0
22 20 V
V
SS1
V
CC2
SS
23 V
34 V
44 40 V
SS2
SS2
CC
PP
8 PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5. 8XC251SA/SB/SP/SQ PLCC/DIP Pin Assignments Arranged by Functional Category
Address & Data Input/Output
Name PLCC DIP Name PLCC DIP
AD0/ P 0.0 43 39 P1.0/T2 2 1
AD1/ P 0.1 42 38 P1.1/T2 EX 3 2
AD2/ P 0.2 41 37 P1.2/ECI 4 3
AD3/ P 0.3 40 36 P1.3/CEX0 5 4
AD4/ P 0.4 39 35 P1.4/CEX1 6 5
AD5/ P 0.5 38 34 P1.5/CEX2 7 6
AD6/P0.6 37 33 P1.6/CE X3/ WAIT# 8 7
AD7/P0.7 36 32 P1.7/CEX4/ A17/WC LK 9 8
A8/P2.0 24 21 P3.0/RXD 11 10
A9/P2.1 25 22 P3. 1/T XD 13 11
A10/P2.2 2623 P3.4/T0 1614
A11/P2.3 27 24 P3.5/T1 17 15
A12/P2.4 28 25
A13/P2.5 29 26 Power & Ground
A14/P2.6 30 27 Name PLCC DIP
A15/P2.7 31 28 V
P3.7/RD#/A16 19 17 V
P1.7/CEX4/A17/WCLK 9 8 V
CC
CC2
SS
V
SS1
V
SS2
Processor Control EA#/VPP 35 31
Name PLCC DIP
P3.2/INT0# 14 12 Bus Control & Status
P3.3/INT1# 15 13 Name PLCC DIP
EA#/V
PP
35 31 P3.6/WR# 18 16
RST 10 9 P3.7/RD#/A16 19 17
XTAL1 21 18 ALE/PROG# 33 30
XTAL2 20 19 PSEN# 32 29
44 40
12
22 20
1
23, 34
PRELIMINARY 9
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
3.0 SIGNALS
Table 6. Signal Descriptions
Signal
Name
Type Description
A17 O 18th Address Bit (A17). Output to memory as 18th external address
bit (A17) in extended bus applications, depending on the values of bits
RD0 and RD1 in configuration byte UCONFIG0 (see Chapte r 4,
“Device Configuration,” of the 8XC251SA/SB/SP/SQ Embedded
Microcontroller User ’s Man ual). See also RD# and PSEN# .
A16 O Address Line 16. See RD#. RD#
†
A15:8
AD7:0
O Address Lines. Upper address lines for the external bus. P2.7:0
†
I/O Address/Data Lines. Multiplexed lower address lines and data lines
for external memory.
ALE O Address Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An externa l latch can use ALE to demulti pl ex the addre ss
from the address/data bus.
CEX4:0 I/O Programmable Counter Array (PCA) Input/Output Pins. These are
EA# I External Access. Directs program memory accesses to on-chip or off-
input signals for the PCA capture mode and output signals for the PCA
compare mo de and PCA PWM mo de .
chip code memory. For EA# = 0, all program memory accesses are offchip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if
the address is within the range of the on-chip
ROM/OTPROM/EP ROM; otherwise the acce ss is off-chip. The value
of EA# is latched at reset. For devices without on-chip
ROM/OTPROM/EPROM, EA# must be strapped to ground.
ECI I PCA External Clock Input. External clock input to the 16-bit PCA
INT1:0# I External Interrupts 0 and 1. These inp uts se t bits IE1: 0 in the TCON
timer.
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by
a falling edge on INT1 #/INT0#. If bits INT1:0 are clear, bits IE1:0 are
set by a low level on INT1:0#.
PROG# I Programming Pulse. The program min g puls e is app li ed to thi s pin fo r
programming the on-chip OTPROM.
P0.7:0 I/O Port 0. This is an 8-bit, open-d rain, bi directio na l I/O port . AD7:0
P1.0
P1.1
P1.2
P1.7:3
I/O Port 1. This is an 8-bit, bidirection al I/O port with in tern a l pullu ps. T2
P2.7:0 I/O Port 2. This is an 8-bit, bidirection al I/O port with in tern a l pullu ps. A15: 8
†
The descripti ons of A15 :8 /P2 .7: 0 and AD7:0 /P0.7:0 are for the nonpa ge-mo de chip conf igu ra tio n (com patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontro llers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
Alternate
Function
P1.7/CEX4/
WCLK
P0.7:0
PROG#
P1.6 :3
P1.7 /A17/
WAIT#
V
PP
P1.2
P3.3:2
ALE
T2EX
ECI
CEX3: 0
CEX4/ A17 /
WAIT#/
WCLK
10 PRELIMINARY
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. Signal Descriptions (Contin ued )
Signal
Name
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
Type Description
I/O Port 3. This is an 8-bit, bid ire ctio na l I/O port with intern al pull ups. RXD
P3.7
PSEN# O Program Store Enab le. Read signal output. This output is asserted
RD# O Read or 17th Address Bit (A16). Read signal ou tput to exte rna l data
for a memory address range that depends on bits RD0 and RD1 in
configuratio n byte UCONFIG0 (see RD# and Chapter 4, “Device Configuration,” in the 8XC251SA/SB/SP/SQ Embedded Microcontroller
User’s Manual) .
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and
Chapter 4, “Device Configuration,” in the 8XC251SA/SB/SP/SQ
Embedded Microcontroller User’s Manual).
RST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins
are driven to their reset condit ions when a volta ge great er tha n V
applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and V
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
CC
.
IH1
RXD I/O Receive Serial Data. RXD sends and receives data in serial I/O mode
0 and receives data in serial I/O mode s 1, 2, and 3.
T1:0 I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
T2 I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal
is the external clock input. For the clock-out mode, it is the timer 2
clock output.
T2EX I Tim e r 2 External Input. In timer 2 ca ptu re mo de , a fallin g ed ge ini-
TXD O Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0
V
CC
V
CC2
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
tiates a capture of the timer 2 registers. In auto-reload mode, a falling
edge causes the timer 2 registers to be reloaded. In the up-down
counter mode, this signal determ ines th e count dire ctio n: 1 = up, 0 =
down.
and tran smit s se ria l da ta in seria l I/O mo de s 1, 2, and 3.
PWR Supply Voltage. Connect this pin to the +5V supply voltage. —
PWR Secondary Supply Voltage 2. This supply voltage connection is pro-
vided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB
as a pin-for-pin replacement for the 8XC51FX, V
nected withou t loss of compati bility. (Not available on DIP)
can be uncon-
SS2
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, po rt 0 carries the lower addre ss bit s (A7: 0), and port 2 carries the upper address b its
(A15:8) and the data (D7:0).
is
Alternate
Functio n
TXD
INT1:0#
T1:0
WR#
RD#/A16
—
P3.7/A16
—
P3.0
P3.5:4
P1.0
P1.1
P3.1
—
PRELIMINARY 11
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