Intel 87C196CB, 8XC196NT User Manual

87C196CB Supplement to 8XC196NT User’s Manual

87C196CB Supplement to 8XC196NT User’s Manual

August 2004

Order Number: 272787-003

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rwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

othe of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

l may make changes to specifications and product descriptions at any time, without notice.

Inte

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Inte

l reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising

from future changes to them.

The 87C196CB and 8XC196NT microprocessors may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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*Third-party brands and names are th e property of their respective owners.

CHAPTER 1

GUIDE TO THIS MANUAL

1.1 MANUAL CONTENTS................................................................................................... 1-1

1.2 RELATED DOCUMENTS.............................................................................................. 1-2

CHAPTER 2

ARCHITECTURAL OVERVIEW

2.1 DEVICE FEATURES ................................................... ...... ...... ..... ................................. 2-1

2.2 BLOCK DIAGRAM....................................... ..... ...... ..... ...... ............................................ 2-2

2.3 INTERNAL TIMING........................................................................................................ 2-2

CHAPTER 3

MEMORY PARTITIONS

3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING .................. 3-1

CHAPTER 4

STANDARD AND PTS INTERRUPTS

4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES............................................. 4-1

CHAPTER 5

I/O PORTS

5.1 PORT 0 AND EPORT.................................................................................................... 5-1

CHAPTER 6

ANALOG-TO-DIGITAL (A/D) CONVERTER

6.1 ADDITIONAL A/D INPUT CHANNELS.......................................................................... 6-1

CHAPTER 7

CAN SERIAL COMMUNICATIONS CONTROLLER

7.1 CAN FUNCTIONAL OVERVIEW................................................................................... 7-1

7.2 CAN CONTROLLER SIGNALS AND REGISTERS....................................................... 7-3

7.3 CAN CONTROLLER OPERATION................................................................................ 7-4

7.3.1 Address Map ..................................................... ........................................................7-5

7.3.2 Message Objects ........................................ ...... ..... ...................................................7-5

7.3.2.1 Receive and Transmit Priorities ...........................................................................7-6

7.3.2.2 Message Acceptance Filt ering .......................... ...... ...... ............................ ..... ......7-6

7.3.3 Message Frames .............................................. ..... ...................................................7-7

7.3.4 Error Detection and Management Logic ...................................................................7-9

7.3.5 Bit Timing ................................................................................................................7-10

7.3.5.1 Bit Timing Equations ..........................................................................................7-12

7.4 CONFIGURING THE CAN CONTROLLER................................................................. 7-13

7.4.1 Programming the CAN Control (CAN_CON) Register ............................................7-13

7.4.2 Programming the Bit Timing 0 (CAN_BTIME0) Register ........................................7-15

7.4.3 Programming the Bit Timing 1 (CAN_BTIME1) Register ........................................7-16

iii

87C196CB SUPPLEMENT

7.4.4 Programming a Message Acceptance Filter ...........................................................7-17

7.5 CONFIGURING MESSAGE OBJECTS....................................................................... 7-20

7.5.1 Specifying a Message Object’s Configuration .........................................................7-21

7.5.2 Programming the Message Object Identifier ...........................................................7-22

7.5.3 Programming the Message Object Control Registers .............................................7-23

7.5.3.1 Message Object Control Register 0 ...................................................................7-23

7.5.3.2 Message Object Control Register 1 ...................................................................7-23

7.5.4 Programming the Message Object Data .................................................................7-23

7.6 ENABLING THE CAN INTERRUPTS.......................................................................... 7-29

7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS......................... 7-32

7.8 FLOW DIAGRAMS ...................................................................................................... 7-35

7.9 DESIGN CONSIDERATIONS...................................................................................... 7-41

7.9.1 Hardware Reset ......................................................................................................7-41

7.9.2 Software Initialization ..............................................................................................7-41

7.9.3 Bus-off State ...........................................................................................................7-41

CHAPTER 8

SPECIAL OPERATING MODES

8.1 CLOCK CIRCUITRY...................................................................................................... 8-1

CHAPTER 9

INTERFACING WITH EXTERNAL MEMORY

9.1 ADDRESS PINS............................................................................................................ 9-1

9.2 BUS TIMING MODES.................................................................................................... 9-1

CHAPTER 10

PROGRAMMING THE NONVOLATILE MEMORY

10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES.......................................... 10-1

10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE.............................................. 10-1

10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING................................... 10-2

10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMING.............................................. 10-3

10.4.1 Selecting Bank 0 (FF2000–FF7FFFH) ....................................................................10-4

10.4.2 Selecting Bank 1 (FF8000–FFFFFFH) ....................................................................10-4

APPENDIX A

SIGNAL DESCRIPTIONS

A.1 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. A-1

A.2 SIGNAL DESCRIPTIONS............................................................................................. A-3

A.3 DEFAULT CONDITIONS............................................................................................ A-14

GLOSSARY

INDEX

CONTENTS

FIGURES

Figure Page

2-1 87C196CB Block Diagram............................................................................................2-2

2-2 Clock Circuitry..............................................................................................................2-3

2-3 Internal Clock Phases..................................................................................................2-4

2-4 Effect of Clock Mode on CLKOUT Frequency..............................................................2-5

4-1 Interrupt Mask 1 (INT_MASK1) Register......................................................................4-2

4-2 interrupt Pending 1 (INT_PEND1) Register..................................................................4-2

5-1 Port

5-2 Extended Port I/O Direction (EP_DIR) Register...........................................................5-2

5-3 Extended Port Mode (EP_MODE) Register.................................................................5-2

5-4 Extended Port Input (EP_PIN) Register.......................................................................5-3

5-5 Extended Port Data Output (EP_REG) Register..........................................................5-3

6-1 A/D Command (AD_COMMAND) Register....................................................... ..... ......6-2

6-2 A/D Result (AD_RESULT) Register — Read Format...................................................6-3

7-1 A System Using CAN Controllers.................................................................................7-1

7-2 CAN Controller Block Diagram.....................................................................................7-2

7-3 CAN Message Frames.................................................................................................7-7

7-4 A Bit Time as Specified by the CAN Protocol.............................................................7-10

7-5 A Bit Time as Implemented in the CAN Controller .....................................................7-11

7-6 CAN Control (CAN_CON) Register............................................................................7-13

7-7 CAN Bit Timing 0 (CAN_BTIME0) Register................................................................7-15

7-8 CAN Bit Timing 1 (CAN_BTIME1) Register................................................................7-16

7-9 CAN Standard Global Mask (CAN_SGMSK) Register...............................................7-18

7-10 CAN Extended Global Mask (CAN_EGMSK) Register..............................................7-19

7-11 CAN Message 15 Mask (CAN_MSK15) Register.......................................................7-20

7-12 CAN Message Object 7-13 CAN Message Object 7-14 CAN Message Object 7-15 CAN Message Object 7-16 CAN Message Object Data (CAN_MSG

7-17 CAN Control (CAN_CON) Register............................................................................7-29

7-18 CAN Message Object

7-19 CAN Interrupt Pending (CAN_INT) Register..............................................................7-32

7-20 CAN Status (CAN_STAT) Register............................................................................7-33

7-21 CAN Message Object

7-22 Receiving a Message for Message Objects 1–14 — CPU Flow ................................7-36

7-23 Receiving a Message for Message Object 15 — CPU Flow......................................7-37

7-24 Receiving a Message — CAN Controller Flow...........................................................7-38

7-25 Transmitting a Message — CPU Flow.......................................................................7-39

7-26 Transmitting a Message — CAN Controller Flow.......................................................7-40

8-1 Clock Circuitry..............................................................................................................8-1

9-1 Modes 0 and 3 Timings................................................................................................9-2

9-2 Chip Configuration 1 (CCR1) Register.........................................................................9-3

10-1 Auto Programming Circuit..........................................................................................10-3

A-1 87C196CB 84-pin PLCC Package..............................................................................A-2

Pin Input (Px_PIN) Register...............................................................................5-1

Configuration (CAN_MSGxCFG) Register...........................7-21

Identifier (CAN_MSGxID0–3) Register................................7-22

Control 0 (CAN_MSGxCON0) Register...............................7-24

Control 1 (CAN_MSGxCON1) Register...............................7-26

DATA0–7) Registers..................................7-28

Control 0 (CAN_MSGxCON0) Register...............................7-31

Control 0 (CAN_MSGxCON0) Register...............................7-34

8XC196CB SUPPLEMENT

FIGURES

Figure Page

A-2 87C196CB 100-pin QFP Package............... .......... .. .......... .. .......... .................... .. .......A-3

CONTENTS

TABLES

Table Page

1-1 Related Documents......................................................................................................1-2

2-1 Features of the 8XC196NT and 87C196CB.................................................................2-1

2-2 State Times at Various Frequencies................................................ ............................2-4

2-3 Relationships Between Input Frequency, Clock Multiplier, and State Times...............2-5

3-1 Register File Memory Addresses.................................... .............................................3-1

3-2 87C196CB Memory Map..............................................................................................3-2

3-3 87C196CB Peripheral SFRs.........................................................................................3-3

3-4 CAN Peripheral SFRs...................................................................................................3-4

3-5 Selecting a Window of Peripheral SFRs.......................................................................3-6

3-6 Selecting a Window of the Upper Register File............................................................3-7

3-7 Selecting a Window of Upper Register RAM................................................................3-8

3-8 Windows .......................................................................................................................3-9

3-9 WSR Settings and Direct Addresse s for Windowable SFRs......................................3-11

4-1 Interrupt Sources, Vectors, and Priorities................................... ...... ............................4-1

5-1 87C196CB Input/Output Ports......................................................................................5-1

6-1 A/D Converter Pins.................................... ............................................................. ......6-1

7-1 CAN Controller Signals.................................................................................................7-3

7-2 Control and Status Registers .......................................................................................7-3

7-3 CAN Controller Address Map.......................................................................................7-5

7-4 Message Object Structure............................................................................................7-6

7-5 Effect of Masking on Message Identifiers.....................................................................7-7

7-6 Standard Message Frame................................................................ ..... ...... .................7-8

7-7 Extended Message Frame...........................................................................................7-8

7-8 CAN Protocol Bit Time Segments ..............................................................................7-10

7-9 CAN Controller Bit Time Segments............................................................................7-11

7-10 Bit Timing Relationships.............................................................................................7-12

7-11 Bit Timing Requirements for Synchronization............................ ...... ..... .....................7-17

7-12 Control Register Bit-pair Interpretation.......................................................................7-23

7-13 Cross-reference for Register Bits Shown in Flowcharts.............................................7-35

7-14 Register Values Following Reset................................................................................7-41

9-1 Modes 0 and 3 Timing Comparisons............................................................................9-1

10-1 Signature Word and Programming Voltages..............................................................10-1

10-2 Slave Programming Mode Memory Map............................... .....................................10-2

10-3 Auto Programming Memory Map................................................................................10-2

10-4 Serial Port Programming Mode Memory Map............................................................10-4

A-1 87C196CB Signals Arranged by Functional Categories..............................................A-1

A-2 Description of Columns of Table A-3...........................................................................A-4

A-3 Signal Descriptions......................................................................................................A-4

A-4 Definition of Status Symbols .....................................................................................A-14

A-5 87C196CB Pin Status...............................................................................................A-14

vii

Guide to This Manual

CHAPTER 1

GUIDE TO THIS MANUAL

This document is a supplement to the 8XC196NT Microcontroller User’s Manual. It describes the differences between the 87C196CB and the 8XC196NT. For information not found in this supplement, please consult the 8XC196NT Microcontroller User’s Manual (order number

272317) or the 87C196CB datasheet (87C196CA/87C196CB 20 MHz Advanced 16-Bit CHMOS Microcontroller with Integrated CAN 2.0, order number 272405).

1.1 MANUAL CONTENTS

This supplement contains several chapters, an appendix, a glossary, and an index. This chapter, Chapter 1, provides an overview of the supplement. This section summarizes the contents of the remaining chapters and appendixes. The remain der of this chapter provides references to related documentation.

Chapter 2 — Architectural Overview — compares the features of the 87C196CB with those of the 8XC196NT and describes the 87C196CB’s internal clock circuitry.

Chapter 3 — Memory Partitions — describes the addressable memory space of the 84 -pin and 100-pin 87C196CB, lists the peripheral special-function registers (SFRs), and provides tables of WSR values for windowing higher memory into the lower register file for direct access.

Chapter 4 — Standard and PTS Interrupts — describes the additional interrupts for the CAN (controller area network) peripheral and the SFRs that support those interrupts.

Chapter 5 — I/O Ports — describes the port 0 and EPORT differences for the 100-pin 87C196CB. Both port 0 and the EPORT are implemented as eight-bit ports on the 100-pin 87C196CB, but as four-bit ports (like the 8XC196NT) on the 84-pin 87C196CB.

Chapter 6 — Analog-to-digital ( A/D) Converter — illustrates the SFRs that are affected by the implementation of port 0 as an eight-bit port.

Chapter 7 — CAN Serial Communications Controller — describes the 87C196CB’s integrated CAN controller and explains how to configure it. This integrated periphera l is similar to Intel’s standalone 82527 CAN serial communications controller, supporting both the standard and extended message frames specified by the CAN 2.0 protocol parts A and B.

Chapter 8 — Special Operating Modes — illustrates the clock control circuitry of the 87C196CB.

1-1

87C196CB SUPPLEMENT

Chapter 9 — Interfacing with External Memory — discusses differenc es in the bus timing modes supported by the 8XC196NT and the 87C196CB.

Chapter 10 — Programming the Nonvola tile Memory — describes the memory maps and rec-

ommended circuits to support programmi ng of the 87C196CB’s 56 Kbytes of OTPROM.

Appendix A — Signal Descriptions — describes the additional signals implemented on the 87C196CB.

Glossary — defines terms with special me aning used througho ut this supplement. Index — lists key topics with page number referenc es .

1.2 RELATED DOCUMENTS

Table 1-1 lists additional documents that you may find useful in desig ning systems incorporating the 87C196CB microcontroller.

T able 1-1. Related Documents

Title and Description Order Number

8XC196NT Microcontroller User’s Manual Automotive Products 87C196C B 20 MHz Advanced 1 6-Bit CHM OS Microcontroller with

Integrated CAN 2.0 (

handbook 231792

datasheet)

272317

272405

1-2

Architectural Overview

CHAPTER 2

ARCHITECTURAL OVERVIEW

This chapter describes architectural differences between the 87C196CB and the 8XC196NT. Both the 8XC196NT and the 87C196CB are designed for high-speed calculations and fast I/O. With the addition of the CAN (controller area network ) peripheral, the 8 7C196CB reduces pointto-point wiring requirements, making it well-suited to automotive and factory automation applications.

The 87C196CB is available in eith er an 84-p in or a 100-pin p ackage. Th e 84-pin 8 7C196CB, like the 8XC196NT, has up to 2 0 external address lines, enabling access to 1 Mbyte of linear add ress space. The 100-pin 87C196CB has four additional pin s available for ex ternal add ress lines. With all 24 external address lines connected, the 100-pin 87C196CB can access 16 Mbytes of linear address space.

2.1 DEVICE FEATURES

Table 2-1 lists the features of the 8XC196NT and the 87C196CB. The 87C196CB implements more OTPROM, more register RAM, four additional A/D channels, and the CAN peripheral. The 100-pin 87C196CB also implements four additional EPORT pins.

Table 2-1. Features of the 8XC196NT and 87C196CB

8XC196NT 68 0 or 32 K 1 K 512 56 10 2 4 1 4 0 87C196CB 84 56 K 1.5 K 512 56 10 2 8 1 4 2 87C196CB 100 56 K 1.5 K 512 60 10 2 8 1 8 2

†

2-1

87C196CB SUPPLEMENT

2.2 BLOCK DIAGRAM

Figure 2-1 shows the major blocks within the device. The 8XC196NT and 87C196CB have the same peripheral set with the exception of the CAN (controller area network) periphe ral, which is unique to the 87C196CB. The CAN peripheral manages communications between multiple network nodes. This integrated periph eral is similar to Intel’s standalon e 82527 CAN serial communications controller, supporting both the standard and extended message frames specified by the CAN 2.0 protocol parts A and B.

Core

Clock and

Power Mgmt.

SSIO

OTPROM

Code/Data

RAM

EPAI/O

A/DSIO

Interrupt

Controller

PTS

WDT

Slave

Port

CAN

A3179-01

Figure 2-1. 87C196CB Block Diagram

2.3 INTERNAL TIMING

The 87C196CB’s clock circuitry ( Figure 2-2 ) implements phase-locked loop and clock multiplier circuitry, which can substantially increase the CPU clock rate while using a lower-frequency input clock. The clock circuitry accepts an input clock signal on XTAL1 provided by an external crystal or oscillator. Depending on the value of the PLLEN pin, this frequency is routed either through the phase-locked loop and multiplier or directly to the divide-by-two circuit. The multiplier circuitry can quadruple the inpu t frequency (F

) before the frequency (f) reache s the di-

XTAL1

vide-by-two circuitry. The clock generators accept the divided input frequency (f/2) from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2. These signals are active when high.

2-2

NOTE

This manual uses lowercase “f” to represent the internal clock frequency. For the 87C196CB, f is equal to either F

XTAL1

or 4F

, depending on the clock

XTAL1

multiplier mode, which is controlled by the PLLEN input pin.

XTAL1

Disable

PLL

(Powerdown)

ARCHITECTURAL OVERVIEW

Phase

Comparator

Filter

Phase-

locked

Oscillator

Phase-locked Loop

Clock Multiplier

Peripheral Clocks (PH1, PH2) CLKOUT CPU Clocks (PH1, PH2)

A3168-01

XTAL2

PLLEN

Disable

Oscillator

(Powerdown)

XTAL1

Disable Clock Input

(Powerdown)

Divide-by-two 

Circuit

f

Clock

Generators

Disable Clocks

(Powerdown)

Disable Clocks

(Idle, Powerdown)

Figure 2-2. Clock Circuitry

The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock circuitry routes separate internal clock signals to the CPU and the peripher als to provid e flexibility in power management. It also outputs the CLKOUT signal on the CLKOUT pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal. This delay varies with temperature and voltage.

2-3

87C196CB SUPPLEMENT

XTAL1

PH1

PH2

CLKOUT

1 State Time

Phase 1 Phase 2

A0805-01

Figure 2-3. Internal Clock Phases

The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies.

Table 2-2. State Times at Various Frequencies

(Frequency Input to th e

Divide-by-two Circuit)

State Time

8 MHz 250 ns 12 MHz 167 ns 16 MHz 125 ns 20 MHz 100 ns

The following formulas calculate the freq uency of PH1 and PH2, the d uration of a state time, and the duration of a clock period (t).

P H1 (in MHz)

-- - PH2== State Time (in µs) 2

-- -= t f

-- -=

Because the device can operate at many frequencies, this manual defines time requir ements (such as instruction execution times) in terms of state times rather than specific measurements. Datasheets list AC characteristics in terms of clock periods (t; sometimes called T

osc

Figure 2-4 illustrates the timing relationships between the input freq uency (F

), the operating

XTAL1

frequency (f), and the CLKOUT signal with each PLLEN pin conf iguration. Ta ble 2-3 details the relationships between the input frequency (F

), the PLLEN pin, the operating frequency (f),

XTAL1

the clock period (t), and state times.

2-4

XTAL1 (5 MHz)

CLKOUT

XTAL1 (5 MHz)

CLKOUT

ARCHITECTURAL OVERVIEW

PLLEN = 0

t = 80ns



XHCH

PLLEN = 1

t = 20ns

XHCH

A3170-01

Figure 2-4. Effect of Clock Mode on CLKOUT Frequency

Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times

XTAL1

(Frequency

on XTAL1)

PLLEN Multiplier

(Input Frequency to

the Divide-by-two Circui t)

4 MHz 0 1 4 MHz 250 ns 500 ns 5 MHz 0 1 5 MHz 200 ns 400 ns

8 MHz 0 1 8 MHz 125 ns 250 ns 12 MHz 0 1 12 MHz 83.5 ns 167 ns 16 MHz 0 1 16 MHz 62.5 ns 125 ns 20 MHz 0 1 20 MHz 50 ns 100 ns

4 MHz 1 4 16 MHz 62.5 ns 125 ns

5 MHz 1 4 20 MHz 50 ns 100 ns

(Clock

Period)

State Time

2-5

Memory Partitions

CHAPTER 3

MEMORY PARTITIONS

This chapter describes the differences in the address space of the 87C196CB from that of the 8XC196NT. The 87C196CB has 56 Kbytes of one-time-programmable read-only memory (OTPROM), while the 8XC196NT is available with 32 Kbytes. The 87C196CB also has an additional 512 bytes of register RAM.

The 87C196CB is available in eith er an 84-p in or a 100-pin p ackage. Th e 84-pin 8 7C196CB, like the 8XC196NT, has up to 2 0 external address lines, enabling access to 1 Mbyte of linear add ress space. The 100-pin 87C196CB has four additional pin s available for ex ternal add ress lines. With all 24 external address lines connected (A23:16 and AD15:0), the 100-pin 87 C196CB can access 16 Mbytes of linear address space.

3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING

Table 3-1 compares the register file addresses of the 8XC196NT and 87C196CB. Table 3-2 is a memory map of the 87C196CB. Table 3-3 lists the 87C196CB’s peripheral SFRs (these are the same as those of the 8XC196NT). Table 3-4 lists the CAN peripheral SFRs, which are unique to the 87C196CB. Tables 3-5 through 3-9 provide the information necessary to window higher memory into the lower register file for direct access.

Table 3-1. Register File Memory Addresses

Device and Hex

Address Range

CB NT

1DFF 1C00

03FF 0100

00FF 001A

0019 0018

0017 0000

. .

— Register RAM Indirect, indexed, or windowed direct

03FF 0100

00FF 001A

0019 0018

0017 0000

Upper register file (register RAM) Indirect, indexed, or windowed direct

Lower register file (register RAM) Direct, indirect, or indexed

Lower register file (stack pointer) Direct, indirect, or indexed

Lower register file (CPU SFRs) Direct, indirect, or indexed

Description Addressing Modes

3-1

87C196CB SUPPLEMENT

Table 3-2. 87C196CB Memory Map

Hex

Address

FFFFFF

FF2080 FF207F

FF2000

FF1FFF

FF0600

FF05FF FF0400

FF03FF FF0100

FF00FF FF0000

FEFFFF

0F0000

0EFFFF

010000

00FFFF

002000

001FFF 001FE0

001FDF

001F00

001EFF 001E00

001DFF

001C00 001BFF

000600

0005FF

000400

0003FF

000100

0000FF

000000

†

For the 87C196CB, the program and special-purpose memory locations (FF2000-FFF FFFH) can reside

Program memory (After a device reset, the first instruction fetch is from FF2080H)

Special purpose memory

External device (memory or I/O) connected to address/data bus Indirect, indexed, extended Internal code and data RAM

(mapped identically into pages FFH and 00H) External device (memory or I/O) connected to address/data bus Indirect, indexed, extended

Reserved

††

100-pin 87C196CB: External device (memory or I/O) 84-pin 87C196CB: Overlaid memory

External device (memory or I/O) connected to address/data bus Indirect, indexed, extended

External device or remapped OTPROM

Memory-mapped SFRs Indirect, indexed, extended

Peripheral SFRs

CAN SFRs Indirect, indexed, extended

Internal register RAM External device (memory or I/O) connected to address/data bus;

future SFR expansion Internal code and data RAM

(mapped identically into pages 00H and FFH) Upper register file (register RAM)

Lower register file (register RAM, stack pointer, CPU SFRs) Direct, indirect, indexed

either in external memory or in internal OTPROM.

††

Locations xF0000-xF00FFH are reserved for in-circuit emulator s. Do not use these locations except to initialize them. Except as otherwise noted, initialize unused program memory locations and reserved memory locations to FFH.

†††

These locations can be either external memory (CCB2.2=0) or a copy of the OTPROM (CCB2.2=1).

Description Addressing Modes

†

Indirect, indexed, extended

††

†††

Indirect, indexed, extended

Indirect, indexed, extended,

windowed direct

Indirect, indexed,

windowed direct

Indirect, indexed, extended

Indirect, indexed,

windowed direct

3-2

MEMORY PARTITIONS

Table 3-3. 87C196CB Peripheral SFRs

Ports 0, 1, 2, and 6 SFRs Timer 1, Timer 2, and EPA SFRs

Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte

1FDEH Reserved Reserved 1FDCH Reserved Reserved 1F9CH Reserved T2CON TROL 1FDAH Reserved P0_PIN

1FD8H Reserved Reserved 1F98H Reserved T1CONTROL 1FD6H P6_PIN P1_P IN 1F96H Reserved Reserved 1FD4H P6_REG P1_REG 1F94H Reserved Reserved 1FD2H P6_DIR P1_DIR 1F92H Reserved Reserved

1FD0H P6_MODE P1_MODE 1F90H Reserved Reserved 1FCEH P2_PIN Reserved EPA SFRs 1FCCH P2_REG Reserved 1FCAH P2_DIR Reserved

1FC8H P2_MODE Reserved 1F8CH Reserved COMP1_CON

1FC6H Reserved Reserved

1FC4H Reserved Reserved 1F88H Reserved COMP0_CON

1FC2H Reserved Reserved

1FC0H Reserved Reserved 1F84H Reserved EPA9_CON

SIO and SS IO SFRs

Address High (Odd) Byte Low (Even) Byte

1FBEH Reserved Reserved 1FBCH SP_BAUD (H) SP_BAUD (L) 1F7CH Reserved EPA7_CON

1FBAH SP_CON SBUF_TX

1FB8H SP_STATUS SBUF_RX 1F78H Reserved EPA6_CON

1FB6H Reserved Reserved

1FB4H Reserved SSIO_BAUD 1F74H Reserved EP A5_CON

1FB2H SSIO1_CON SSIO1_BUF

1FB0H SSIO0_CON SSIO0_BUF 1F70H Reserved EPA4_CON

A/D SFRs

Address High (Odd) Byte Low (Even) Byte

1FAEH AD_TIME AD_TEST 1FACH Reserved AD_COMMAND 1F68H Reserved EPA2_CON

1FAAH AD_RESULT (H) AD_RESULT (L)

EPA Interrupt SFRs

Address High (Odd) Byte Low (Even) Byte

1FA8H Reserved EPAIPV 1F60H Reserved EPA0_CON

1FA6H Reserved EPA_PEND1

1FA4H Reserved EPA_MASK1

†

1FA2H EPA_PEND (H) EPA_PEND (L)

†

1FA0H EP A_M AS K (H) EP A_M ASK (L)

†

Must be addressed as a word .

†

1F9EH TIMER2 (H) TIMER2 (L)

†

1F9AH TIMER1 (H) TIMER1 (L)

Address High (Odd) Byte Low (Even) Byte

†

1F8EH COMP1_TIME (H) COMP 1_TI M E (L)

†

1F8AH COMP0_TIME (H) COMP 0_TI M E (L)

†

1F86H EPA9_TIME (H) EPA9_TIME (L)

†

1F82H EPA8_TIME (H) EPA8_TIME (L)

1F80H Reserved EPA8_CON

†

1F7EH EPA7_TIME (H) EPA7_TIME (L)

†

1F7AH EPA6_TIME (H) EPA6_TIME (L)

†

1F76H EPA5_TIME (H) EPA5_TIME (L)

†

1F72H EPA4_TIME (H) EPA4_TIME (L)

†

1F6EH EPA3_TIME (H) EPA3_TIME (L)

†

1F6CH EPA3_CON (H) EPA3_CON (L)

†

1F6AH EPA2_TIME (H) EPA2_TIME (L)

†

1F66H EPA1_TIME (H) EPA1_TIME (L)

†

1F64H EPA1_CON (H) EPA1_CON (L)

†

1F62H EPA0_TIME (H) EPA0_TIME (L)

3-3

87C196CB SUPPLEMENT

Table 3-4. CAN Peripheral SFRs

Message 15 Message 11

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1EFEH Reserved CAN_MSG15DATA7 1EBEH Reserved CAN_MSG11DATA7 1EFCH CAN_MSG15DATA6 CAN_MSG15DATA5 1EBCH CAN_MSG11DATA6 CAN_MSG11DATA5 1EFAH CAN_MSG15DATA4 CAN_MSG15DATA3 1EBAH CAN_MSG11DATA4 CAN_MSG11DATA3

1EF8H CAN_MSG15DATA2 CAN_MSG15DATA1 1EB8H CAN_MSG11DATA2 CAN_MSG11DATA1 1EF6H CAN_MSG15DATA0 CAN_MSG15CFG 1EB6H CAN_MSG11DATA0 CAN_MSG11CFG 1EF4H CAN_MSG15ID3 CAN_MSG15ID2 1EB4H CAN_MSG11ID3 CAN_MSG11ID2 1EF2H CAN_MSG15ID1 CAN_MSG15ID0 1EB2H CAN_MSG11ID1 CAN_MSG11ID0 1EF0H CAN_MSG15CON1 CAN_MSG15CON0 1EB0H CAN_MSG11CON1 CAN_MSG11CON0

Message 14 Message 10

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1EEEH Reserved CAN_MSG14DATA7 1EAEH Reserved CAN_MSG10DATA7 1EECH CAN_MSG14DATA6 CAN_MSG14DATA5 1EACH CAN_MSG10DATA6 CAN_MSG10DATA5 1EEAH CAN_MSG14DATA4 CAN_MSG14DATA3 1EAAH CAN_MSG10DATA4 CAN_MSG10DATA3

1EE8H CAN_MSG14DATA2 CAN_MSG14DATA1 1EA8H CAN_MSG10DATA2 CAN_MSG10DATA1 1EE6H CAN_MSG14DATA0 CAN_MSG14CFG 1EA6H CAN_MSG10DATA0 CAN_MSG10CFG 1EE4H CAN_MSG14ID3 CAN_MSG14ID2 1EA4H CAN_MSG10ID3 CAN_MSG10ID2 1EE2H CAN_MSG14ID1 CAN_MSG14ID0 1EA2H CAN_MSG10ID1 CAN_MSG10ID0 1EE0H CAN_MSG14CON1 CAN_MSG14CON0 1EA0H CAN_MSG10CON1 CAN_MSG10CON0

Message 13 Message 9

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1EDEH Reserved CAN_MSG13DATA7 1E9EH Reserved CAN_MSG9DATA7 1EDCH CAN_MSG13DATA6 CAN_MSG13DATA5 1E9CH CAN_MSG9D ATA6 CAN_MSG9DATA5 1EDAH CAN_MSG13DATA4 CAN_MSG13DATA3 1E9AH CAN_MSG9DATA4 CAN_MSG9DATA3 1ED8H CAN_MSG13DATA2 CAN_MSG13DATA1 1E98H CAN_MSG9DATA2 CAN_MSG9DATA1 1ED6H CAN_MSG13DATA0 CAN_MSG13CFG 1E96H CAN_MSG9DATA0 CAN_MSG9CFG 1ED4H CAN_MSG13ID3 CAN_MSG13ID2 1E94H CAN_MSG9ID3 CAN_MSG9ID2 1ED2H CAN_MSG13ID1 CAN_MSG13ID0 1E92H CAN_MSG9ID1 CAN_MSG9ID0 1ED0H CAN_MSG13CON1 CAN_MSG13CON0 1E90H CAN_MSG9CON1 CAN_MSG9CON0

Message 12 Message 8

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1ECEH Reserved CAN_MSG12DATA7 1E8EH Reserved CAN_MSG8DATA7 1ECCH CAN_MSG12DATA6 CAN_MSG12DATA5 1E8CH CAN_MSG8D ATA6 CAN_MSG8DATA5 1ECAH CAN_MSG12DATA4 CAN_MSG12DATA3 1E8AH CAN_MSG8DATA4 CAN_MSG8DATA3 1EC8H CAN_MSG12DATA2 CAN_MSG12DATA1 1E88H CAN_MSG8DATA2 CAN_MSG8DATA1 1EC6H CAN_MSG12DATA0 CAN_MSG12CFG 1E86H CAN_MSG8DATA0 CAN_MSG8CFG 1EC4H CAN_MSG12ID3 CAN_MSG12ID2 1E84H CAN_MSG8ID3 CAN_MSG8ID2 1EC2H CAN_MSG12ID1 CAN_MSG12ID0 1E82H CAN_MSG8ID1 CAN_MSG8ID0 1EC0H CAN_MSG12CON1 CAN_MSG12CON0 1E80H CAN_MSG8CON1 CAN_MSG8CON0

3-4

MEMORY PARTITIONS

Table 3-4. CAN Peripheral SFRs (Continued)

Message 7 Message 3 and Bit Timing 0

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1E7EH Reserved CAN_MSG7DATA7 1E3EH CAN_BT IM E0

1E7CH C AN_MSG7DATA6 CAN_MSG7DATA5 1E3CH CAN_MSG3DATA6 CAN_MSG3 D ATA5

1E7AH CAN_MSG7DATA4 CAN_MSG7DATA3 1E3AH CAN_MSG3DATA4 CAN_MSG3DATA3 1E78H CAN_MSG7DATA2 CAN_MSG7DATA1 1E38H CAN_MSG3DATA2 CAN_MSG3DATA1 1E76H CAN_MSG7DATA0 CAN_MSG7CFG 1E36H CAN_M SG3D ATA0 CAN_MSG3CFG 1E74H CAN_MSG7ID3 CAN_MSG7ID2 1E34H CAN_MSG3ID3 CAN_MSG3ID2 1E72H CAN_MSG7ID1 CAN_MSG7ID0 1E32H CAN_MSG3ID1 CAN_MSG3ID0 1E70H CAN_MSG7CON1 CAN_MSG7CON0 1E30 H CAN_MSG3CON1 CAN_MSG3CON0

Message 6 Message 2

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1E6EH Reserved CAN_MSG6DATA7 1E2EH Reserved CAN_MSG2DATA7

1E6CH CAN_MSG6DATA6 CAN_MSG6DATA5 1E2CH CAN_MSG2DATA6 CAN_MSG2DATA5

1E6AH CAN_MSG6DATA4 CAN_MSG6DATA3 1E2AH CAN_MSG2DATA4 CAN_MSG2DATA3 1E68H CAN_MSG6DATA2 CAN_MSG6DATA1 1E28H CAN_MSG2DATA2 CAN_MSG2DATA1 1E66H CAN_MSG6DATA0 CAN_MSG6CFG 1E26H CAN_MSG2DATA0 CAN_MSG2CFG 1E64H CAN_MSG6ID3 CAN_MSG6ID2 1E24H CAN_MSG2ID3 CAN_MSG2ID2 1E62H CAN_MSG6ID1 CAN_MSG6ID0 1E22H CAN_MSG2ID1 CAN_MSG2ID0 1E60H CAN_MSG6CON1 CAN_MSG6CON0 1E20H CAN_MSG2CON1 CAN_MSG2CON0

Message 5 and Interrupts Message 1

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1E5EH CAN_INT CAN_MSG5DATA7 1E1EH Reserved CAN_MSG1DATA7

1E5CH CAN_MSG5DATA6 CAN_MSG5DATA5 1E1CH CAN_MSG1DATA6 CAN_MSG1DATA5

1E5AH CAN_MSG5DATA4 CAN_MSG5DATA3 1E1AH CAN_MSG1DATA4 CAN_MSG1DATA3 1E58H CAN_MSG5DATA2 CAN_MSG5DATA1 1E18H CAN_MSG1DATA2 CAN_MSG1DATA1 1E56H CAN_MSG5DATA0 CAN_MSG5CFG 1E16H CAN_MSG1DATA0 CAN_MSG1CFG 1E54H CAN_MSG5ID3 CAN_MSG5ID2 1E14H CAN_MSG1ID3 CAN_MSG1ID2 1E52H CAN_MSG5ID1 CAN_MSG5ID0 1E12H CAN_MSG1ID1 CAN_MSG1ID0 1E50H CAN_MSG5CON1 CAN_MSG5CON0 1E10H CAN_MSG1CON1 CAN_MSG1CON0

Message 4 and Bit Timing 1 Mask, Control, and Status

Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte

1E4EH CAN_BTIME1

1E4CH CAN_MSG4DATA6 CAN_MSG4DATA5 1E0CH CAN_MSK15 CAN_MSK15

1E4AH CAN_MSG4DATA4 CAN_MSG4DATA3 1E0AH CAN_EGMSK CAN_EGMSK 1E48H CAN_MSG4DATA2 CAN_MSG4DATA1 1E08H CAN_EGMSK CAN_EGMSK 1E46H CAN_MSG4DATA0 CAN_MSG4CFG 1E06H CAN_SGMSK CAN_SGMSK 1E44H CAN_MSG4ID3 CAN_MSG4ID2 1E04H Reserved Reserved 1E42H CAN_MSG4ID1 CAN_MSG4ID0 1E02H Reserved Reserved 1E40H CAN_MSG4CON1 CAN_MSG4CON0 1E00H CAN_STAT CAN_CON

†

The CCE bit in the control register (CAN_CON) must be set to enable write access to the bit timing registers

(CAN_BTIME0 and CAN_BTIME1).

†

CAN_MSG4DATA7 1E0EH CAN_MSK15 CAN_MSK15

†

CAN_MSG3DATA7

†

3-5

87C196CB SUPPLEMENT

Table 3-5. Selecting a Window of Peripheral SFRs

Peripheral

Ports 0, 1, 2, 6 7EH 3FH

EPA compare 0–1, capture/compare 8–9, timers 7CH EPA capture/compare 0–7 7BH 3DH 1EH CAN messages 14–15 77H CAN messages 12–13 76H CAN messages 10–11 75H CAN messages 8–9 74H CAN messages 6–7 73H CAN messages 4–5, bit timing 1, interrupts 72H CAN messages 2–3, bit timing 0 71H CAN message 1, control, status, mask 70H

WSR Value for

32-byte Window

(00E0–00FFH)

WSR Value for

64-byte Window

(00C0–00FFH)

3EH

3BH

3AH

39H

38H

WSR Value for

128-byte Window

(0080–00FFH)

1FHA/D converter, EPA interrupts 7DH

1DH

1CH

3-6

Table 3-6. Selecting a Window of the Upper Register File

Locations

03E0–03FFH 5FH 03C0–03DFH 5EH 03A0–03BFH 5DH 0380–039FH 5CH 0360–037FH 5BH 0340–035FH 5AH 0320–033FH 59H 0300–031FH 58H 02E0–02FFH 57H 02C0–02DFH 56H 02A0–02BFH 55H

0260–027FH 53H 0240–025FH 52H 0220–023FH 51H

01E0–01FFH 4FH 01C0–01DFH 4EH 01A0–01BFH 4DH

0160–017FH 4BH 0140–015FH 4AH 0120–013FH 49H

WSR Value

for 32-byte Window

(00E0–00FFH)

WSR Value

for 64-byte Window

(00C0–00FFH)

2FH

2EH

2DH

2CH

2BH

2AH0280–029FH 54H

29H

28H0200–021FH 50H

27H

26H0180–019FH 4CH

25H

24H0100–011FH 48H

MEMORY PARTITIONS

WSR Value

for 128-byte Window

(0080–00FFH)

17H

16H

15H

14H

13H

12H

3-7

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