Intel 830 User Manual

Intel® Pentium® D Processor 800Δ Sequence

Datasheet

– On 90 nm Process in the 775-land LGA Package and supporting

February 2006

Intel

Extended Memory 64 Technology

Document Number: 307506-003

Contents

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT , COP YRIGHT O R OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.

Intel may make changes to specifications and product descripti ons at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflict s or inco mpatibilities arising from future changes to them.

The Intel specifications. Current characterized errata are available on request.

different processor families. Over time processor numbers will increment based on changes in clock speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See http://www.intel.com/products/processor_number for details.

drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including details on which processors support EM64T or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a support ing operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its

Pentium® D processor may contain design defects or errors known as errata which may cause the product to deviate from published

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device

2 Datasheet

Contents

1 Introduction....................................................................................................................................11

1.1 Terminology........................................................................................................................12

1.1.1 Processor Packaging Terminology........................................................................12

1.2 References .........................................................................................................................13

2 Electrical Specifications................ .... ... ... ... ... .... ... .......................................... ... ... ..........................15

2.1 Power and Ground Lands...................................................................................................15

2.2 Decoupling Guidelines........................................................................................................15

2.2.1 VCC Decoupling ....................................................................................................15

2.2.2 VTT Decoupling.....................................................................................................15

2.2.3 FSB Decoupling.....................................................................................................16

2.3 Voltage Identification ..........................................................................................................16

2.4 Reserved, Unused, FC and TESTHI Signals......................................................................18

2.5 Voltage and Current Specifications ....................................................................................19

2.5.1 Absolute Maximum and Minimum Ratings.............................................................19

2.5.2 DC Voltage and Current Specifications .................................................................19

2.5.3 VCC Overshoot Specification ................................................................................25

2.5.4 Die Voltage Validation ...........................................................................................26

2.6 Signaling Specifications......................................................................................................26

2.6.1 FSB Signal Groups................................................................................................26

2.6.2 GTL+ Asynchronous Signals.................................................................................28

2.6.3 FSB DC Specifications ..........................................................................................29

2.7 Clock Specifications........ ... .................................................................................................32

2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................32

2.7.2 FSB Frequency Select Signals..............................................................................32

2.7.3 Phase Lock Loop (PLL) and Filter .........................................................................33

3 Package Mechanical Specifications ..............................................................................................35

3.1 Package Mechanical Drawing ............................................................................................35

3.2 Processor Component Keep-Out Zones.............................................................................39

3.3 Package Loading Specifications.........................................................................................39

3.4 Package Handling Guidelines.............................................................................................39

3.5 Package Insertion Specifications........................................................................................40

3.6 Processor Mass Specification.............................................................................................40

3.7 Processor Materials............................................................................................................40

3.8 Processor Markings............................................................................................................40

3.9 Processor Land Coordinates ..............................................................................................42

4 Land Listing and Signal Descriptions ............................................................................................43

4.1 Processor Land Assignments.............................................................................................43

4.2 Alphabetical Signals Reference..........................................................................................66

5 Thermal Specifications and Design Considerations......................................................................75

5.1 Processor Thermal Specifications ......................................................................................75

5.1.1 Thermal Specifications ..........................................................................................75

5.1.2 Thermal Metrology.................................................................................................79

Datasheet 3

Contents

5.2 Processor Thermal Features.................... ... ... ... .......................................... .... ... ... ... ... .... ...79

5.2.1 Thermal Monitor.............................. ... ... .......................................... .... ... ... .............79

5.2.2 On-Demand Mode.................................................................................................80

5.2.3 PROCHOT# Signal................................................................................................80

5.2.4 FORCEPR# Signal Pin..........................................................................................81

5.2.5 THERMTRIP# Signal.............................................................................................82

5.2.6 T

CONTROL

and Fan Speed Reduction....................................................................82

5.2.7 Thermal Diode......... .... ... ... ... ... .... ... ... ... .................................................................82

6 Features ........................................................................................................................................85

6.1 Power-On Configuration Options................................. ... .... ... ... ... ... .... ... ... ..........................85

6.2 Clock Control and Low Power States.................................................................................85

6.2.1 Normal State................................... .......................................................................86

6.2.2 HALT and Enhanced HALT Powerdown States ....................................................86

6.2.3 Stop-Grant State................................ ... .... ... ... ... .... ... ... ... .......................................87

6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State......................88

6.2.5 Enhanced Intel SpeedStep

Technology ..............................................................88

7 Boxed Processor Specifications....................................................................................................89

7.1 Mechanical Specifications ..................................................................................................90

7.1.1 Boxed Processor Cooling Solution Dimensions ....................................................90

7.1.2 Boxed Processor Fan Heatsink Weight.................................................................91

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly.......91

7.2 Electrical Requirements......................................................................................................91

7.2.1 Fan Heatsink Power Supply ..................................................................................91

7.3 Thermal Specifications .......................................................... ... ... ... .... ... ... ... .... ...................93

7.3.1 Boxed Processor Cooling Requirements...............................................................93

7.3.2 Variable Speed Fan...............................................................................................95

8 Balanced Technology Extended (BTX) Type I Boxed Processor Specifications...........................97

8.1 Mechanical Specifications ..................................................................................................98

8.1.1 Cooling Solution Dimensions.................................................................................98

8.1.2 Boxed Processor Fan Heatsink Weight.................................................................98

8.1.3 Boxed Processor Support and Retention Module (SRM) ......................................99

8.2 Electrical Requirements......................................................................................................99

8.2.1 Fan Heatsink Power Supply ..................................................................................99

8.3 Thermal Specifications .......................................................... ... ... ... .... ... ... ... .... .................101

8.3.1 Boxed Processor Cooling Requirements.............................................................101

8.3.2 Variable Speed Fan.............................................................................................102

9 Debug Tools Specifications....... ... ... .... ... ... .......................................... ... ... ..................................105

9.1 Logic Analyzer Interface (LAI) ..........................................................................................105

9.1.1 Mechanical Considerations..................................................................................105

9.1.2 Electrical Considerations.....................................................................................105

4 Datasheet

Contents

Figures

2-1 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor............22

2-2 VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor............24

2-3 VCC Overshoot Example Waveform ..........................................................................................25

2-4 Phase Lock Loop (PLL) Filter Requirements . .............................................................................34

3-1 Processor Package Assembly Sketch........................................................................................35

3-2 Processor Package Drawing 1 ...................................................................................................36

3-3 Processor Package Drawing 2 ...................................................................................................37

3-4 Processor Package Drawing 3 ...................................................................................................38

3-5 Processor Top-Side Marking Example (Intel 3-6 Processor Top-Side Marking Example (Intel

3-7 Processor Land Coordinates, Top View.....................................................................................42

4-1 Landout Diagram (Top View – Left Side)....................................................................................44

4-2 Landout Diagram (Top View – Right Side).................................................................................45

5-1 Thermal Profile for the Pentium D Processor with PRB=1 ................................... ... ... ... ... .... ......77

5-2 Thermal Profile for the Pentium D Processor with PRB=0 ................................... ... ... ... ... .... ......78

5-3 Case Temperature (TC) Measurement Location........................................................................79

6-1 Processor Low Power State Machine.........................................................................................86

7-1 Mechanical Representation of the Boxed Processor..................................................................89

7-2 Side View Space Requirements for the Boxed Processor (Applies to all four side views).........90

7-3 Top View Space Requirements for the Boxed Processor...........................................................90

7-4 Overall View Space Requirements for the Boxed Processor .................................. ... ... ... .... ... ...91

7-5 Boxed Processor Fan Heatsink Power Cable Connector Description........................................92

7-6 Baseboard Power Header Placement Relative to Processor Socket .........................................93

7-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)........................94

7-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)........................94

7-9 Boxed Processor Fan Heatsink Set Points.................................................................................95

8-1 Mechanical Representation of the Boxed Processor..................................................................97

8-2 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes ..........98

8-3 Assembly Stack Including the Support and Retention Module...................................................99

8-4 Boxed Processor Fan Heatsink Power Cable Connector.........................................................100

8-5 Balanced Technology Extended (BTX) Mainboard Power Head er Placement (hatched area) 101

8-6 Boxed Processor TMA Set Points ....................................................... .... ... ... ... .... ... ... ... ...........102

Pentium® D Processors 840, 830, 820).......... ...40

Pentium® D Processor 805)...............................41

Datasheet 5

Contents

Tables

1-1 References .................................................................................................................................13

2-1 Voltage Identification Definition ..................................................................................................17

2-2 Processor DC Absolute Maximum Ratings ................................................................................19

2-3 Voltage and Current Specifications ............................................................................................20

2-4 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor ...........21

2-5 VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor ...........23

2-6 VCC Overshoot Specifications ............................................................ ... .... ... ... ... .... ... ................25

2-7 FSB Signal Groups.....................................................................................................................27

2-8 Signal Characteristics.................................................................................................................28

2-9 Signal Reference Voltages.........................................................................................................28

2-10BSEL[2:0] and VID[5:0] Signal Group DC Specifications...........................................................29

2-11GTL+ Signal Group DC Specifications .......................................................................................29

2-12PWRGOOD Input and TAP Signal Group DC Specifications.....................................................30

2-13GTL+ Asynchronous Signal Group DC Specifications ...............................................................30

2-14VTTPWRGD DC Specifications..................................................................................................31

2-15BOOTSELECT and MSID[1:0] DC Specifications......................................................................31

2-16GTL+ Bus Voltage Definitions ....................................................................................................31

2-17Core Frequency to FSB Multiplier Configuration. ... ... .... .......................................... ... ... .............32

2-18BSEL[2:0] Frequency Table for BCLK[1:0].................................................................................33

3-1 Processor Loading Specifications ..............................................................................................39

3-2 Package Handling Guidelines ....................................................................................................39

3-3 Processor Materials....................................................................................................................40

4-1 Alphabetical Land Assignments .................................................................................................46

4-2 Numerical Land Assignment......... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... .......................................56

4-3 Signal Description.......................................................................................................................66

5-1 Processor Thermal Specifications..............................................................................................76

5-2 Thermal Profile for the Pentium D Processor with PRB=1 .........................................................77

5-3 Thermal Profile for the Pentium D Processor with PRB=0 .........................................................78

5-4 Thermal Diode Parameters ........................................................................................................82

5-5 Thermal Diode Interface.............................................................................................................83

6-1 Power-On Configuration Option Signals.....................................................................................85

7-1 Fan Heatsink Power and Signal Specifications..........................................................................92

7-2 Fan Heatsink Power and Signal Specifications..........................................................................95

8-1 Fan Heatsink Power and Signal Specifications........................................................................100

8-2 Balanced Technology Extended (BTX) Type I Boxed Processor TMA Set Points for

3-wire Operation........................... .... ... ... ... ... .... ... ... ..................................................................102

6 Datasheet

Revision History

Contents

Revision

Number

-001 • Initial release May 2005

-002

-003

• Added Balanced Technology Extended (BTX) Type I Boxed Processor Specifications chapter.

• Added Intel

• Updated THERMTRIP# signal description in Table 4-3.

Pentium® D processor 805 specifications.

Description Date

October 2005

February 2006

Datasheet 7

Contents

8 Datasheet

Intel® Pentium® D Processor 800 Sequence Features

Contents

• Available at 3.20 GHz, 3 GHz, 2.80 GHz, and

2.66 MHz

• Enhanced Intel Speedstep

D processor 840 and 830 only)

• Supports Intel

(Intel

EM64T)

Extended Memory 64 Technology

Technology (Pentium

• Supports Execute Disable Bit capability

• Binary compatible with applications run ning on

previous members of the Intel microprocessor line

• Intel NetBurst

microarchitecture

• FSB frequency at 800 MHz (Pentium D Processors

840, 830 and 820 only)

• FSB frequency at 533 MHz (Pentium D Processor

805 only)

• Hyper-Pipelined Technology

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

The Intel® Pentium® D processor delivers Intel's advanced, powerful processors for desktop PCs that are based on the Intel NetBurst applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.

microarchitecture. The Pentium D processor is designed to deliver performanc e across

• Optimized for 32-bit applications run ning on

advanced 32-bit operating systems

• Two 16-KB Level 1 data caches

• Two 1 MB Advanced Transfer Caches (on-die,

full-speed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC)

• 144 Streaming SIMD Extensions 2 (SSE2)

instructions

• 13 Streaming SIMD Extensions 3 (SSE3)

instructions

• Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved

cache hit rate on load/store operations

• 775-land Package

Intel

Extended Memory 64 Technology (Intel® EM64T)Φ enables the Pentium D processor to execute operating systems and applications written to take advantage of the Intel EM64T. The Pentium D processor 840 and 830 supporting Enhanced Intel Speedstep consumption.

The Pentium D processor also includes the Execute Disable Bit capability . This fea ture, combined with a supported operating system, allows memory to be marked as executable or non-executable.

Datasheet 9

technology allows tradeoffs to be made between performance and power

Contents

10 Datasheet

1 Introduction

The Intel® Pentium® D processor extends Intel's Desktop dual-core product line. The Pentium D processor uses Flip-Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775land LGA socket, referred to as the LGA775 socket. The Pentium D processor, like the Intel Pentium 4 processor in the 775-land package, utilizes the Intel NetBurst maintains the tradition of compatibility with IA-32 software.

The Intel EM64T) This enhancement enables the processor to execute operating systems and applications written to take advantage of Intel EM64T. Further details on the 64-bit extension architecture and programming model can be found in the Intel Guide at http://developer.intel.com/technology/64bitextensions/.

Note: In this document the Pentium D processor 800 sequence is also referred to as the Pentium D

processor or simply as the processor. The Pentium D processor functions as two physical processors in one package. This allows a

duplication of execution resources to provide increased system responsiveness in multitasking environments, and headroom for next generation multithreaded applications and new usages.

Pentium® D processor supports Intel® Extended Memory 64 Technology (Intel®

as an enhancement to Intel's IA-32 architecture, on server and workstation platforms.

Introduction

microarchitecture and

64-bit Extension Technology Software Developer's

The Pentium D processor supports all the existing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Streaming SIMD Extensions 3 (SSE3) are 13 additional instructions that further extend the capabilities of Intel processor technology. These new instructions enhance the performance of optimized applications for the digital home such as video, image processing, and media compression technology.

The processor’s Intel NetBurst microarchitecture FSB uses a split-transaction, deferred reply protocol like the Intel Pentium 4 processor. The Intel NetBurst microarchitecture FSB uses SourceSynchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6.4 GB/s.

The Pentium D processor includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel Architecture Software Developer's Manual for more detailed information.

Intel will enable support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

The processor includes an address bus powerdown capability that removes power from the address and data pins when the FSB is not in use. This feature is always enabled on the processor.

Enhanced Intel SpeedStep power consumptions. This may lower average power consumption (in conjunction with OS support).

Technology allows trade-offs to be made between performance and

Datasheet 11

Introduction

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• Intel

• Processor — For this document, the term processor is the generic form of the Intel Pentium D

• Keep-out zone — The area on or near the processor that system design can not use.

• Intel

• Processor core — Processor core die with integrated L2 cache.

• FC-LGA4 package — The Pentium D processor is available in a Flip-Chip Land Grid Array

• LGA775 socket — The Pentium D processor mates with the system board through a surface

• Integrated heat spreader (IHS) — A component of the processor package used to enhance

• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical

• Storage conditions — Refers to a non-operational state. The processor may be installed in a

• Functional operation — Refers to normal operating conditions in which all processor

Pentium® D processor 800 sequence — Dual-core processor in the FC-LGA4

package with two 1-MB L2 caches.

processor 800 sequence.

945G/945GZ/945P/945PL Express Chipset Family — Chipset that supports DDR2

memory technology for the Pentium D processor.

955X Express Chipset — Chipset that supports DDR2 memory technology for the

Pentium D processor.

4 package, consisting of a processor core mounted on a substrate with an integrated heat spreader (IHS).

mount, 775-land, LGA socket.

the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.

platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

specifications, including DC, AC, system bus, signal quality, mechanical and thermal, are satisfied.

12 Datasheet

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document:

Table 1-1. References

Intel

Pentium® D Processor and Intel® Pentium® Processor Extreme

Edition 840 Thermal and Mechanical Design Guidelines

Intel

Pentium® Processor Extreme Edition and Intel® Pentium® D

Processor Specification Update Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775

Socket LGA775 Socket Mechanical Design Guide

Intel

Architecture Software Developer's Manual Volume 1: Basic Architecture, Document 253665 Volume 2A :Instruction Set Reference, A-M, Document 253666 Volume 2B: Instruction Set Reference, N-Z, Document 253667 Volume 3 : System Programming Guide, Document 253668

Introduction

Document Document Location

http://developer.intel.com/design/ pentiumXE/designex/306830.htm

http://developer.intel.com/design/ PentiumXE/specupdt/

306832.htm http://developer.intel.com/design/

Pentium4/guides/302356.htm http://developer.intel.com/design/

pentium4/guides/302666.htm

http://developer.intel.com/design/ pentium4/manuals/ index_new.htm

Datasheet 13

Introduction

14 Datasheet

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The Intel® Pentium® D processor has 226 VCC (power) and 273 VSS (ground) inputs for on-chip power distribution. All VCC lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) lands.

The Pentium D processor has 24 signals that are denoted as VTT that provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the V

specifications outlined in Table 2-3.

Electrical Specifications

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (C longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-3. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for further information.

2.2.2 VTT Decoupling

), such as electrolytic or aluminum-polymer capacitors, supply current during

BULK

Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.

Datasheet 15

Electrical Specifications

2.2.3 FSB Decoupling

The Pentium D processor package integrates signal termination on the die as well as incorporates high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system baseboard for proper GTL+ bus operation.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the Pentium D processor is defined by the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC lands (Section 2.5.3 for V these signals. A minimum voltage for each processor frequency is provided in Table 2-3.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 2-3.

The Pentium D processor uses six voltage identification signals, VID[5:0], to support automatic selection of power supply voltages. Table 2-1 specifies the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Vol tage Regul ator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for more details.

overshoot specifications). Refer to Table 2-10 for the DC specifications for

The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Minimum and maximum voltages must be maintained as shown in Table 2-4/Table 2-5 and

Figure 2-1/Figure 2-2 as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-3, Table 2-4, and

Table 2-5. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775

Socket for further details.

). This will represent a DC shift in the load line. It should be

16 Datasheet

Electrical Specifications

Table 2-1. Voltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.2875 1 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.3000 0 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.3125 1 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.3250 0 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.3375 1 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.3500 0 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.3625 1 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.3750 0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875 1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000 0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125 1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250 0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375 1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.4500 0 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.4625 1 1 1 1 1 1 VR output off 1 0 1 1 1 1 1.4750 0 1 1 1 1 1 VR output off 0 0 1 1 1 1 1.4875 1 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.5000 0 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.5125 1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250 0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375 1 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.5500 0 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625 1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750 0 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.5875 1 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.6000

Datasheet 17

Electrical Specifications

2.4 Reserved, Unused, FC and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, V to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. In a system level design, on-die termination has been included on the Pentium D processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on the processor silicon. However, see Table 2-8 for details on GTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (V unconnected; however, this may interfere with some test access port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability . For unu sed GTL+ inputs or I/O signals, us e pull-up r esistors of the same value as the on-die termination resistors (R

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.

FCx signals are signals that are available for compatibility with other processors. The TESTHI signals must be tied to the processor V

resistor has a resistance value within ±20% of the impedance of the board transmission line traces. For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

). Refer to Table 2-16 for more details.

using a matched resistor, where a matched

). Unused outputs can be left

TT,

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

18 Datasheet

2.5 Voltage and Current Specifications

2.5.1 Absolute Maximum and Minimum Ratings

Table 2-2 specifies absolute maximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute max im u m and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor longterm reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Electrical Specifications

Table 2-2. Processor DC Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within th ese limits will not aff ect the long-te rm reliability of the device. For functional operation, refer to the processor case temperature specifications.

4. This rating applies to the processor and does not include any tray or packaging.

Core voltage with respect to V FSB termination voltage with

respect to V Processor case temperature See Section 5 See Section 5 °C - Processor storage temperature –40 +85 °C

- 0.3 1.55 V -

2.5.2 DC Voltage and Current Specifications

The processor DC specifications in this section are defined at the processor core silicon and not at the package lands unless noted otherwise. See Chapter 4 for the signal definitions and

signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group.

1, 2

3, 4

Datasheet 19

Electrical Specifications

Table 2-3. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID range VID 1.200 — 1.400 V

Processor number Core Frequency

for 775_VR_CONFIG_05B

CC_RESET

SGNT

ENHANCED_HALT

TCC

VTT_OUT I I

CC_VCCA

CC_VCCIOPLL

CC_GTLREF

processor

840 830

processor 820 805

D processor (PRB = 1) 840 830

D processor (PRB = 0) 820

805

active 840 830 820 805

840/830/820/805

840/830/820/805 ICC TCC active — — I VTT for 775_VTT_CONFIG_2 processors:

FSB termination voltage (DC+AC specifications) 1.14 1.20 1.26 DC Current that may be drawn from VTT_OUT per pin — — 580 mA FSB termination current — — 4.7 A ICC for PLL lands — — 120 mA ICC for I/O PLL land — — 100 mA ICC for GTLREF — — 200 μA

(PRB = 1)

3.20 GHz 3GHz

for 775_VR_CONFIG_05A

(PRB = 0)

2.80 GHz

2.66 GHz

for 775_VR_CONFIG_05B Pentium

3.20 GHz 3GHz

for 775_VR_CONFIG_05A Pentium

2.80 GHz

2.66 GHz

when PWRGOOD and RESET# are

3.20 GHz 3GHz

2.80 GHz

2.66 GHz

Stop-Grant

3.20/3/2.80/2.66 GHz

Enhanced Halt

3.20/3/2.80/2.66 GHz

Refer to Table 2-5 and

Figure 2-2

Refer to Table 2-4 and

Figure 2-1

——

125 125

——

100 100

——

125 125 106 106

——

65 A

50 A

NOTES:

1. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings.

2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2-1 for more information.

3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

4. Re fer to Table 2-5 and Figure 2-2 for the minimum, typical, and maximum V to any V

and ICC combination wherein VCC exceeds V

for a given current.

_MAX

allowed for a given current. The processor should not be subjected

2, 3, 4, 5

2, 3, 5, 6, 7

10, 11, 12

11, 12

14, 15

12, 16

12 12 12

20 Datasheet

Electrical Specifications

5. 775_VR_CONFIG_05A and 775_VR_CONFIG_05B refer to voltage regulator configurations that are defined in the Voltage Regulator Down (VRD)

10.1 Design Guide For Desktop LGA775 Socket.

6. Re fer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum V to any V

7. These frequencies will operate properly in a system designed for 775_VR_CONFIG_05B processors. The power and I in this configuration due to the improved loadline and resulting higher V

8. I

9. I

CC_RESET

10. The current specified is also for AutoHALT State.

11. I

12. These parameters are based on design characterization and are not tested.

13. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum I

14. V

15. Baseboard bandwidth is limited to 20 MHz.

16. This is maximum total current drawn from V the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Deskt op LGA775 Socket to determine the total I system.

and ICC combination wherein VCC exceeds V

is based on the VCC Maximum loadline. Refer to Figure 2-1 and Figure 2-2 for details.

_MAX

is specified while PWRGOOD and RESET# are active.

Stop-Grant and ICC Enhanced Halt are specified at V

for the processor.

must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land.

plane by only the processor. This specification does not include the current coming fr om RTT (through

for a given current.

_MAX

allowed for a given current. The processor should not be subjected

will be incrementally higher

drawn by the

Table 2-4. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor

Icc (A) Voltage Deviation from VID Setting (V)

1, 2, 3

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

100

Maximum Voltage

1.30 mΩ

0.000 -0.019 -0.038

-0.007 -0.026 -0.045

-0.013 -0.033 -0.053

-0.020 -0.040 -0.060

-0.026 -0.047 -0.067

-0.033 -0.053 -0.074

-0.039 -0.060 -0.082

-0.046 -0.067 -0.089

-0.052 -0.074 -0.096

-0.059 -0.081 -0.103

-0.065 -0.088 -0.111

-0.072 -0.095 -0.118

-0.078 -0.102 -0.125

-0.085 -0.108 -0.132

-0.091 -0.115 -0.140

-0.098 -0.122 -0.147

-0.101 -0.126 -0.151

-0.111 -0.136 -0.161

-0.117 -0.143 -0.169

-0.124 -0.150 -0.176

-0.130 -0.157 -0.183

Typical Voltage

1.38 mΩ

Minimum Voltage

1.45 mΩ

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.5.3.

2. This table is intended to aid in reading discrete points on Figure2-1.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guide- lines and VR implementation details.

Datasheet 21

Electrical Specifications

Figure 2-1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D

Processor

Icc [A]

Vcc Maximum

VID - 0.000

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

VID - 0.088

VID - 0.100

Vcc [V]

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

VID - 0.175

VID - 0.188

0 102030405060708090100

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.5.3.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. V oltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.

22 Datasheet

Electrical Specifications

Table 2-5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor

Icc (A) Voltage Deviation from VID Setting (V)

1, 2, 3

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

100 105 110 115 120 125

Maximum Voltage

1.30 mΩ

0.000 -0.019 -0.038

-0.007 -0.026 -0.045

-0.013 -0.033 -0.053

-0.020 -0.040 -0.060

-0.026 -0.047 -0.067

-0.033 -0.053 -0.074

-0.039 -0.060 -0.082

-0.046 -0.067 -0.089

-0.052 -0.074 -0.096

-0.059 -0.081 -0.103

-0.065 -0.088 -0.111

-0.072 -0.095 -0.118

-0.078 -0.102 -0.125

-0.085 -0.108 -0.132

-0.091 -0.115 -0.140

-0.098 -0.122 -0.147

-0.101 -0.126 -0.151

-0.111 -0.136 -0.161

-0.117 -0.143 -0.169

-0.124 -0.150 -0.176

-0.130 -0.157 -0.183

-0.137 -0.163 -0.190

-0.143 -0.170 -0.198

-0.150 -0.177 -0.205

-0.156 -0.184 -0.212

-0.163 -0.191 -0.219

Typical Voltage

1.38 mΩ

Minimum Voltage

1.45 mΩ

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.5.3.

2. This table is intended to aid in reading discrete points on Figure2-2.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. V olt age regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation deta ils.

Datasheet 23

Electrical Specifications

Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D

Processor

VID - 0.000

VID - 0.025

VID - 0.050

VID - 0.075

VID - 0.100

Vcc [V]

VID - 0.125

VID - 0.150

VID - 0.175

VID - 0.200

VID - 0.225

0 102030405060708090100110120

Icc [A]

Vcc Maximum

Vcc Typical

Vcc Minimum

24 Datasheet

2.5.3 VCC Overshoot Specification

The Pentium D processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + V

OS_MAX

duration of the overshoot event must not exceed T time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 2-6. VCC Overshoot Specifications

Symbol Parameter Min Typ Max Unit Figure

OS_MAX

Magnitude of VCC overshoot above VID — — 0.050 V 2-3 Time duration of VCC overshoot above VID — — 25 μs 2-3

Figure 2-3. VCC Overshoot Example Waveform

OS_MAX

is the maximum allowable overshoot voltage). The time

OS_MAX

Example Overshoot Waveform

OS_MAX

Electrical Specifications

is the maximum allowable

VID + 0.050

VID

Voltage (V)

TOS: Overshoot time above VID V

NOTES:

1. V

is measured overshoot voltage.

2. T

is measured time duration above VID.

: Overshoot above VID

Time

Datasheet 25

Electrical Specifications

2.5.4 Die Voltage Validation

Overshoot events on the processor must meet the specifications in Table 2-6 when measured across the VCC_SENSE ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for additional voltage regulator validation details.

and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be

2.6 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as V processor (and chipset), separate V for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

. Because platforms implement separate power planes for each

and VTT supplies are necessary. This configuration allows

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see

Table 2-16 for GTLREF specifications). Termination resistors (R

on the processor silicon and are terminated to V termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

2.6.1 FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals that are relative to their respective strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-7 identifies which signals are common clock, source synchronous and asynchronous.

) for G TL+ signals are provided

. Intel chipsets will also provide on-die

26 Datasheet

Table 2-7. FSB Signal Groups

Signal Group Type Signals

Electrical Specifications

GTL+ Common Clock Input

GTL+ Common Clock I/O Synchronous to BCLK[1:0]

GTL+ Source Synchronous I/O

GTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# GTL+ Asynchronous

Input GTL+ Asynchronous

Output GTL+ Asynchronous

Input/Output TAP Input Synchronous to TCK TCK, TDI, TMS, TRST# TAP Output Synchronous to TCK TDO FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. The value of A[16:3]# and A[35:17]# during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.

3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#,

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB0#

Synchronous to assoc.

strobe

A[35:17]# ADSTB1# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3#

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#

FERR#/PBE#, IERR#, THERMTRIP#

PROCHOT#

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF[1:0], COMP[1:0], COMP[3:2], IMPSEL, RESERVED, TESTHI[13:0], THERMDA, THERMDC, VCC_SENSE, VSS_SENSE, BSEL[2:0], SKTOCC#,

DBR#

, VTTPWRGD, BOOTSELECT, PWRGOOD, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], FCx, VCC_MB_REGULATION, VSS_MB_REGULATION, MSID[1:0], VCCPLL

Table 2-8 outlines the signals which include on-die termination (RTT). Open drain signals are also

included. Table 2-9 provides signal reference voltages.

Datasheet 27

Electrical Specifications

Table 2-8. Signal Characteristics

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOTSELECT DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, IMPSEL PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#, MSID[1:0]

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/ PBE#, IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0]

NOTES:

1. These signals have a 250–5000 Ω pullup to VTT rather than on-die termination.

2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

, LOCK#, MCERR#,

Open Drain Signals

, BPRI#, D[63:0]#,

Table 2-9. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 2-12 for more information.

Signals with no R

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0], COMP[3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0], THERMDA, THERMDC, THERMTRIP#, VID[5:0], VTTPWRGD, GTLREF[1:0], TCK, TDI, TRST#, TMS

BOOTSELECT, VTTPWRGD, A20M#, IGNNE#, INIT#, PWRGOOD

TMS

, TRST#1, MSID[1:0]

, SMI#, STPCLK#, TCK1, TDI1,

2.6.2 GTL+ Asynchronous Signals

The signals A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. GTL+ asynchronous signals follow the same DC requirements as GTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. GTL+ asynchronous signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order for the processor to recognize the proper signal state. See Section 2.6.3 for the DC specifications for the GT L+ Asynchronous signal groups. See Table 6.2 for addit ion al tim ing requirements for entering and leaving the low power states.

28 Datasheet

2.6.3 FSB DC Specifications

The processor front side bus DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.

Table 2-10. BSEL[2:0] and VID[5:0] Signal Group DC Specifications

Symbol Parameter Max Unit Notes

RON (BSEL) Buffer On Resistance 60 Ω -

(VID) Buffer On Resistance 60 Ω -

TOL

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are not tested and are based on design simulations.

3. Leakage to VSS with land held at 2.5V.

Table 2-11. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

6. Leakage to VSS with land held at VTT.

and VOH may experience excursions above VTT.

Max Land Current 8 mA Output Leakage Current 200 µA Voltage Tolerance VTT (max) V -

Input Low Voltage 0.0 GTLREF – (0.10 * VTT)V Input High Voltage GTLREF + (0.10 * VTT)VTTV Output High Voltage N/A V

Output Low Current N/A Input Leakage Current N/A ± 200 µA

Output Leakage Current

N/A ± 200 µA

Buffer On Resistance 8 12 Ω

referred to in these specifications is the instantaneous VTT.

/[(0.50*R

ON_MIN

Electrical Specifications

2, 3

3, 4, 5

TT_MIN

) +

]

V A-

1, 2

3, 5

Datasheet 29

Electrical Specifications

Table 2-12. PWRGOOD Input and TAP Signal Group DC Specificat ions

Symbol Parameter Min Max Unit Notes

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

3. V

4. The VTT referred to in these specifications refers to instantaneous VTT.

5. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the t est load.

6. Leakage to VSS with land held at VTT.

Input Hysteresis 200 350 mV

HYS

Input low to high

threshold voltage Input high to low

threshold voltage Output High Voltage N/A V

Output Low Current - 45 mA

Input Leakage Current - ± 200 µA

Output Leakage

Current Buffer On Resistance 7 12 Ω

represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs.

HYS

0.5 * (V

+ V

– V

HYS_MAX

HYS_MIN

) 0.5 * (VTT + V

) 0.5 * (VTT – V

-± 200µA

HYS_MAX

HYS_MIN

1, 2

5 6

Table 2-13. GTL+ Asynchronous Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

Input Low Voltage 0.0 VTT/2 – (0.10 * VTT)-

Input High Voltage VTT/2 + (0.10 * VTT)VTT-

Output High Voltage 0.90*V

Output Low Current —

Input Leakage Current N/A ± 200 µA

Output Leakage

Current

Buffer On Resistance 8 12 Ω

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. LINT0/INTR, LINT1/NMI, and FORCEPR# use GTLREF as a reference voltage. For these two signals,

= GTLREF + (0.10 * VTT) and VIL= GTLREF – (0.10 * VTT).

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

and VOH may experience excursions above VTT.

5. V

6. The V

7. All outputs are open drain.

8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test

9. Leakage to VSS with land held at VTT.

10. Leakage to VTT with land held at 300 mV.

TT referred to in these specifications refers to instantaneous V

load.

/[(0.50*R

N/A ± 200 µA

ON_MIN

TT_MIN

]

) +

2, 3

3, 4, 5, 6

5, 6, 7

V A

30 Datasheet

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