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Intel® Pentium® D Processor 800Δ Sequence

Datasheet

– On 90 nm Process in the 775-land LGA Package and supporting

February 2006

Intel

Extended Memory 64 Technology

Document Number: 307506-003

Contents

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT , COP YRIGHT O R OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.

Intel may make changes to specifications and product descripti ons at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflict s or inco mpatibilities arising from future changes to them.

The Intel specifications. Current characterized errata are available on request.

different processor families. Over time processor numbers will increment based on changes in clock speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See http://www.intel.com/products/processor_number for details.

drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including details on which processors support EM64T or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a support ing operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its

Pentium® D processor may contain design defects or errors known as errata which may cause the product to deviate from published

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device

2 Datasheet

Contents

1 Introduction....................................................................................................................................11

1.1 Terminology........................................................................................................................12

1.1.1 Processor Packaging Terminology........................................................................12

1.2 References .........................................................................................................................13

2 Electrical Specifications................ .... ... ... ... ... .... ... .......................................... ... ... ..........................15

2.1 Power and Ground Lands...................................................................................................15

2.2 Decoupling Guidelines........................................................................................................15

2.2.1 VCC Decoupling ....................................................................................................15

2.2.2 VTT Decoupling.....................................................................................................15

2.2.3 FSB Decoupling.....................................................................................................16

2.3 Voltage Identification ..........................................................................................................16

2.4 Reserved, Unused, FC and TESTHI Signals......................................................................18

2.5 Voltage and Current Specifications ....................................................................................19

2.5.1 Absolute Maximum and Minimum Ratings.............................................................19

2.5.2 DC Voltage and Current Specifications .................................................................19

2.5.3 VCC Overshoot Specification ................................................................................25

2.5.4 Die Voltage Validation ...........................................................................................26

2.6 Signaling Specifications......................................................................................................26

2.6.1 FSB Signal Groups................................................................................................26

2.6.2 GTL+ Asynchronous Signals.................................................................................28

2.6.3 FSB DC Specifications ..........................................................................................29

2.7 Clock Specifications........ ... .................................................................................................32

2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................32

2.7.2 FSB Frequency Select Signals..............................................................................32

2.7.3 Phase Lock Loop (PLL) and Filter .........................................................................33

3 Package Mechanical Specifications ..............................................................................................35

3.1 Package Mechanical Drawing ............................................................................................35

3.2 Processor Component Keep-Out Zones.............................................................................39

3.3 Package Loading Specifications.........................................................................................39

3.4 Package Handling Guidelines.............................................................................................39

3.5 Package Insertion Specifications........................................................................................40

3.6 Processor Mass Specification.............................................................................................40

3.7 Processor Materials............................................................................................................40

3.8 Processor Markings............................................................................................................40

3.9 Processor Land Coordinates ..............................................................................................42

4 Land Listing and Signal Descriptions ............................................................................................43

4.1 Processor Land Assignments.............................................................................................43

4.2 Alphabetical Signals Reference..........................................................................................66

5 Thermal Specifications and Design Considerations......................................................................75

5.1 Processor Thermal Specifications ......................................................................................75

5.1.1 Thermal Specifications ..........................................................................................75

5.1.2 Thermal Metrology.................................................................................................79

Datasheet 3

Contents

5.2 Processor Thermal Features.................... ... ... ... .......................................... .... ... ... ... ... .... ...79

5.2.1 Thermal Monitor.............................. ... ... .......................................... .... ... ... .............79

5.2.2 On-Demand Mode.................................................................................................80

5.2.3 PROCHOT# Signal................................................................................................80

5.2.4 FORCEPR# Signal Pin..........................................................................................81

5.2.5 THERMTRIP# Signal.............................................................................................82

5.2.6 T

CONTROL

and Fan Speed Reduction....................................................................82

5.2.7 Thermal Diode......... .... ... ... ... ... .... ... ... ... .................................................................82

6 Features ........................................................................................................................................85

6.1 Power-On Configuration Options................................. ... .... ... ... ... ... .... ... ... ..........................85

6.2 Clock Control and Low Power States.................................................................................85

6.2.1 Normal State................................... .......................................................................86

6.2.2 HALT and Enhanced HALT Powerdown States ....................................................86

6.2.3 Stop-Grant State................................ ... .... ... ... ... .... ... ... ... .......................................87

6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State......................88

6.2.5 Enhanced Intel SpeedStep

Technology ..............................................................88

7 Boxed Processor Specifications....................................................................................................89

7.1 Mechanical Specifications ..................................................................................................90

7.1.1 Boxed Processor Cooling Solution Dimensions ....................................................90

7.1.2 Boxed Processor Fan Heatsink Weight.................................................................91

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly.......91

7.2 Electrical Requirements......................................................................................................91

7.2.1 Fan Heatsink Power Supply ..................................................................................91

7.3 Thermal Specifications .......................................................... ... ... ... .... ... ... ... .... ...................93

7.3.1 Boxed Processor Cooling Requirements...............................................................93

7.3.2 Variable Speed Fan...............................................................................................95

8 Balanced Technology Extended (BTX) Type I Boxed Processor Specifications...........................97

8.1 Mechanical Specifications ..................................................................................................98

8.1.1 Cooling Solution Dimensions.................................................................................98

8.1.2 Boxed Processor Fan Heatsink Weight.................................................................98

8.1.3 Boxed Processor Support and Retention Module (SRM) ......................................99

8.2 Electrical Requirements......................................................................................................99

8.2.1 Fan Heatsink Power Supply ..................................................................................99

8.3 Thermal Specifications .......................................................... ... ... ... .... ... ... ... .... .................101

8.3.1 Boxed Processor Cooling Requirements.............................................................101

8.3.2 Variable Speed Fan.............................................................................................102

9 Debug Tools Specifications....... ... ... .... ... ... .......................................... ... ... ..................................105

9.1 Logic Analyzer Interface (LAI) ..........................................................................................105

9.1.1 Mechanical Considerations..................................................................................105

9.1.2 Electrical Considerations.....................................................................................105

4 Datasheet

Contents

Figures

2-1 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor............22

2-2 VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor............24

2-3 VCC Overshoot Example Waveform ..........................................................................................25

2-4 Phase Lock Loop (PLL) Filter Requirements . .............................................................................34

3-1 Processor Package Assembly Sketch........................................................................................35

3-2 Processor Package Drawing 1 ...................................................................................................36

3-3 Processor Package Drawing 2 ...................................................................................................37

3-4 Processor Package Drawing 3 ...................................................................................................38

3-5 Processor Top-Side Marking Example (Intel 3-6 Processor Top-Side Marking Example (Intel

3-7 Processor Land Coordinates, Top View.....................................................................................42

4-1 Landout Diagram (Top View – Left Side)....................................................................................44

4-2 Landout Diagram (Top View – Right Side).................................................................................45

5-1 Thermal Profile for the Pentium D Processor with PRB=1 ................................... ... ... ... ... .... ......77

5-2 Thermal Profile for the Pentium D Processor with PRB=0 ................................... ... ... ... ... .... ......78

5-3 Case Temperature (TC) Measurement Location........................................................................79

6-1 Processor Low Power State Machine.........................................................................................86

7-1 Mechanical Representation of the Boxed Processor..................................................................89

7-2 Side View Space Requirements for the Boxed Processor (Applies to all four side views).........90

7-3 Top View Space Requirements for the Boxed Processor...........................................................90

7-4 Overall View Space Requirements for the Boxed Processor .................................. ... ... ... .... ... ...91

7-5 Boxed Processor Fan Heatsink Power Cable Connector Description........................................92

7-6 Baseboard Power Header Placement Relative to Processor Socket .........................................93

7-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)........................94

7-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)........................94

7-9 Boxed Processor Fan Heatsink Set Points.................................................................................95

8-1 Mechanical Representation of the Boxed Processor..................................................................97

8-2 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes ..........98

8-3 Assembly Stack Including the Support and Retention Module...................................................99

8-4 Boxed Processor Fan Heatsink Power Cable Connector.........................................................100

8-5 Balanced Technology Extended (BTX) Mainboard Power Head er Placement (hatched area) 101

8-6 Boxed Processor TMA Set Points ....................................................... .... ... ... ... .... ... ... ... ...........102

Pentium® D Processors 840, 830, 820).......... ...40

Pentium® D Processor 805)...............................41

Datasheet 5

Contents

Tables

1-1 References .................................................................................................................................13

2-1 Voltage Identification Definition ..................................................................................................17

2-2 Processor DC Absolute Maximum Ratings ................................................................................19

2-3 Voltage and Current Specifications ............................................................................................20

2-4 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor ...........21

2-5 VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor ...........23

2-6 VCC Overshoot Specifications ............................................................ ... .... ... ... ... .... ... ................25

2-7 FSB Signal Groups.....................................................................................................................27

2-8 Signal Characteristics.................................................................................................................28

2-9 Signal Reference Voltages.........................................................................................................28

2-10BSEL[2:0] and VID[5:0] Signal Group DC Specifications...........................................................29

2-11GTL+ Signal Group DC Specifications .......................................................................................29

2-12PWRGOOD Input and TAP Signal Group DC Specifications.....................................................30

2-13GTL+ Asynchronous Signal Group DC Specifications ...............................................................30

2-14VTTPWRGD DC Specifications..................................................................................................31

2-15BOOTSELECT and MSID[1:0] DC Specifications......................................................................31

2-16GTL+ Bus Voltage Definitions ....................................................................................................31

2-17Core Frequency to FSB Multiplier Configuration. ... ... .... .......................................... ... ... .............32

2-18BSEL[2:0] Frequency Table for BCLK[1:0].................................................................................33

3-1 Processor Loading Specifications ..............................................................................................39

3-2 Package Handling Guidelines ....................................................................................................39

3-3 Processor Materials....................................................................................................................40

4-1 Alphabetical Land Assignments .................................................................................................46

4-2 Numerical Land Assignment......... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... .......................................56

4-3 Signal Description.......................................................................................................................66

5-1 Processor Thermal Specifications..............................................................................................76

5-2 Thermal Profile for the Pentium D Processor with PRB=1 .........................................................77

5-3 Thermal Profile for the Pentium D Processor with PRB=0 .........................................................78

5-4 Thermal Diode Parameters ........................................................................................................82

5-5 Thermal Diode Interface.............................................................................................................83

6-1 Power-On Configuration Option Signals.....................................................................................85

7-1 Fan Heatsink Power and Signal Specifications..........................................................................92

7-2 Fan Heatsink Power and Signal Specifications..........................................................................95

8-1 Fan Heatsink Power and Signal Specifications........................................................................100

8-2 Balanced Technology Extended (BTX) Type I Boxed Processor TMA Set Points for

3-wire Operation........................... .... ... ... ... ... .... ... ... ..................................................................102

6 Datasheet

Revision History

Contents

Revision

Number

-001 • Initial release May 2005

-002

-003

• Added Balanced Technology Extended (BTX) Type I Boxed Processor Specifications chapter.

• Added Intel

• Updated THERMTRIP# signal description in Table 4-3.

Pentium® D processor 805 specifications.

Description Date

October 2005

February 2006

Datasheet 7

Contents

8 Datasheet

Intel® Pentium® D Processor 800 Sequence Features

Contents

• Available at 3.20 GHz, 3 GHz, 2.80 GHz, and

2.66 MHz

• Enhanced Intel Speedstep

D processor 840 and 830 only)

• Supports Intel

(Intel

EM64T)

Extended Memory 64 Technology

Technology (Pentium

• Supports Execute Disable Bit capability

• Binary compatible with applications run ning on

previous members of the Intel microprocessor line

• Intel NetBurst

microarchitecture

• FSB frequency at 800 MHz (Pentium D Processors

840, 830 and 820 only)

• FSB frequency at 533 MHz (Pentium D Processor

805 only)

• Hyper-Pipelined Technology

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

The Intel® Pentium® D processor delivers Intel's advanced, powerful processors for desktop PCs that are based on the Intel NetBurst applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.

microarchitecture. The Pentium D processor is designed to deliver performanc e across

• Optimized for 32-bit applications run ning on

advanced 32-bit operating systems

• Two 16-KB Level 1 data caches

• Two 1 MB Advanced Transfer Caches (on-die,

full-speed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC)

• 144 Streaming SIMD Extensions 2 (SSE2)

instructions

• 13 Streaming SIMD Extensions 3 (SSE3)

instructions

• Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved

cache hit rate on load/store operations

• 775-land Package

Intel

Extended Memory 64 Technology (Intel® EM64T)Φ enables the Pentium D processor to execute operating systems and applications written to take advantage of the Intel EM64T. The Pentium D processor 840 and 830 supporting Enhanced Intel Speedstep consumption.

The Pentium D processor also includes the Execute Disable Bit capability . This fea ture, combined with a supported operating system, allows memory to be marked as executable or non-executable.

Datasheet 9

technology allows tradeoffs to be made between performance and power

Contents

10 Datasheet

1 Introduction

The Intel® Pentium® D processor extends Intel's Desktop dual-core product line. The Pentium D processor uses Flip-Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775land LGA socket, referred to as the LGA775 socket. The Pentium D processor, like the Intel Pentium 4 processor in the 775-land package, utilizes the Intel NetBurst maintains the tradition of compatibility with IA-32 software.

The Intel EM64T) This enhancement enables the processor to execute operating systems and applications written to take advantage of Intel EM64T. Further details on the 64-bit extension architecture and programming model can be found in the Intel Guide at http://developer.intel.com/technology/64bitextensions/.

Note: In this document the Pentium D processor 800 sequence is also referred to as the Pentium D

processor or simply as the processor. The Pentium D processor functions as two physical processors in one package. This allows a

duplication of execution resources to provide increased system responsiveness in multitasking environments, and headroom for next generation multithreaded applications and new usages.

Pentium® D processor supports Intel® Extended Memory 64 Technology (Intel®

as an enhancement to Intel's IA-32 architecture, on server and workstation platforms.

Introduction

microarchitecture and

64-bit Extension Technology Software Developer's

The Pentium D processor supports all the existing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Streaming SIMD Extensions 3 (SSE3) are 13 additional instructions that further extend the capabilities of Intel processor technology. These new instructions enhance the performance of optimized applications for the digital home such as video, image processing, and media compression technology.

The processor’s Intel NetBurst microarchitecture FSB uses a split-transaction, deferred reply protocol like the Intel Pentium 4 processor. The Intel NetBurst microarchitecture FSB uses SourceSynchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6.4 GB/s.

The Pentium D processor includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel Architecture Software Developer's Manual for more detailed information.

Intel will enable support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

The processor includes an address bus powerdown capability that removes power from the address and data pins when the FSB is not in use. This feature is always enabled on the processor.

Enhanced Intel SpeedStep power consumptions. This may lower average power consumption (in conjunction with OS support).

Technology allows trade-offs to be made between performance and

Datasheet 11

Introduction

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• Intel

• Processor — For this document, the term processor is the generic form of the Intel Pentium D

• Keep-out zone — The area on or near the processor that system design can not use.

• Intel

• Processor core — Processor core die with integrated L2 cache.

• FC-LGA4 package — The Pentium D processor is available in a Flip-Chip Land Grid Array

• LGA775 socket — The Pentium D processor mates with the system board through a surface

• Integrated heat spreader (IHS) — A component of the processor package used to enhance

• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical

• Storage conditions — Refers to a non-operational state. The processor may be installed in a

• Functional operation — Refers to normal operating conditions in which all processor

Pentium® D processor 800 sequence — Dual-core processor in the FC-LGA4

package with two 1-MB L2 caches.

processor 800 sequence.

945G/945GZ/945P/945PL Express Chipset Family — Chipset that supports DDR2

memory technology for the Pentium D processor.

955X Express Chipset — Chipset that supports DDR2 memory technology for the

Pentium D processor.

4 package, consisting of a processor core mounted on a substrate with an integrated heat spreader (IHS).

mount, 775-land, LGA socket.

the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.

platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

specifications, including DC, AC, system bus, signal quality, mechanical and thermal, are satisfied.

12 Datasheet

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document:

Table 1-1. References

Intel

Pentium® D Processor and Intel® Pentium® Processor Extreme

Edition 840 Thermal and Mechanical Design Guidelines

Intel

Pentium® Processor Extreme Edition and Intel® Pentium® D

Processor Specification Update Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775

Socket LGA775 Socket Mechanical Design Guide

Intel

Architecture Software Developer's Manual Volume 1: Basic Architecture, Document 253665 Volume 2A :Instruction Set Reference, A-M, Document 253666 Volume 2B: Instruction Set Reference, N-Z, Document 253667 Volume 3 : System Programming Guide, Document 253668

Introduction

Document Document Location

http://developer.intel.com/design/ pentiumXE/designex/306830.htm

http://developer.intel.com/design/ PentiumXE/specupdt/

306832.htm http://developer.intel.com/design/

Pentium4/guides/302356.htm http://developer.intel.com/design/

pentium4/guides/302666.htm

http://developer.intel.com/design/ pentium4/manuals/ index_new.htm

Datasheet 13

Introduction

14 Datasheet

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The Intel® Pentium® D processor has 226 VCC (power) and 273 VSS (ground) inputs for on-chip power distribution. All VCC lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) lands.

The Pentium D processor has 24 signals that are denoted as VTT that provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the V

specifications outlined in Table 2-3.

Electrical Specifications

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (C longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-3. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for further information.

2.2.2 VTT Decoupling

), such as electrolytic or aluminum-polymer capacitors, supply current during

BULK

Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.

Datasheet 15

Electrical Specifications

2.2.3 FSB Decoupling

The Pentium D processor package integrates signal termination on the die as well as incorporates high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system baseboard for proper GTL+ bus operation.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the Pentium D processor is defined by the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC lands (Section 2.5.3 for V these signals. A minimum voltage for each processor frequency is provided in Table 2-3.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 2-3.

The Pentium D processor uses six voltage identification signals, VID[5:0], to support automatic selection of power supply voltages. Table 2-1 specifies the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Vol tage Regul ator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for more details.

overshoot specifications). Refer to Table 2-10 for the DC specifications for

The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Minimum and maximum voltages must be maintained as shown in Table 2-4/Table 2-5 and

Figure 2-1/Figure 2-2 as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-3, Table 2-4, and

Table 2-5. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775

Socket for further details.

). This will represent a DC shift in the load line. It should be

16 Datasheet

Electrical Specifications

Table 2-1. Voltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.2875 1 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.3000 0 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.3125 1 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.3250 0 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.3375 1 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.3500 0 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.3625 1 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.3750 0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875 1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000 0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125 1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250 0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375 1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.4500 0 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.4625 1 1 1 1 1 1 VR output off 1 0 1 1 1 1 1.4750 0 1 1 1 1 1 VR output off 0 0 1 1 1 1 1.4875 1 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.5000 0 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.5125 1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250 0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375 1 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.5500 0 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625 1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750 0 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.5875 1 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.6000

Datasheet 17

Electrical Specifications

2.4 Reserved, Unused, FC and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, V to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. In a system level design, on-die termination has been included on the Pentium D processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on the processor silicon. However, see Table 2-8 for details on GTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (V unconnected; however, this may interfere with some test access port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability . For unu sed GTL+ inputs or I/O signals, us e pull-up r esistors of the same value as the on-die termination resistors (R

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.

FCx signals are signals that are available for compatibility with other processors. The TESTHI signals must be tied to the processor V

resistor has a resistance value within ±20% of the impedance of the board transmission line traces. For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

). Refer to Table 2-16 for more details.

using a matched resistor, where a matched

). Unused outputs can be left

TT,

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

18 Datasheet

2.5 Voltage and Current Specifications

2.5.1 Absolute Maximum and Minimum Ratings

Table 2-2 specifies absolute maximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute max im u m and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor longterm reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Electrical Specifications

Table 2-2. Processor DC Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within th ese limits will not aff ect the long-te rm reliability of the device. For functional operation, refer to the processor case temperature specifications.

4. This rating applies to the processor and does not include any tray or packaging.

Core voltage with respect to V FSB termination voltage with

respect to V Processor case temperature See Section 5 See Section 5 °C - Processor storage temperature –40 +85 °C

- 0.3 1.55 V -

2.5.2 DC Voltage and Current Specifications

The processor DC specifications in this section are defined at the processor core silicon and not at the package lands unless noted otherwise. See Chapter 4 for the signal definitions and

signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group.

1, 2

3, 4

Datasheet 19

Electrical Specifications

Table 2-3. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID range VID 1.200 — 1.400 V

Processor number Core Frequency

for 775_VR_CONFIG_05B

CC_RESET

SGNT

ENHANCED_HALT

TCC

VTT_OUT I I

CC_VCCA

CC_VCCIOPLL

CC_GTLREF

processor

840 830

processor 820 805

D processor (PRB = 1) 840 830

D processor (PRB = 0) 820

805

active 840 830 820 805

840/830/820/805

840/830/820/805 ICC TCC active — — I VTT for 775_VTT_CONFIG_2 processors:

FSB termination voltage (DC+AC specifications) 1.14 1.20 1.26 DC Current that may be drawn from VTT_OUT per pin — — 580 mA FSB termination current — — 4.7 A ICC for PLL lands — — 120 mA ICC for I/O PLL land — — 100 mA ICC for GTLREF — — 200 μA

(PRB = 1)

3.20 GHz 3GHz

for 775_VR_CONFIG_05A

(PRB = 0)

2.80 GHz

2.66 GHz

for 775_VR_CONFIG_05B Pentium

3.20 GHz 3GHz

for 775_VR_CONFIG_05A Pentium

2.80 GHz

2.66 GHz

when PWRGOOD and RESET# are

3.20 GHz 3GHz

2.80 GHz

2.66 GHz

Stop-Grant

3.20/3/2.80/2.66 GHz

Enhanced Halt

3.20/3/2.80/2.66 GHz

Refer to Table 2-5 and

Figure 2-2

Refer to Table 2-4 and

Figure 2-1

——

125 125

——

100 100

——

125 125 106 106

——

65 A

50 A

NOTES:

1. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings.

2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2-1 for more information.

3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

4. Re fer to Table 2-5 and Figure 2-2 for the minimum, typical, and maximum V to any V

and ICC combination wherein VCC exceeds V

for a given current.

_MAX

allowed for a given current. The processor should not be subjected

2, 3, 4, 5

2, 3, 5, 6, 7

10, 11, 12

11, 12

14, 15

12, 16

12 12 12

20 Datasheet

Electrical Specifications

5. 775_VR_CONFIG_05A and 775_VR_CONFIG_05B refer to voltage regulator configurations that are defined in the Voltage Regulator Down (VRD)

10.1 Design Guide For Desktop LGA775 Socket.

6. Re fer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum V to any V

7. These frequencies will operate properly in a system designed for 775_VR_CONFIG_05B processors. The power and I in this configuration due to the improved loadline and resulting higher V

8. I

9. I

CC_RESET

10. The current specified is also for AutoHALT State.

11. I

12. These parameters are based on design characterization and are not tested.

13. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum I

14. V

15. Baseboard bandwidth is limited to 20 MHz.

16. This is maximum total current drawn from V the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Deskt op LGA775 Socket to determine the total I system.

and ICC combination wherein VCC exceeds V

is based on the VCC Maximum loadline. Refer to Figure 2-1 and Figure 2-2 for details.

_MAX

is specified while PWRGOOD and RESET# are active.

Stop-Grant and ICC Enhanced Halt are specified at V

for the processor.

must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land.

plane by only the processor. This specification does not include the current coming fr om RTT (through

for a given current.

_MAX

allowed for a given current. The processor should not be subjected

will be incrementally higher

drawn by the

Table 2-4. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor

Icc (A) Voltage Deviation from VID Setting (V)

1, 2, 3

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

100

Maximum Voltage

1.30 mΩ

0.000 -0.019 -0.038

-0.007 -0.026 -0.045

-0.013 -0.033 -0.053

-0.020 -0.040 -0.060

-0.026 -0.047 -0.067

-0.033 -0.053 -0.074

-0.039 -0.060 -0.082

-0.046 -0.067 -0.089

-0.052 -0.074 -0.096

-0.059 -0.081 -0.103

-0.065 -0.088 -0.111

-0.072 -0.095 -0.118

-0.078 -0.102 -0.125

-0.085 -0.108 -0.132

-0.091 -0.115 -0.140

-0.098 -0.122 -0.147

-0.101 -0.126 -0.151

-0.111 -0.136 -0.161

-0.117 -0.143 -0.169

-0.124 -0.150 -0.176

-0.130 -0.157 -0.183

Typical Voltage

1.38 mΩ

Minimum Voltage

1.45 mΩ

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.5.3.

2. This table is intended to aid in reading discrete points on Figure2-1.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guide- lines and VR implementation details.

Datasheet 21

Electrical Specifications

Figure 2-1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D

Processor

Icc [A]

Vcc Maximum

VID - 0.000

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

VID - 0.088

VID - 0.100

Vcc [V]

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

VID - 0.175

VID - 0.188

0 102030405060708090100

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.5.3.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. V oltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.

22 Datasheet

Electrical Specifications

Table 2-5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor

Icc (A) Voltage Deviation from VID Setting (V)

1, 2, 3

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

100 105 110 115 120 125

Maximum Voltage

1.30 mΩ

0.000 -0.019 -0.038

-0.007 -0.026 -0.045

-0.013 -0.033 -0.053

-0.020 -0.040 -0.060

-0.026 -0.047 -0.067

-0.033 -0.053 -0.074

-0.039 -0.060 -0.082

-0.046 -0.067 -0.089

-0.052 -0.074 -0.096

-0.059 -0.081 -0.103

-0.065 -0.088 -0.111

-0.072 -0.095 -0.118

-0.078 -0.102 -0.125

-0.085 -0.108 -0.132

-0.091 -0.115 -0.140

-0.098 -0.122 -0.147

-0.101 -0.126 -0.151

-0.111 -0.136 -0.161

-0.117 -0.143 -0.169

-0.124 -0.150 -0.176

-0.130 -0.157 -0.183

-0.137 -0.163 -0.190

-0.143 -0.170 -0.198

-0.150 -0.177 -0.205

-0.156 -0.184 -0.212

-0.163 -0.191 -0.219

Typical Voltage

1.38 mΩ

Minimum Voltage

1.45 mΩ

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.5.3.

2. This table is intended to aid in reading discrete points on Figure2-2.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. V olt age regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation deta ils.

Datasheet 23

Electrical Specifications

Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D

Processor

VID - 0.000

VID - 0.025

VID - 0.050

VID - 0.075

VID - 0.100

Vcc [V]

VID - 0.125

VID - 0.150

VID - 0.175

VID - 0.200

VID - 0.225

0 102030405060708090100110120

Icc [A]

Vcc Maximum

Vcc Typical

Vcc Minimum

24 Datasheet

2.5.3 VCC Overshoot Specification

The Pentium D processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + V

OS_MAX

duration of the overshoot event must not exceed T time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 2-6. VCC Overshoot Specifications

Symbol Parameter Min Typ Max Unit Figure

OS_MAX

Magnitude of VCC overshoot above VID — — 0.050 V 2-3 Time duration of VCC overshoot above VID — — 25 μs 2-3

Figure 2-3. VCC Overshoot Example Waveform

OS_MAX

is the maximum allowable overshoot voltage). The time

OS_MAX

Example Overshoot Waveform

OS_MAX

Electrical Specifications

is the maximum allowable

VID + 0.050

VID

Voltage (V)

TOS: Overshoot time above VID V

NOTES:

1. V

is measured overshoot voltage.

2. T

is measured time duration above VID.

: Overshoot above VID

Time

Datasheet 25

Electrical Specifications

2.5.4 Die Voltage Validation

Overshoot events on the processor must meet the specifications in Table 2-6 when measured across the VCC_SENSE ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for additional voltage regulator validation details.

and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be

2.6 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as V processor (and chipset), separate V for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.

. Because platforms implement separate power planes for each

and VTT supplies are necessary. This configuration allows

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see

Table 2-16 for GTLREF specifications). Termination resistors (R

on the processor silicon and are terminated to V termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

2.6.1 FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals that are relative to their respective strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-7 identifies which signals are common clock, source synchronous and asynchronous.

) for G TL+ signals are provided

. Intel chipsets will also provide on-die

26 Datasheet

Table 2-7. FSB Signal Groups

Signal Group Type Signals

Electrical Specifications

GTL+ Common Clock Input

GTL+ Common Clock I/O Synchronous to BCLK[1:0]

GTL+ Source Synchronous I/O

GTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# GTL+ Asynchronous

Input GTL+ Asynchronous

Output GTL+ Asynchronous

Input/Output TAP Input Synchronous to TCK TCK, TDI, TMS, TRST# TAP Output Synchronous to TCK TDO FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. The value of A[16:3]# and A[35:17]# during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.

3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#,

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB0#

Synchronous to assoc.

strobe

A[35:17]# ADSTB1# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3#

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#

FERR#/PBE#, IERR#, THERMTRIP#

PROCHOT#

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF[1:0], COMP[1:0], COMP[3:2], IMPSEL, RESERVED, TESTHI[13:0], THERMDA, THERMDC, VCC_SENSE, VSS_SENSE, BSEL[2:0], SKTOCC#,

DBR#

, VTTPWRGD, BOOTSELECT, PWRGOOD, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], FCx, VCC_MB_REGULATION, VSS_MB_REGULATION, MSID[1:0], VCCPLL

Table 2-8 outlines the signals which include on-die termination (RTT). Open drain signals are also

included. Table 2-9 provides signal reference voltages.

Datasheet 27

Electrical Specifications

Table 2-8. Signal Characteristics

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOTSELECT DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, IMPSEL PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#, MSID[1:0]

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/ PBE#, IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0]

NOTES:

1. These signals have a 250–5000 Ω pullup to VTT rather than on-die termination.

2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

, LOCK#, MCERR#,

Open Drain Signals

, BPRI#, D[63:0]#,

Table 2-9. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 2-12 for more information.

Signals with no R

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0], COMP[3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0], THERMDA, THERMDC, THERMTRIP#, VID[5:0], VTTPWRGD, GTLREF[1:0], TCK, TDI, TRST#, TMS

BOOTSELECT, VTTPWRGD, A20M#, IGNNE#, INIT#, PWRGOOD

TMS

, TRST#1, MSID[1:0]

, SMI#, STPCLK#, TCK1, TDI1,

2.6.2 GTL+ Asynchronous Signals

The signals A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. GTL+ asynchronous signals follow the same DC requirements as GTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. GTL+ asynchronous signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order for the processor to recognize the proper signal state. See Section 2.6.3 for the DC specifications for the GT L+ Asynchronous signal groups. See Table 6.2 for addit ion al tim ing requirements for entering and leaving the low power states.

28 Datasheet

2.6.3 FSB DC Specifications

The processor front side bus DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.

Table 2-10. BSEL[2:0] and VID[5:0] Signal Group DC Specifications

Symbol Parameter Max Unit Notes

RON (BSEL) Buffer On Resistance 60 Ω -

(VID) Buffer On Resistance 60 Ω -

TOL

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are not tested and are based on design simulations.

3. Leakage to VSS with land held at 2.5V.

Table 2-11. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

6. Leakage to VSS with land held at VTT.

and VOH may experience excursions above VTT.

Max Land Current 8 mA Output Leakage Current 200 µA Voltage Tolerance VTT (max) V -

Input Low Voltage 0.0 GTLREF – (0.10 * VTT)V Input High Voltage GTLREF + (0.10 * VTT)VTTV Output High Voltage N/A V

Output Low Current N/A Input Leakage Current N/A ± 200 µA

Output Leakage Current

N/A ± 200 µA

Buffer On Resistance 8 12 Ω

referred to in these specifications is the instantaneous VTT.

/[(0.50*R

ON_MIN

Electrical Specifications

2, 3

3, 4, 5

TT_MIN

) +

]

V A-

1, 2

3, 5

Datasheet 29

Electrical Specifications

Table 2-12. PWRGOOD Input and TAP Signal Group DC Specificat ions

Symbol Parameter Min Max Unit Notes

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

3. V

4. The VTT referred to in these specifications refers to instantaneous VTT.

5. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the t est load.

6. Leakage to VSS with land held at VTT.

Input Hysteresis 200 350 mV

HYS

Input low to high

threshold voltage Input high to low

threshold voltage Output High Voltage N/A V

Output Low Current - 45 mA

Input Leakage Current - ± 200 µA

Output Leakage

Current Buffer On Resistance 7 12 Ω

represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs.

HYS

0.5 * (V

+ V

– V

HYS_MAX

HYS_MIN

) 0.5 * (VTT + V

) 0.5 * (VTT – V

-± 200µA

HYS_MAX

HYS_MIN

1, 2

5 6

Table 2-13. GTL+ Asynchronous Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

Input Low Voltage 0.0 VTT/2 – (0.10 * VTT)-

Input High Voltage VTT/2 + (0.10 * VTT)VTT-

Output High Voltage 0.90*V

Output Low Current —

Input Leakage Current N/A ± 200 µA

Output Leakage

Current

Buffer On Resistance 8 12 Ω

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. LINT0/INTR, LINT1/NMI, and FORCEPR# use GTLREF as a reference voltage. For these two signals,

= GTLREF + (0.10 * VTT) and VIL= GTLREF – (0.10 * VTT).

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

and VOH may experience excursions above VTT.

5. V

6. The V

7. All outputs are open drain.

8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test

9. Leakage to VSS with land held at VTT.

10. Leakage to VTT with land held at 300 mV.

TT referred to in these specifications refers to instantaneous V

load.

/[(0.50*R

N/A ± 200 µA

ON_MIN

TT_MIN

]

) +

2, 3

3, 4, 5, 6

5, 6, 7

V A

30 Datasheet

Table 2-14. VTTPWRGD DC Specifications

Symbol Parameter Min Typ Max Unit Notes

Input Low Voltage — — 0.3 V

Input High Voltage 0.9 — — V

Table 2-15. BOOTSELECT and MSID[1:0] DC Specifications

Symbol Parameter Min Typ Max Unit Notes

Input Low Voltage — — 0.24 V

Input High Voltage 0.96 — — V -

NOTES:

1. These parameters are not tested and are based on design simulations.

2.6.3.1 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-8 for details on which GTL+ signals do not in clude on-die termination.

Electrical Specifications

Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 2-16 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) must be generated on the moth erboard using high precision voltage divider circuits.

Table 2-16. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_PU GTLREF pull up resistor 124 * 0.99 124 124 * 1.01 Ω GTLREF_PD GTLREF pull down resistor 210 * 0.99 210 210 * 1.01 Ω

PULLUP

RTT

COMP[1:0]

COMP[3:2]

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLREF land).

3. These pull-ups are to VTT.

4. RTT is the on-die termination resistance measured at VTT/2 of the GTL+ output driver. The IMPSEL pin is used to select a 50Ω or 60Ω buffer and R

5. COMP resistance must be provided on the system board with 1% resistors. COMP[1:0] resistors are to VSS. COMP[3:2] resistors are to V

On die pullup for BOOTSELECT signal

60 Ω Platform Termination Resistance

50 Ω Platform Termination Resistance

60 Ω Platform COMP Resistance

50 Ω Platform COMP Resistance

60 Ω Platform COMP Resistance

50 Ω Platform COMP Resistance

value.

500 - 5000 Ω

41 50 58 Ω

37 45 52 Ω

59.8 60.4 61 Ω

49.9 * 0.99 49.9 49.9 * 1.01 Ω

59.8 60.4 61 Ω

49.9 * 0.99 49.9 49.9 * 1.01 Ω

2 2

Datasheet 31

Electrical Specifications

2.7 Clock Specifications

2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor . As in previous generation processors, the Pentium D processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The Pentium D processor uses a differential clocking implementation.

Table 2-17. Core Frequency to FSB Multiplier Configuration

Multiplication of System Core Frequency to FSB Frequency

1/14 RESERVED 2.80 GHz 1/15 RESERVED 3 GHz 1/16 RESERVED 3.20 GHz 1/17 RESERVED RESERVED 1/18 RESERVED RESERVED 1/19 RESERVED RESERVED 1/20 2.66 GHz RESERVED 1/21 RESERVED RESERVED -

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

Core Frequency (133 MHz BCLK/

533 MHz FSB)

2.7.2 FSB Frequency Select Signals

Upon power up, the front side bus frequency is set to the maximum supported by the individual processor. BSEL[2:0] are open-drain outputs that must be pulled up to V the front side bus frequency. Refer to Table 2-10 for DC specifications. Table 2-18 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. Individual processors will only operate at their specified front side bus clock frequency.

Core Frequency (200 MHz BCLK/

800 MHz FSB)

1, 2

Notes

, and are used to select

The Pentium D processor 840, 830, and 820 operate at 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency). The Pentium processor 805 operates at 533 MHz FSB frequency (selected by a 133 MHz BCLK[1:0] frequency).

32 Datasheet

Table 2-18. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L RESERVED L L H 133 MHz L H H RESERVED L H L 200 MHz H L L RESERVED H L H RESERVED H H H RESERVED H H L RESERVED

2.7.3 Phase Lock Loop (PLL) and Filter

and V

CCA

CCIOPLL

processor. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from V

are power sources required by the PLL clock generators for the Pentium D

Electrical Specifications

The AC low-pass requirements, with input at V

are as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-4.

Datasheet 33

Electrical Specifications

Figure 2-4. Phase Lock Loop (PLL) Filter Requirements

0.2 dB 0 dB

–0.5 dB

Forbidden

–28 dB

–34 dB

NOTES:

1. Diagram not to scale.

2. No specifications for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

4. fcore represents the maximum core frequency supported by the platform.

Zone

Passband

Forbidden

Zone

1 MHz 66 MHz fcorefpeak1 HzDC

High

Frequency

Band

34 Datasheet

Package Mechanical Specifications

3 Package Mechanical

Specifications

The Intel® Pentium® D processor is packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.

The package components shown in Figure 3-1 include the following:

• Integrated Heat Spreader (IHS)

• Thermal Interface Material (TIM)

• Processor core (die)

• Package substrate

• Capacitors

Figure 3-1. Processor Package Assembly Sketch

Core (die)

IHS

Substrate

System Board

NOTE:

1. Socket and motherboard are included for reference and are not part of processor package.

3.1 Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-4. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include:

• Package reference with tolerances (total height, length, width, etc.)

• IHS parallelism and tilt

• Land dimensions

• Top-side and back-side component keep-out dimensions

• Reference datums

• All drawing dimensions are in mm [in].

TIM

Capacitors

LGA775 Socket

Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installati on of

the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.

Datasheet 35

Package Mechanical Specifications

Figure 3-2. Processor Package Drawing 1

36 Datasheet

Figure 3-3. Processor Package Drawing 2

Package Mechanical Specifications

Datasheet 37

Package Mechanical Specifications

Figure 3-4. Processor Package Drawing 3

38 Datasheet

Package Mechanical Specifications

3.2 Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.

The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.

3.3 Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package. These

mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum

Table 3-1. Processor Loading Specifications

loading specification must be maintained by any thermal and mechanical solutions.

Parameter Minimum Maximum Notes

Static 80 N [18 lbf] 311 N [70 lbf]

Dynamic — 756 N [170 lbf]

NOTES:

1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package.

3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and does not include the limits of the processor socket.

4. Dynamic loading is defined as the sum of the load on the package from a 1 lb heatsink mass accelerating through a 11 ms trapezoidal pulse of 50 g and the maximum static load.

3.4 Package Handling Guidelines

Table 3-2 includes a list of guideli nes on package hand ling in terms of recommended maximum

loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.

Table 3-2. Package Handling Guidelines

Parameter Maximum Recommended Notes

Shear 311 N [70 lbf] Tensile 111 N [25 lbf] Torque 3.95 N-m [35 lbf-in]

NOTES:

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

2. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.

3. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface.

4. These guidelines are based on limited testing for design characterization.

1, 2, 3

1, 3, 4

1, 4 2, 4 3, 4

Datasheet 39

Package Mechanical Specifications

3.5 Package Insertion Specifications

The Pentium D processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide.

3.6 Processor Mass Specification

The typical mass of the Pentium D processor is 22.03 g [0.78 oz]. This mass [weight] includes all the components that are included in the package.

3.7 Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3. Processor Materials

Component Material

Integrated Heat Spreader (IHS) Nickel Plated Copper

Substrate Fiber Reinforced Resin

Substrate Lands Gold Plated Copper

3.8 Processor Markings

Figure 3-5 and Figure 3-6 show the topside markings on the processor for the Pentium D processor

800 sequence. These diagrams are to aid in the identification of the Pentium D processor.

Figure 3-5. Processor Top-Side Marking Example (Intel® Pentium® D Processors 840, 830,

820)

Brand

Processor Number/ S-Spec/

Country of Assy

Frequency/L2 Cache/Bus/

775_VR_CONFIG_05x

FPO

INTEL XXXXXXXX

840 SLxxx [COO]

3.20GHZ/2M/800/05B

[FPO]

‘04

Unique Unit

2-D Matrix Mark

ATPO S/N

40 Datasheet

Identifier ATPO Serial #

Package Mechanical Specifications

Figure 3-6. Processor Top-Side Marking Example (Intel® Pentium® D Processor 805)

Brand

Processor Number/ S-Spec/

Country of Assy

Frequency/L2 Cache/Bus/

775_VR_CONFIG_05x

FPO

INTEL XXXXXXXX

2.66GHZ/2M/533/05A

[FPO] [e4]

‘04

805 SLxxx [COO]

Pb-free SLI designator

2-D Matrix Mark

Unique Unit Identifier ATPO Serial #

ATPO S/N

Datasheet 41

Package Mechanical Specifications

3.9 Processor Land Coordinates

Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to

Figure 3-7. Processor Land Coordinates, Top View

throughout the document to identify processor lands.

/ V

89101112131415161718192021222324252627282930

1234567

AN AM AL AK

AJ AH AG

V U T R P N M

J H G F E D C B A

Socket LGA775

Quadrants

Top View

AL AK AJ AH

AF AE AD AC AB AA

Address /

W V

Common Clock /

U T R P N M L K J H G F E D C B A

123456789101112131415161718192021222324252627282930

Async

VTT / Clocks Data

42 Datasheet

Land Listing and Signal Descriptions

4 Land Listing and Signal

Descriptions

This chapter provides the processor land assignment and signal descriptions.

4.1 Processor Land Assignments

This section contains the land listings for the Intel® Pentium® D processor. The landout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the landout arranged by land number and they show the physical location of each signal on the package land array (top view). Table 4-1 is a listing of all processor lands ordered alphabetically by land (signal) name. Table 4-2 is also a listing of all processor lands; the ordering is by land number.

43 Datasheet

Land Listing and Signal Descriptions

Figure 4-1. Landout Diagram (Top View – Left Side)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VCC VCC VCC VCC VCC VCC AB VSS VSS VSS VSS VSS VSS VSS VSS

AA VSS VSS VSS VSS VSS VSS VSS VSS

Y VCC VCC VCC VCC VCC VCC VCC VCC

W VCC VCC VCC VCC VCC VCC VCC VCC

V VSS VSS VSS VSS VSS VSS VSS VSS

U VCC VCC VCC VCC VCC VCC VCC VCC

T VCC VCC VCC VCC VCC VCC VCC VCC

R VSS VSS VSS VSS VSS VSS VSS VSS

P VSS VSS VSS VSS VSS VSS VSS VSS

N VCC VCC VCC VCC VCC VCC VCC VCC

M VCC VCC VCC VCC VCC VCC VCC VCC

L VSS VSS VSS VSS VSS VSS VSS VSS

K VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DP3# DP0# VCC

F E

C VTT VTT VTT VTT VTT VTT VSS

B A

GTLREF

BSEL1

BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31#

VTT VTT VTT VTT VTT VTT VSS VCCPLL D46# VSS D48# DBI2# VSS D49# RSVD VSS

VTT VTT VTT VTT VTT VTT VSS VSSA D63# D59# VSS D60# D57# VSS D55# D53# VTT VTT VTT VTT VTT VTT VSS VCCA D62# VSS RSVD D61# VSS D56# DSTBN3# VSS

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DP2# DP1#

_SEL

RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS D43# D41# VSS D38# D37# VSS D30#

VSS VSS VSS VSS VSS FC10 RSVD D45# D42# VSS D40# D39# VSS D34# D33#

VCCIO

VSS D58# DBI3# VSS D54# DSTBP3# VSS D51#

PLL

44 Datasheet

Land Listing and Signal Descriptions

Figure 4-2. Landout Diagram (Top View – Right Side)

14 13 12 11 10 9 8 7 6 5 4 3 2 1

VCC VSS VCC VCC VSS VCC VCC FC16

VCC VSS VCC VCC VSS VCC VCC FC12 VTTPWRGD FC11 VSS VID2 VID0 VSS AM VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VSS PROCHOT# THERMDA AL VCC VSS VCC VCC VSS VCC VCC VSS FORCEPR# VSS VID4 ITP_CLK0 VSS THERMDC AK VCC VSS VCC VCC VSS VCC VCC VSS A35# A34# VSS ITP_CLK1 BPM0# BPM1# AJ VCC VSS VCC VCC VSS VCC VCC VSS VSS A33# A32# VSS RSVD VSS AH VCC VSS VCC VCC VSS VCC VCC VSS A29# A31# A30# BPM5# BPM3# TRST# AG VCC VSS VCC VCC VSS VCC VCC VSS VSS A27# A28# VSS BPM4# TDO AF VCC VSS VCC VCC VSS VCC SKTOCC# VSS RSVD VSS RSVD FC18 VSS TCK AE

VCC VSS A22# ADSTB1# VSS BINIT# BPM2# TDI AD VCC VSS VSS A25# RSVD VSS DBR# TMS AC VCC VSS A17# A24# A26# MCERR# IERR# VSS AB

VCC VSS VSS A23# A21# VSS LL_ID1

VCC VSS A19# VSS A20# FC17 VSS

VCC VSS A18# A16# VSS TESTHI1 TESTHI12 MSID0 W VCC VSS VSS A14# A15# VSS LL_ID0 MSID1 V VCC VSS A10# A12# A13# AP1# AP0# VSS U VCC VSS VSS A9# A11# VSS FC4 COMP1 T

VCC VSS ADSTB0# VSS A8#

VCC VSS A4# RSVD VSS INIT# SMI# TESTHI11 P VCC VSS VSS RSVD RSVD VSS IGNNE# PWRGOOD N

VCC VSS REQ2# A5# A7# STPCLK#

VCC VSS VSS A3# A6# VSS TESTHI13 LINT1 L VCC VSS REQ3# VSS REQ0# A20M# VSS LINT0 K

VCC VCC VCC VCC VCC VCC VCC VSS REQ4# REQ1# VSS FC22 FC3

VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI10 RSP# VSS GTLREF1 GTLREF0

VSS_MB_

REGULATION

VCC_MB_

REGULATION

VSS_

SENSE

VCC_

SENSE

FERR#/

PBE#

VSS VSS AN

VTT_OUT_

RIGHT

BOOT

SELECT

VSS COMP3 R

THER-

MTRIP#

VSS M

VTT_OUT_

LEFT

D29# D27# DSTBN1# DBI1# RSVD D16# BPRI# DEFER# RSVD FC7 TESTHI9 TESTHI8 COMP2 VSS G D28# VSS D24# D23# VSS D18# D17# VSS IMPSEL RS1# VSS BR0# FC5 F

VSS D26# DSTBP1# VSS D21# D19# VSS RSVD RSVD FC20 HITM# TRDY# VSS E

RSVD D25# VSS D15# D22# VSS D12# D20# VSS VSS HIT# VSS ADS# RSVD D

D52# VSS D14# D11# VSS RSVD DSTBN0# VSS D3# D1# VSS LOCK# BNR# DRDY#

VSS FC19 D13# VSS D10# DSTBP0# VSS D6# D5# VSS D0# RS0# DBSY# VSS B

D50# COMP0 VSS D9# D8# VSS DBI0# D7# VSS D4# D2# RS2# VSS

14 13 12 11 10 9 8 7 6 5 4 3 2 1

Datasheet 45

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

A3# L5 Source Synch Input/Output A4# P6 Source Synch Input/Output A5# M5 Source Synch Input/Output A6# L4 Source Synch Input/Output A7# M4 Source Synch Input/Output A8# R4 Source Synch Input/Output

A9# T5 Source Synch Input/Output A10# U6 Source Synch Input/Output A11# T4 Source Synch Input/Output A12# U5 Source Synch Input/Output A13# U4 Source Synch Input/Output A14# V5 Source Synch Input/Output A15# V4 Source Synch Input/Output A16# W5 Source Synch Input/Output A17# AB6 Source Synch Input/Output A18# W6 Source Synch Input/Output A19# Y6 Source Synch Input/Output A20# Y4 Source Synch Input/Output

A20M# K3 Asynch GTL+ Input

A21# AA4 Source Synch Input/Output A22# AD6 Source Synch Input/Output A23# AA5 Source Synch Input/Output A24# AB5 Source Synch Input/Output A25# AC5 Source Synch Input/Output A26# AB4 Source Synch Input/Output A27# AF5 Source Synch Input/Output A28# AF4 Source Synch Input/Output A29# AG6 Source Synch Input/Output A30# AG4 Source Synch Input/Output A31# AG5 Source Synch Input/Output A32# AH4 Source Synch Input/Output A33# AH5 Source Synch Input/Output A34# AJ5 Source Synch Input/Output A35# AJ6 Source Synch Input/Output

ADS# D2 Common Clock Input/Output ADSTB0# R6 Source Synch Input/Output ADSTB1# AD5 Source Synch Input/Output

AP0# U2 Common Clock Input/Output AP1# U3 Common Clock Input/Output

BCLK0 F28 Clock Input

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

BCLK1 G28 Clock Input BINIT# AD3 Common Clock Input/Output

BNR# C2 Common Clock Input/Output

BOOTSELECT Y1 Power/Other Input

BPM0# AJ2 Common Clock Input/Output BPM1# AJ1 Common Clock Input/Output BPM2# AD2 Common Clock Input/Output BPM3# AG2 Common Clock Input/Output BPM4# AF2 Common Clock Input/Output BPM5# AG3 Common Clock Input/Output

BPRI# G8 Common Clock Input

BR0# F3 Common Clock Input/Output BSEL0 G29 Power/Other Output BSEL1 H30 Power/Other Output BSEL2 G30 Power/Other Output

COMP0 A13 Power/Other Input COMP1 T1 Power/Other Input COMP2 G2 Power/Other Input COMP3 R1 Power/Other Input

D0# B4 Source Synch Input/Output D1# C5 Source Synch Input/Output D2# A4 Source Synch Input/Output D3# C6 Source Synch Input/Output D4# A5 Source Synch Input/Output D5# B6 Source Synch Input/Output D6# B7 Source Synch Input/Output D7# A7 Source Synch Input/Output D8# A10 Source Synch Input/Output

D9# A11 Source Synch Input/Output D10# B10 Source Synch Input/Output D11# C11 Source Synch Input/Output D12# D8 Source Synch Input/Output D13# B12 Source Synch Input/Output D14# C12 Source Synch Input/Output D15# D11 Source Synch Input/Output D16# G9 Source Synch Input/Output D17# F8 Source Synch Input/Output D18# F9 Source Synch Input/Output D19# E9 Source Synch Input/Output D20# D7 Source Synch Input/Output

Land #Signal Buffer

Type

Direction

46 Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

D21# E10 Source Synch Input/Output D22# D10 Source Synch Input/Output D23# F11 Source Synch Input/Output D24# F12 Source Synch Input/Output D25# D13 Source Synch Input/Output D26# E13 Source Synch Input/Output D27# G13 Source Synch Input/Output D28# F14 Source Synch Input/Output D29# G14 Source Synch Input/Output D30# F15 Source Synch Input/Output D31# G15 Source Synch Input/Output D32# G16 Source Synch Input/Output D33# E15 Source Synch Input/Output D34# E16 Source Synch Input/Output D35# G18 Source Synch Input/Output D36# G17 Source Synch Input/Output D37# F17 Source Synch Input/Output D38# F18 Source Synch Input/Output D39# E18 Source Synch Input/Output D40# E19 Source Synch Input/Output D41# F20 Source Synch Input/Output D42# E21 Source Synch Input/Output D43# F21 Source Synch Input/Output D44# G21 Source Synch Input/Output D45# E22 Source Synch Input/Output D46# D22 Source Synch Input/Output D47# G22 Source Synch Input/Output D48# D20 Source Synch Input/Output D49# D17 Source Synch Input/Output D50# A14 Source Synch Input/Output D51# C15 Source Synch Input/Output D52# C14 Source Synch Input/Output D53# B15 Source Synch Input/Output D54# C18 Source Synch Input/Output D55# B16 Source Synch Input/Output D56# A17 Source Synch Input/Output D57# B18 Source Synch Input/Output D58# C21 Source Synch Input/Output D59# B21 Source Synch Input/Output D60# B19 Source Synch Input/Output

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

D61# A19 Source Synch Input/Output D62# A22 Source Synch Input/Output

D63# B22 Source Synch Input/Output DBI0# A8 Source Synch Input/Output DBI1# G11 Source Synch Input/Output DBI2# D19 Source Synch Input/Output DBI3# C20 Source Synch Input/Output DBR# AC2 Power/Other Output

DBSY# B2 Common Clock Input/Output

DEFER# G7 Common Clock Input

DP0# J16 Common Clock Input/Output DP1# H15 Common Clock Input/Output DP2# H16 Common Clock Input/Output DP3# J17 Common Clock Input/Output

DRDY# C1 Common Clock Input/Output DSTBN0# C8 Source Synch Input/Output DSTBN1# G12 Source Synch Input/Output DSTBN2# G20 Source Synch Input/Output DSTBN3# A16 Source Synch Input/Output DSTBP0# B9 Source Synch Input/Output DSTBP1# E12 Source Synch Input/Output DSTBP2# G19 Source Synch Input/Output DSTBP3# C17 Source Synch Input/Output

FC3 J2 Power/Other Input FC4 T2 Power/Other Input FC5 F2 Common Clock Input FC7 G5 Source Synch Output

FC10 E24 Power/Other Input

FC11 AM5 Power/Other Output FC12 AM7 Power/Other Output FC16 AN7 Power/Other Output FC17 Y3 Power/Other Input FC18 AE3 Power/Other Input FC19 B13 Power/Other Input FC20 E5 Power/Other Input FC22 J3 Power/Other Input

FERR#/PBE# R3 Asynch GTL+ Output

FORCEPR# AK6 Asynch GTL+ Input

GTLREF_SEL H29 Power/Other Output

GTLREF0 H1 Power/Other Input

Land #Signal Buffer

Type

Direction

Datasheet 47

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

GTLREF1 H2 Power/Other Input

HIT# D4 Common Clock Input/Output HITM# E4 Common Clock Input/Output IERR# AB2 Asynch GTL+ Output

IGNNE# N2 Asynch GTL+ Input IMPSEL F6 Power/Other Input

INIT# P3 Asynch GTL+ Input

ITP_CLK0 AK3 TAP Input ITP_CLK1 AJ3 TAP Input

LINT0 K1 Asynch GTL+ Input

LINT1 L1 Asynch GTL+ Input LL_ID0 V2 Power/Other Output LL_ID1 AA2 Power/Other Output LOCK# C3 Common Clock Input/Output

MCERR# AB3 Common Clock Input/Output

MSID0 W1 Power/Other Input MSID1 V1 Power/Other Input

PROCHOT# AL2 Asynch GTL+

PWRGOOD N1 Power/Other Input

REQ0# K4 Source Synch Input/Output REQ1# J5 Source Synch Input/Output REQ2# M6 Source Synch Input/Output REQ3# K6 Source Synch Input/Output REQ4# J6 Source Synch Input/Output

RESERVED A20 RESERVED AC4 RESERVED AE4 RESERVED AE6 RESERVED AH2 RESERVED C9 RESERVED D1 RESERVED D14 RESERVED D16 RESERVED E23 RESERVED E6 RESERVED E7 RESERVED F23 RESERVED F29 RESERVED G10 RESERVED N4

Land #Signal Buffer

Type

Direction

Output or

Input/Output

Table 4-1. Alphabetical Land

Assignments

Land Name

RESERVED N5 RESERVED P5 RESERVED G6

RESET# G23 Common Clock Input

RS0# B3 Common Clock Input RS1# F5 Common Clock Input RS2# A3 Common Clock Input RSP# H4 Common Clock Input

SKTOCC# AE8 Power/Other Output

SMI# P2 Asynch GTL+ Input

STPCLK# M3 Asynch GTL+ Input

TCK AE1 TAP Input

TDI AD1 TAP Input

TDO AF1 TAP Output TESTHI0 F26 Power/Other Input TESTHI1 W3 Power/Other Input TESTHI2 F25 Power/Other Input TESTHI3 G25 Power/Other Input TESTHI4 G27 Power/Other Input TESTHI5 G26 Power/Other Input TESTHI6 G24 Power/Other Input TESTHI7 F24 Power/Other Input TESTHI8 G3 Power/Other Input TESTHI9 G4 Power/Other Input

TESTHI10 H5 Power/Other Input TESTHI11 P1 Power/Other Input TESTHI12 W2 Power/Other Input

TESTHI13 L2 Asynch GTL+ Input THERMDA AL1 Power/Other THERMDC AK1 Power/Other

THERMTRIP# M2 Asynch GTL+ Output

TMS AC1 TAP Input

TRDY# E3 Common Clock Input

TRST# A G1 TAP Input

VCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power/Other VCC AC24 Power/Other VCC AC25 Power/Other VCC AC26 Power/Other

Land #Signal Buffer

Type

Direction

48 Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

VCC AC27 Power/Other VCC AC28 Power/Other VCC AC29 Power/Other VCC AC30 Power/Other VCC AC8 Power/Other VCC AD23 Power/Other VCC AD24 Power/Other VCC AD25 Power/Other VCC AD26 Power/Other VCC AD27 Power/Other VCC AD28 Power/Other VCC AD29 Power/Other VCC AD30 Power/Other VCC AD8 Power/Other VCC AE11 Power/Other VCC AE12 Power/Other VCC AE14 Power/Other VCC AE15 Power/Other VCC AE18 Power/Other VCC AE19 Power/Other VCC AE21 Power/Other VCC AE22 Power/Other VCC AE23 Power/Other VCC AE9 Power/Other VCC AF11 Power/Other VCC AF12 Power/Other VCC AF14 Power/Other VCC AF15 Power/Other VCC AF18 Power/Other VCC AF19 Power/Other VCC AF21 Power/Other VCC AF22 Power/Other VCC AF8 Power/Other VCC AF9 Power/Other VCC AG11 Power/Other VCC AG12 Power/Other VCC AG14 Power/Other VCC AG15 Power/Other VCC AG18 Power/Other VCC AG19 Power/Other

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

VCC AG21 Power/Other VCC AG22 Power/Other VCC AG25 Power/Other VCC AG26 Power/Other VCC AG27 Power/Other VCC AG28 Power/Other VCC AG29 Power/Other VCC AG30 Power/Other VCC AG8 Power/Other VCC AG9 Power/Other VCC AH11 Power/Other VCC AH12 Power/Other VCC AH14 Power/Other VCC AH15 Power/Other VCC AH18 Power/Other VCC AH19 Power/Other VCC AH21 Power/Other VCC AH22 Power/Other VCC AH25 Power/Other VCC AH26 Power/Other VCC AH27 Power/Other VCC AH28 Power/Other VCC AH29 Power/Other VCC AH30 Power/Other VCC AH8 Power/Other VCC AH9 Power/Other VCC AJ11 Power/Other VCC AJ12 Power/Other VCC AJ14 Power/Other VCC AJ15 Power/Other VCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power/Other VCC AJ26 Power/Other VCC AJ8 Power/Other VCC AJ9 Power/Other VCC AK11 Power/Other VCC AK12 Power/Other

Land #Signal Buffer

Type

Direction

Datasheet 49

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

VCC AK14 Power/Other VCC AK15 Power/Other VCC AK18 Power/Other VCC AK19 Power/Other VCC AK21 Power/Other VCC AK22 Power/Other VCC AK25 Power/Other VCC AK26 Power/Other VCC AK8 Power/Other VCC AK9 Power/Other VCC AL11 Power/Other VCC AL12 Power/Other VCC AL14 Power/Other VCC AL15 Power/Other VCC AL18 Power/Other VCC AL19 Power/Other VCC AL21 Power/Other VCC AL22 Power/Other VCC AL25 Power/Other VCC AL26 Power/Other VCC AL29 Power/Other VCC AL30 Power/Other VCC AL8 Power/Other VCC AL9 Power/Other VCC AM11 Power/Other VCC AM12 Power/Other VCC AM14 Power/Other VCC AM15 Power/Other VCC AM18 Power/Other VCC AM19 Power/Other VCC AM21 Power/Other VCC AM22 Power/Other VCC AM25 Power/Other VCC AM26 Power/Other VCC AM29 Power/Other VCC AM30 Power/Other VCC AM8 Power/Other VCC AM9 Power/Other VCC AN11 Power/Other VCC AN12 Power/Other

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

VCC AN14 Power/Other VCC AN15 Power/Other VCC AN18 Power/Other VCC AN19 Power/Other VCC AN21 Power/Other VCC AN22 Power/Other VCC AN25 Power/Other VCC AN26 Power/Other VCC AN29 Power/Other VCC AN30 Power/Other VCC AN8 Power/Other VCC AN9 Power/Other VCC J10 Power/Other VCC J11 Power/Other VCC J12 Power/Other VCC J13 Power/Other VCC J14 Power/Other VCC J15 Power/Other VCC J18 Power/Other VCC J19 Power/Other VCC J20 Power/Other VCC J21 Power/Other VCC J22 Power/Other VCC J23 Power/Other VCC J24 Power/Other VCC J25 Power/Other VCC J26 Power/Other VCC J27 Power/Other VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other VCC K23 Power/Other VCC K24 Power/Other VCC K25 Power/Other VCC K26 Power/Other VCC K27 Power/Other VCC K28 Power/Other VCC K29 Power/Other

Land #Signal Buffer

Type

Direction

50 Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

VCC K30 Power/Other VCC K8 Power/Other VCC L8 Power/Other VCC M23 Power/Other VCC M24 Power/Other VCC M25 Power/Other VCC M26 Power/Other VCC M27 Power/Other VCC M28 Power/Other VCC M29 Power/Other VCC M30 Power/Other VCC M8 Power/Other VCC N23 Power/Other VCC N24 Power/Other VCC N25 Power/Other VCC N26 Power/Other VCC N27 Power/Other VCC N28 Power/Other VCC N29 Power/Other VCC N30 Power/Other VCC N8 Power/Other VCC P8 Power/Other VCC R8 Power/Other VCC T23 Power/Other VCC T24 Power/Other VCC T25 Power/Other VCC T26 Power/Other VCC T27 Power/Other VCC T28 Power/Other VCC T29 Power/Other VCC T30 Power/Other VCC T8 Power/Other VCC U23 Power/Other VCC U24 Power/Other VCC U25 Power/Other VCC U26 Power/Other VCC U27 Power/Other VCC U28 Power/Other VCC U29 Power/Other VCC U30 Power/Other

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

VCC U8 Power/Other VCC V8 Power/Other VCC W23 Power/Other VCC W24 Power/Other VCC W25 Power/Other VCC W26 Power/Other VCC W27 Power/Other VCC W28 Power/Other VCC W29 Power/Other VCC W30 Power/Other VCC W8 Power/Other VCC Y23 Power/Other VCC Y24 Power/Other VCC Y25 Power/Other VCC Y26 Power/Other VCC Y27 Power/Other VCC Y28 Power/Other VCC Y29 Power/Other VCC Y30 Power/Other VCC Y8 Power/Other

VCC_MB_

REGULATION

VCC_SENSE AN3 Power/Other Output

VCCA A23 Power/Other

VCCIOPLL C23 Power/Other

VCCPLL D23 Power/Other Input

VID0 AM2 Power/Other Output VID1 AL5 Power/Other Output VID2 AM3 Power/Other Output VID3 AL6 Power/Other Output VID4 AK4 Power/Other Output VID5 AL4 Power/Other Output

VSS A12 Power/Other VSS A15 Power/Other VSS A18 Power/Other VSS A2 Power/Other VSS A21 Power/Other VSS A24 Power/Other VSS A6 Power/Other VSS A9 Power/Other VSS AA23 Power/Other

Land #Signal Buffer

AN5 Power/Other Output

Type

Direction

Datasheet 51

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

VSS AA24 Power/Other VSS AA25 Power/Other VSS AA26 Power/Other VSS AA27 Power/Other VSS AA28 Power/Other VSS AA29 Power/Other VSS AA3 Power/Other VSS AA30 Power/Other VSS AA6 Power/Other VSS AA7 Power/Other VSS AB1 Power/Other VSS AB23 Power/Other VSS AB24 Power/Other VSS AB25 Power/Other VSS AB26 Power/Other VSS AB27 Power/Other VSS AB28 Power/Other VSS AB29 Power/Other VSS AB30 Power/Other VSS AB7 Power/Other VSS AC3 Power/Other VSS AC6 Power/Other VSS AC7 Power/Other VSS AD4 Power/Other VSS AD7 Power/Other VSS AE10 Power/Other VSS AE13 Power/Other VSS AE16 Power/Other VSS AE17 Power/Other VSS AE2 Power/Other VSS AE20 Power/Other VSS AE24 Power/Other VSS AE25 Power/Other VSS AE26 Power/Other VSS AE27 Power/Other VSS AE28 Power/Other VSS AE29 Power/Other VSS AE30 Power/Other VSS AE5 Power/Other VSS AE7 Power/Other

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

VSS AF10 Power/Other VSS AF13 Power/Other VSS AF16 Power/Other VSS AF17 Power/Other VSS AF20 Power/Other VSS AF23 Power/Other VSS AF24 Power/Other VSS AF25 Power/Other VSS AF26 Power/Other VSS AF27 Power/Other VSS AF28 Power/Other VSS AF29 Power/Other VSS AF3 Power/Other VSS AF30 Power/Other VSS AF6 Power/Other VSS AF7 Power/Other VSS AG10 Power/Other VSS AG13 Power/Other VSS AG16 Power/Other VSS AG17 Power/Other VSS AG20 Power/Other VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/Other VSS AH10 Power/Other VSS AH13 Power/Other VSS AH16 Power/Other VSS AH17 Power/Other VSS AH20 Power/Other VSS AH23 Power/Other VSS AH24 Power/Other VSS AH3 Power/Other VSS AH6 Power/Other VSS AH7 Power/Other VSS AJ10 Power/Other VSS AJ13 Power/Other VSS AJ16 Power/Other VSS AJ17 Power/Other VSS AJ20 Power/Other

Land #Signal Buffer

Type

Direction

52 Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

VSS AJ23 Power/Other VSS AJ24 Power/Other VSS AJ27 Power/Other VSS AJ28 Power/Other VSS AJ29 Power/Other VSS AJ30 Power/Other VSS AJ4 Power/Other VSS AJ7 Power/Other VSS AK10 Power/Other VSS AK13 Power/Other VSS AK16 Power/Other VSS AK17 Power/Other VSS AK2 Power/Other VSS AK20 Power/Other VSS AK23 Power/Other VSS AK24 Power/Other VSS AK27 Power/Other VSS AK28 Power/Other VSS AK29 Power/Other VSS AK30 Power/Other VSS AK5 Power/Other VSS AK7 Power/Other VSS AL10 Power/Other VSS AL13 Power/Other VSS AL16 Power/Other VSS AL17 Power/Other VSS AL20 Power/Other VSS AL23 Power/Other VSS AL24 Power/Other VSS AL27 Power/Other VSS AL28 Power/Other VSS AL3 Power/Other VSS AL7 Power/Other VSS AM1 Power/Other VSS AM10 Power/Other VSS AM13 Power/Other VSS AM16 Power/Other VSS AM17 Power/Other VSS AM20 Power/Other VSS AM23 Power/Other

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

VSS AM24 Power/Other VSS AM27 Power/Other VSS AM28 Power/Other VSS AM4 Power/Other VSS AN1 Power/Other VSS AN10 Power/Other VSS AN13 Power/Other VSS AN16 Power/Other VSS AN17 Power/Other VSS AN2 Power/Other VSS AN20 Power/Other VSS AN23 Power/Other VSS AN24 Power/Other VSS AN27 Power/Other VSS AN28 Power/Other VSS B1 Power/Other VSS B11 Power/Other VSS B14 Power/Other VSS B17 Power/Other VSS B20 Power/Other VSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS C10 Power/Other VSS C13 Power/Other VSS C16 Power/Other VSS C19 Power/Other VSS C22 Power/Other VSS C24 Power/Other VSS C4 Power/Other VSS C7 Power/Other VSS D12 Power/Other VSS D15 Power/Other VSS D18 Power/Other VSS D21 Power/Other VSS D24 Power/Other VSS D3 Power/Other VSS D5 Power/Other VSS D6 Power/Other VSS D9 Power/Other

Land #Signal Buffer

Type

Direction

Datasheet 53

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

VSS E11 Power/Other VSS E14 Power/Other VSS E17 Power/Other VSS E2 Power/Other VSS E20 Power/Other VSS E25 Power/Other VSS E26 Power/Other VSS E27 Power/Other VSS E28 Power/Other VSS E29 Power/Other VSS E8 Power/Other VSS F10 Power/Other VSS F13 Power/Other VSS F16 Power/Other VSS F19 Power/Other VSS F22 Power/Other VSS F4 Power/Other VSS F7 Power/Other VSS G1 Power/Other VSS H10 Power/Other VSS H11 Power/Other VSS H12 Power/Other VSS H13 Power/Other VSS H14 Power/Other VSS H17 Power/Other VSS H18 Power/Other VSS H19 Power/Other VSS H20 Power/Other VSS H21 Power/Other VSS H22 Power/Other VSS H23 Power/Other VSS H24 Power/Other VSS H25 Power/Other VSS H26 Power/Other VSS H27 Power/Other VSS H28 Power/Other VSS H3 Power/Other VSS H6 Power/Other VSS H7 Power/Other VSS H8 Power/Other

Land #Signal Buffer

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

VSS H9 Power/Other VSS J4 Power/Other VSS J7 Power/Other VSS K2 Power/Other VSS K5 Power/Other VSS K7 Power/Other VSS L23 Power/Other VSS L24 Power/Other VSS L25 Power/Other VSS L26 Power/Other VSS L27 Power/Other VSS L28 Power/Other VSS L29 Power/Other VSS L3 Power/Other VSS L30 Power/Other VSS L6 Power/Other VSS L7 Power/Other VSS M1 Power/Other VSS M7 Power/Other VSS N3 Power/Other VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Other VSS P28 Power/Other VSS P29 Power/Other VSS P30 Power/Other VSS P4 Power/Other VSS P7 Power/Other VSS R2 Power/Other VSS R23 Power/Other VSS R24 Power/Other VSS R25 Power/Other VSS R26 Power/Other VSS R27 Power/Other VSS R28 Power/Other VSS R29 Power/Other

Land #Signal Buffer

Type

Direction

54 Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Land Name

VSS R30 Power/Other VSS R5 Power/Other VSS R7 Power/Other VSS T3 Power/Other VSS T6 Power/Other VSS T7 Power/Other VSS U1 Power/Other VSS U7 Power/Other VSS V23 Power/Other VSS V24 Power/Other VSS V25 Power/Other VSS V26 Power/Other VSS V27 Power/Other VSS V28 Power/Other VSS V29 Power/Other VSS V3 Power/Other VSS V30 Power/Other VSS V6 Power/Other VSS V7 Power/Other VSS W4 Power/Other VSS W7 Power/Other VSS Y2 Power/Other VSS Y5 Power/Other VSS Y7 Power/Other

VSS_MB_

REGULATION

VSS_SENSE AN4 Power/Other Output

VSSA B23 Power/Other

Land #Signal Buffer

AN6 Power/Other Output

Type

Direction

Table 4-1. Alphabetical Land

Assignments

Land Name

VTT A25 Power/Other VTT A26 Power/Other VTT A27 Power/Other VTT A28 Power/Other VTT A29 Power/Other VTT A30 Power/Other VTT B25 Power/Other VTT B26 Power/Other VTT B27 Power/Other VTT B28 Power/Other VTT B29 Power/Other VTT B30 Power/Other VTT C25 Power/Other VTT C26 Power/Other VTT C27 Power/Other VTT C28 Power/Other VTT C29 Power/Other VTT C30 Power/Other VTT D25 Power/Other VTT D26 Power/Other VTT D27 Power/Other VTT D28 Power/Other VTT D29 Power/Other VTT D30 Power/Other

VTT_OUT_LEFT J1 Power/Other Output

VTT_OUT_RIGHT AA1 Power/Other Output

VTT_SEL F27 Power/Other Output

VTTPWRGD AM6 Power/Other Input

Land #Signal Buffer

Type

Direction

Datasheet 55

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

A2 VSS Power/Other A3 RS2# Common Clock Input A4 D2# Source Synch Input/Output A5 D4# Source Synch Input/Output A6 VSS Power/Other A7 D7# Source Synch Input/Output A8 DBI0# Source Synch Input/Output A9 VSS Power/Other

A10 D8# Source Synch Input/Output

A11 D9# Source Synch Input/Output A12 VSS Power/Other A13 COMP0 Power/Other Input A14 D50# Source Synch Input/Output A15 VSS Power/Other A16 DSTBN3# Source Synch Input/Output A17 D56# Source Synch Input/Output A18 VSS Power/Other A19 D61# Source Synch Input/Output A20 RESERVED A21 VSS Power/Other A22 D62# Source Synch Input/Output A23 VCCA Power/Other A24 VSS Power/Other A25 VTT Power/Other A26 VTT Power/Other A27 VTT Power/Other A28 VTT Power/Other A29 VTT Power/Other A30 VTT Power/Other

B1 VSS Power/Other B2 DBSY# Common Clock Input/Output B3 RS0# Common Clock Input B4 D0# Source Synch Input/Output B5 VSS Power/Other B6 D5# Source Synch Input/Output B7 D6# Source Synch Input/Output B8 VSS Power/Other B9 DSTBP0# Source Synch Input/Output

B10 D10# Source Synch Input/Output

B11 VSS Power/Other B12 D13# Source Synch Input/Output

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

B13 FC19 Power/Other Input B14 VSS Power/Other B15 D53# Source Synch Input/Output B16 D55# Source Synch Input/Output B17 VSS Power/Other B18 D57# Source Synch Input/Output B19 D60# Source Synch Input/Output B20 VSS Power/Other B21 D59# Source Synch Input/Output B22 D63# Source Synch Input/Output B23 VSSA Power/Other B24 VSS Power/Other B25 VTT Power/Other B26 VTT Power/Other B27 VTT Power/Other B28 VTT Power/Other B29 VTT Power/Other B30 VTT Power/Other

C1 DRDY# Common Clock Input/Output C2 BNR# Common Clock Input/Output C3 LOCK# Common Clock Input/Output C4 VSS Power/Other C5 D1# Source Synch Input/Output C6 D3# Source Synch Input/Output C7 VSS Power/Other C8 DSTBN0# Source Synch Input/Output

C9 RESERVED C10 VSS Power/Other C11 D11# Source Synch Input/Output C12 D14# Source Synch Input/Output C13 VSS Power/Other C14 D52# Source Synch Input/Output C15 D51# Source Synch Input/Output C16 VSS Power/Other C17 DSTBP3# Source Synch Input/Output C18 D54# Source Synch Input/Output C19 VSS Power/Other C20 DBI3# Source Synch Input/Output C21 D58# Source Synch Input/Output C22 VSS Power/Other C23 VCCIOPLL Power/Other

Land Name

Signal Buffer

Type

Direction

56 Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Other C29 VTT Power/Other C30 VTT Power/Other

D1 RESERVED D2 ADS# Common Clock Input/Output D3 VSS Power/Other D4 HIT# Common Clock Input/Output D5 VSS Power/Other D6 VSS Power/Other D7 D20# Source Synch Input/Output D8 D12# Source Synch Input/Output D9 VSS Power/Other

D10 D22# Source Synch Input/Output

D11 D15# Source Synch Input/Output D12 VSS Power/Other D13 D25# Source Synch Input/Output D14 RESERVED D15 VSS Power/Other D16 RESERVED D17 D49# Source Synch Input/Output D18 VSS Power/Other D19 DBI2# Source Synch Input/Output D20 D48# Source Synch Input/Output D21 VSS Power/Other D22 D46# Source Synch Input/Output D23 VCCPLL Power/Other Input D24 VSS Power/Other D25 VTT Power/Other D26 VTT Power/Other D27 VTT Power/Other D28 VTT Power/Other D29 VTT Power/Other D30 VTT Power/Other

E2 VSS Power/Other E3 TRDY# Common Clock Input E4 HITM# Common Clock Input/Output E5 FC20 Power/Other Input

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

E6 RESERVED E7 RESERVED E8 VSS Power/Other

E9 D19# Source Synch Input/Output E10 D21# Source Synch Input/Output E11 VSS Power/Other E12 DSTBP1# Source Synch Input/Output E13 D26# Source Synch Input/Output E14 VSS Power/Other E15 D33# Source Synch Input/Output E16 D34# Source Synch Input/Output E17 VSS Power/Other E18 D39# Source Synch Input/Output E19 D40# Source Synch Input/Output E20 VSS Power/Other E21 D42# Source Synch Input/Output E22 D45# Source Synch Input/Output E23 RESERVED E24 FC10 Power/Other Input E25 VSS Power/Other E26 VSS Power/Other E27 VSS Power/Other E28 VSS Power/Other E29 VSS Power/Other

F2 FC5 Common Clock Input

F3 BR0# Common Clock Input/Output

F4 VSS Power/Other

F5 RS1# Common Clock Input

F6 IMPSEL Power/Other Input

F7 VSS Power/Other

F8 D17# Source Synch Input/Output

F9 D18# Source Synch Input/Output F10 VSS Power/Other F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output F16 VSS Power/Other F17 D37# Source Synch Input/Output F18 D38# Source Synch Input/Output

Land Name

Signal Buffer

Type

Direction

Datasheet 57

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

F19 VSS Power/Other F20 D41# Source Synch Input/Output F21 D43# Source Synch Input/Output F22 VSS Power/Other F23 RESERVED F24 TESTHI7 Power/Other Input F25 TESTHI2 Power/Other Input F26 TESTHI0 Power/Other Input F27 VTT_SEL Power/Other Output F28 BCLK0 Clock Input F29 RESERVED

G1 VSS Power/Other G2 COMP2 Power/Other Input G3 TESTHI8 Power/Other Input G4 TESTHI9 Power/Other Input G5 FC7 Source Synch Output G6 RESERVED G7 DEFER# Common Clock Input G8 BPRI# Common Clock Input

G9 D16# Source Synch Input/Output G10 RESERVED G11 DBI1# Source Synch Input/Output G12 DSTBN1# Source Synch Input/Output G13 D27# Source Synch Input/Output G14 D29# Source Synch Input/Output G15 D31# Source Synch Input/Output G16 D32# Source Synch Input/Output G17 D36# Source Synch Input/Output G18 D35# Source Synch Input/Output G19 DSTBP2# Source Synch Input/Output G20 DSTBN2# Source Synch Input/Output G21 D44# Source Synch Input/Output G22 D47# Source Synch Input/Output G23 RESET# Common Clock Input G24 TESTHI6 Power/Other Input G25 TESTHI3 Power/Other Input G26 TESTHI5 Power/Other Input G27 TESTHI4 Power/Other Input G28 BCLK1 Clock Input G29 BSEL0 Power/Other Output G30 BSEL2 Power/Other Output

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

H1 GTLREF0 Power/Other Input H2 GTLREF1 Power/Other Input H3 VSS Power/Other H4 RSP# Common Clock Input H5 TESTHI10 Power/Other Input H6 VSS Power/Other H7 VSS Power/Other H8 VSS Power/Other

H9 VSS Power/Other H10 VSS Power/Other H11 VSS Power/Other H12 VSS Power/Other H13 VSS Power/Other H14 VSS Power/Other H15 DP1# Common Clock Input/Output H16 DP2# Common Clock Input/Output H17 VSS Power/Other H18 VSS Power/Other H19 VSS Power/Other H20 VSS Power/Other H21 VSS Power/Other H22 VSS Power/Other H23 VSS Power/Other H24 VSS Power/Other H25 VSS Power/Other H26 VSS Power/Other H27 VSS Power/Other H28 VSS Power/Other H29 GTLREF_SEL Power/Other Output H30 BSEL1 Power/Other Output

J1 VTT_O UT_LEFT Power/Other Output J2 FC3 Power/Other Input J3 FC22 Power/Other Input J4 VSS Power/Other J5 REQ1# Source Synch Input/Output J6 REQ4# Source Synch Input/Output J7 VSS Power/Other J8 VCC Power/Other J9 VCC Power/Other

J10 VCC Power/Other

J11 VCC Power/Other

Land Name

Signal Buffer

Type

Direction

58 Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

J12 VCC Power/Other J13 VCC Power/Other J14 VCC Power/Other J15 VCC Power/Other J16 DP0# Common Clock Input/Output J17 DP3# Common Clock Input/Output J18 VCC Power/Other J19 VCC Power/Other J20 VCC Power/Other J21 VCC Power/Other J22 VCC Power/Other J23 VCC Power/Other J24 VCC Power/Other J25 VCC Power/Other J26 VCC Power/Other J27 VCC Power/Other J28 VCC Power/Other J29 VCC Power/Other J30 VCC Power/Other

K1 LINT0 Asynch GTL+ Input K2 VSS Power/Other K3 A20M# Asynch GTL+ Input K4 REQ0# Source Synch Input/Output K5 VSS Power/Other K6 REQ3# Source Synch Input/Output K7 VSS Power/Other

K8 VCC Power/Other K23 VCC Power/Other K24 VCC Power/Other K25 VCC Power/Other K26 VCC Power/Other K27 VCC Power/Other K28 VCC Power/Other K29 VCC Power/Other K30 VCC Power/Other

L1 LINT1 Asynch GTL+ Input

L2 TESTHI13 Asynch GTL+ Input

L3 VSS Power/Other

L4 A6# Source Synch Input/Output

L5 A3# Source Synch Input/Output

L6 VSS Power/Other

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

L7 VSS Power/Other

L8 VCC Power/Other L23 VSS Power/Other L24 VSS Power/Other L25 VSS Power/Other L26 VSS Power/Other L27 VSS Power/Other L28 VSS Power/Other L29 VSS Power/Other L30 VSS Power/Other

M1 VSS Power/Other

M2 THERMTRIP# Asynch GTL+ Output

M3 STPCLK# Asynch GTL+ Input

M4 A7# Source Synch Input/Output

M5 A5# Source Synch Input/Output

M6 REQ2# Source Synch Input/Output

M7 VSS Power/Other

M8 VCC Power/Other M23 V CC Power/Other M24 V CC Power/Other M25 V CC Power/Other M26 V CC Power/Other M27 V CC Power/Other M28 V CC Power/Other M29 V CC Power/Other M30 V CC Power/Other

N1 PWRGOOD Power/Other Input

N2 IGNNE# Asynch GTL+ Input

N3 VSS Power/Other

N4 RESERVED

N5 RESERVED

N6 VSS Power/Other

N7 VSS Power/Other

N8 VCC Power/Other N23 VCC Power/Other N24 VCC Power/Other N25 VCC Power/Other N26 VCC Power/Other N27 VCC Power/Other N28 VCC Power/Other N29 VCC Power/Other

Land Name

Signal Buffer

Type

Direction

Datasheet 59

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

N30 VCC Power/Other

P1 TESTHI11 Power/Other Input P2 SMI# Asynch GTL+ Input P3 INIT# Asynch GTL+ Input P4 VSS Power/Other P5 RESERVED P6 A4# Source Synch Input/Output P7 VSS Power/Other

P8 VCC Power/Other P23 VSS Power/Other P24 VSS Power/Other P25 VSS Power/Other P26 VSS Power/Other P27 VSS Power/Other P28 VSS Power/Other P29 VSS Power/Other P30 VSS Power/Other

R1 COMP3 Power/Other Input

R2 VSS Power/Other

R3 FERR#/PBE# Asynch GTL+ Output

R4 A8# Source Synch Input/Output

R5 VSS Power/Other

R6 ADSTB0# Source Synch Input/Output

R7 VSS Power/Other

R8 VCC Power/Other R23 VSS Power/Other R24 VSS Power/Other R25 VSS Power/Other R26 VSS Power/Other R27 VSS Power/Other R28 VSS Power/Other R29 VSS Power/Other R30 VSS Power/Other

T1 COMP1 Power/Other Input

T2 FC4 Power/Other Input

T3 VSS Power/Other

T4 A11# Source Synch Input/Output

T5 A9# Source Synch Input/Output

T6 VSS Power/Other

T7 VSS Power/Other

T8 VCC Power/Other

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

T23 VCC Power/Other T24 VCC Power/Other T25 VCC Power/Other T26 VCC Power/Other T27 VCC Power/Other T28 VCC Power/Other T29 VCC Power/Other T30 VCC Power/Other

U1 VSS Power/Other U2 AP0# Common Clock Input/Output U3 AP1# Common Clock Input/Output U4 A13# Source Synch Input/Output U5 A12# Source Synch Input/Output U6 A10# Source Synch Input/Output U7 VSS Power/Other

U8 VCC Power/Other U23 VCC Power/Other U24 VCC Power/Other U25 VCC Power/Other U26 VCC Power/Other U27 VCC Power/Other U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other

V1 MSID1 Power/Other Input V2 LL_ID0 Power/Other Output V3 VSS Power/Other V4 A15# Source Synch Input/Output V5 A14# Source Synch Input/Output V6 VSS Power/Other V7 VSS Power/Other

V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS Power/Other V26 VSS Power/Other V27 VSS Power/Other V28 VSS Power/Other V29 VSS Power/Other V30 VSS Power/Other

W1 MSID0 Power/Other Input

Land Name

Signal Buffer

Type

Direction

60 Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

W2 TESTHI12 Power/Other Input W3 TESTHI1 Power/Other Input W4 VSS Power/Other W5 A16# Source Synch Input/Output W6 A18# Source Synch Input/Output W7 VSS Power/Other

W8 VCC Power/Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Other

Y1 BOOTSELECT Power/Other Input Y2 VSS Power/Other Y3 FC17 Power/Other Input Y4 A20# Source Synch Input/Output Y5 VSS Power/Other Y6 A19# Source Synch Input/Output Y7 VSS Power/Other

Y8 VCC Power/Other Y23 VCC Power/Other Y24 VCC Power/Other Y25 VCC Power/Other Y26 VCC Power/Other Y27 VCC Power/Other Y28 VCC Power/Other Y29 VCC Power/Other Y30 VCC Power/Other

AA1 VTT_OUT_RIGHT Power/Other Output AA2 LL_ID1 Power/Other Output AA3 VSS Power/Other AA4 A21# Source Synch Input/Output AA5 A23# Source Synch Input/Output AA6 VSS Power/Other AA7 VSS Power/Other

AA8 VCC Power/Other AA23 VSS Power/Other AA24 VSS Power/Other

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

AA25 VSS Power/Other AA26 VSS Power/Other AA27 VSS Power/Other AA28 VSS Power/Other AA29 VSS Power/Other AA30 VSS Power/Other

AB1 VSS Power/Other AB2 IERR# Asynch GTL+ Output AB3 MCERR# Common Clock Input/Output AB4 A26# Source Synch Input/Output AB5 A24# Source Synch Input/Output AB6 A17# Source Synch Input/Output AB7 VSS Power/Other

AB8 VCC Power/Other AB23 VSS Power/Other AB24 VSS Power/Other AB25 VSS Power/Other AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power/Other

AC1 TMS TAP Input

AC2 DBR# Power/Other Output

AC3 VSS Power/Other

AC4 RESERVED

AC5 A25# Source Synch Input/Output

AC6 VSS Power/Other

AC7 VSS Power/Other

AC8 VCC Power/Other

AC23 VCC Power/Other AC24 VCC Power/Other AC25 VCC Power/Other AC26 VCC Power/Other AC27 VCC Power/Other AC28 VCC Power/Other AC29 VCC Power/Other AC30 VCC Power/Other

AD1 TDI TAP Input

AD2 BPM2# Common Clock Input/Output

AD3 BINIT# Common Clock Input/Output

Land Name

Signal Buffer

Type

Direction

Datasheet 61

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

AD4 VSS Power/Other AD5 ADSTB1# Source Synch Input/Output AD6 A22# Source Synch Input/Output AD7 VSS Power/Other

AD8 VCC Power/Other AD23 VCC Power/Other AD24 VCC Power/Other AD25 VCC Power/Other AD26 VCC Power/Other AD27 VCC Power/Other AD28 VCC Power/Other AD29 VCC Power/Other AD30 VCC Power/Other

AE1 TCK TAP Input

AE2 VSS Power/Other

AE3 FC18 Power/Other Input

AE4 RESERVED

AE5 VSS Power/Other

AE6 RESERVED

AE7 VSS Power/Other

AE8 SKTOCC# Power/Other Output

AE9 VCC Power/Other AE10 VSS Power/Other AE11 VCC Power/Other AE12 VCC Power/Other AE13 VSS Power/Other AE14 VCC Power/Other AE15 VCC Power/Other AE16 VSS Power/Other AE17 VSS Power/Other AE18 VCC Power/Other AE19 VCC Power/Other AE20 VSS Power/Other AE21 VCC Power/Other AE22 VCC Power/Other AE23 VCC Power/Other AE24 VSS Power/Other AE25 VSS Power/Other AE26 VSS Power/Other AE27 VSS Power/Other AE28 VSS Power/Other

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

AE29 VSS Power/Other AE30 VSS Power/Other

AF1 TDO TAP Output AF2 BPM4# Common Clock Input/Output AF3 VSS Power/Other AF4 A28# Source Synch Input/Output AF5 A27# Source Synch Input/Output AF6 VSS Power/Other AF7 VSS Power/Other AF8 VCC Power/Other

AF9 VCC Power/Other AF10 VSS Power/Other AF11 VCC Power/Other AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power/Other AF15 VCC Power/Other AF16 VSS Power/Other AF17 VSS Power/Other AF18 VCC Power/Other AF19 VCC Power/Other AF20 VSS Power/Other AF21 VCC Power/Other AF22 VCC Power/Other AF23 VSS Power/Other AF24 VSS Power/Other AF25 VSS Power/Other AF26 VSS Power/Other AF27 VSS Power/Other AF28 VSS Power/Other AF29 VSS Power/Other AF30 VSS Power/Other

AG1 TRST# TAP Input AG2 BPM3# Common Clock Input/Output AG3 BPM5# Common Clock Input/Output AG4 A30# Source Synch Input/Output AG5 A31# Source Synch Input/Output AG6 A29# Source Synch Input/Output AG7 VSS Power/Other AG8 VCC Power/Other AG9 VCC Power/Other

Land Name

Signal Buffer

Type

Direction

62 Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

AG10 VSS Power/Other

AG11 VCC Power/Other AG12 VCC Power/Other AG13 VSS Power/Other AG14 VCC Power/Other AG15 VCC Power/Other AG16 VSS Power/Other AG17 VSS Power/Other AG18 VCC Power/Other AG19 VCC Power/Other AG20 VSS Power/Other AG21 VCC Power/Other AG22 VCC Power/Other AG23 VSS Power/Other AG24 VSS Power/Other AG25 VCC Power/Other AG26 VCC Power/Other AG27 VCC Power/Other AG28 VCC Power/Other AG29 VCC Power/Other AG30 VCC Power/Other

AH1 VSS Power/Other AH2 RESERVED AH3 VSS Power/Other AH4 A32# Source Synch Input/Output AH5 A33# Source Synch Input/Output AH6 VSS Power/Other AH7 VSS Power/Other AH8 VCC Power/Other AH9 VCC Power/Other

AH10 VSS Power/Other

AH11 VCC Power/Other AH12 VCC Power/Other AH13 VSS Power/Other AH14 VCC Power/Other AH15 VCC Power/Other AH16 VSS Power/Other AH17 VSS Power/Other AH18 VCC Power/Other AH19 VCC Power/Other AH20 VSS Power/Other

Land Name

Signal Buffer

Type

Direction

Table 4-2. Numerical Land Assignment

Land

AH21 VCC Power/Other AH22 VCC Power/Other AH23 VSS Power/Other AH24 VSS Power/Other AH25 VCC Power/Other AH26 VCC Power/Other AH27 VCC Power/Other AH28 VCC Power/Other AH29 VCC Power/Other AH30 VCC Power/Other

AJ1 BPM1# Common Clock Input/Output AJ2 BPM0# Common Clock Input/Output AJ3 ITP_CLK1 TAP Input AJ4 VSS Power/Other AJ5 A34# Source Synch Input/Output AJ6 A35# Source Synch Input/Output AJ7 VSS Power/Other AJ8 VCC Power/Other AJ9 VCC Power/Other

AJ10 VSS Power/Other

AJ11 VCC Power/Other AJ12 VCC Power/Other AJ13 VSS Power/Other AJ14 VCC Power/Other AJ15 VCC Power/Other AJ16 VSS Power/Other AJ17 VSS Power/Other AJ18 VCC Power/Other AJ19 VCC Power/Other AJ20 VSS Power/Other AJ21 VCC Power/Other AJ22 VCC Power/Other AJ23 VSS Power/Other AJ24 VSS Power/Other AJ25 VCC Power/Other AJ26 VCC Power/Other AJ27 VSS Power/Other AJ28 VSS Power/Other AJ29 VSS Power/Other AJ30 VSS Power/Other

AK1 THERMDC Power/Other

Land Name

Signal Buffer

Type

Direction

Datasheet 63

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

AK2 VSS Power/Other AK3 ITP_CLK0 TAP Input AK4 VID4 Power/Other Output AK5 VSS Power/Other AK6 FORCEPR# Asynch GTL+ Input AK7 VSS Power/Other AK8 VCC Power/Other

AK9 VCC Power/Other AK10 VSS Power/Other AK11 VCC Power/Other AK12 VCC Power/Other AK13 VSS Power/Other AK14 VCC Power/Other AK15 VCC Power/Other AK16 VSS Power/Other AK17 VSS Power/Other AK18 VCC Power/Other AK19 VCC Power/Other AK20 VSS Power/Other AK21 VCC Power/Other AK22 VCC Power/Other AK23 VSS Power/Other AK24 VSS Power/Other AK25 VCC Power/Other AK26 VCC Power/Other AK27 VSS Power/Other AK28 VSS Power/Other AK29 VSS Power/Other AK30 VSS Power/Other

AL1 THERMDA Power/Other

AL2 PROCHOT# Asynch GTL+

AL3 VSS Power/Other

AL4 VID5 Power/Other Output

AL5 VID1 Power/Other Output

AL6 VID3 Power/Other Output

AL7 VSS Power/Other

AL8 VCC Power/Other

AL9 VCC Power/Other AL10 VSS Power/Other AL11 VCC Power/Other AL12 VCC Power/Other

Land Name

Signal Buffer

Type

Direction

Output or

Input/Output

Table 4-2. Numerical Land Assignment

Land

AL13 VSS Power/Other AL14 VCC Power/Other AL15 VCC Power/Other AL16 VSS Power/Other AL17 VSS Power/Other AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power/Other AL23 VSS Power/Other AL24 VSS Power/Other AL25 VCC Power/Other AL26 VCC Power/Other AL27 VSS Power/Other AL28 VSS Power/Other AL29 VCC Power/Other AL30 VCC Power/Other

AM1 VSS Power/Other AM2 VID0 Power/Other Output AM3 VID2 Power/Other Output AM4 VSS Power/Other AM5 FC11 Power/Other Output AM6 VTTPWRGD Power/Other Input AM7 FC12 Power/Other Output AM8 VCC Power/Other

AM9 VCC Power/Other AM10 VSS Power/Other AM11 VCC Power/Other AM12 VCC Power/Other AM13 VSS Power/Other AM14 VCC Power/Other AM15 VCC Power/Other AM16 VSS Power/Other AM17 VSS Power/Other AM18 VCC Power/Other AM19 VCC Power/Other AM20 VSS Power/Other AM21 VCC Power/Other AM22 VCC Power/Other AM23 VSS Power/Other

Land Name

Signal Buffer

Type

Direction

64 Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

AM24 VSS Power/Other AM25 VCC Power/Other AM26 VCC Power/Other AM27 VSS Power/Other AM28 VSS Power/Other AM29 VCC Power/Other AM30 VCC Power/Other

AN1 VSS Power/Other AN2 VSS Power/Other AN3 VCC_SENSE Power/Other Output AN4 VSS_SENSE Power/Other Output

AN5

AN6

AN7 FC16 Power/Other Output AN8 VCC Power/Other AN9 VCC Power/Other

AN10 VSS Power/Other

AN11 VCC Power/Other

Land Name

VCC_MB_

REGULATION

VSS_MB_

REGULATION

Signal Buffer

Type

Power/Other Output

Direction

Table 4-2. Numerical Land Assignment

Land

AN12 VCC Power/Other AN13 VSS Power/Other AN14 VCC Power/Other AN15 VCC Power/Other AN16 VSS Power/Other AN17 VSS Power/Other AN18 VCC Power/Other AN19 VCC Power/Other AN20 VSS Power/Other AN21 VCC Power/Other AN22 VCC Power/Other AN23 VSS Power/Other AN24 VSS Power/Other AN25 VCC Power/Other AN26 VCC Power/Other AN27 VSS Power/Other AN28 VSS Power/Other AN29 VCC Power/Other AN30 VCC Power/Other

Land Name

Signal Buffer

Type

Direction

Datasheet 65

Land Listing and Signal Descriptions

4.2 Alphabetical Signals Reference

Table 4-3. Signal Description (Sheet 1 of 8)

Name Type Description

-byte physical memory address space. In sub-

A[35:3]#

A20M# Input

ADS#

Input/

Output

Input/

Output

A[35:3]# (Address) define a 2 phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for more details.

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.

ADSTB[1:0]#

AP[1:0]#

BCLK[1:0] Input

Input/

Output

Input/

Output

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB0#

A[35:17]# ADSTB1#

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins/lands of all processor FSB agents. The following table defines the coverage model of these signals.

Request Signals Subphase 1 Subphase 2

A[35:24]# AP0# AP1#

A[23:3]# AP1# AP0#

REQ[4:0]# AP1# AP0#

The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V

CROSS

66 Datasheet

Table 4-3. Signal Description (Sheet 2 of 8)

Name Type Description

BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins/lands of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration, and BINIT# is

BINIT#

BNR#

BOOTSELECT Input

BPM[5:0]#

BPRI# Input

BR0#

BSEL[2:0] Output

COMP[1:0] A nalog

COMP[3:2] A nalog

Input/

Output

Input/

Output

Input/

Output

Input/

Output

sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the FSB and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

This input is required to determine whether the processor is installed in a platform that supports the Pentium D processor. The processor will not operate if this signal is low. This input has a weak internal pull-up to V

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor.

These signals do not have on-die termination. Refer to Section 2.4 for termination requirements.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#.

BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0.

This signal does not have on-die termination and must be terminated. The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the

processor input clock frequency. Table 2-18 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to

Section 2.7.2.

COMP[1:0] must be terminated to V resistors.

COMP[3:2] must be terminated to V resistors.

Land Listing and Signal Descriptions

on the system board using precision

Datasheet 67

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 3 of 8)

Name Type Description

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#.

Quad-Pumped Signal Groups

D[63:0]#

DBI[3:0]#

DBR# Output

DBSY#

DEFER# Input

DP[3:0]#

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Data Group

D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3

Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment To Data Bus

Bus Signal Data Bus Signals

DBI3# D[63:48]# DBI2# D[47:32]# DBI1# D[31:16]# DBI0# D[15:0]#

DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents.

DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.

DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins/lands of all processor FSB agents.

DSTBN#/

DSTBP#

DBI#

68 Datasheet

Table 4-3. Signal Description (Sheet 4 of 8)

Name Type Description

DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents.

DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3#

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DBI0# DSTBP0# D[31:16]#, DBI1# DSTBP1# D[47:32]#, DBI2# DSTBP2# D[63:48]#, DBI3# DSTBP3#

DRDY#

DSTBN[3:0]#

DSTBP[3:0]#

Input/

Output

Input/

Output

Input/

Output

Land Listing and Signal Descriptions

FCx Other FC signals are signals that are available for compatibility with other processors.

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-

FERR#/PBE# Output

FORCEPR# Input

GTLREF[1:0] Input

GTLREF_SEL Output GTLREF_SEL is used to select the appropriate chipset GTLREF voltage.

HIT#

HITM#

Input/

Output

Input/

Output

type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software

Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note.

The FORCEPR# input can be used by the platform to force the processor (both cores) to activate the Thermal Control Circuit (TCC). The TCC will remain active until the system de-asserts FORCEPR#.

GTLREF[1:0] determine the signal reference level for GTL+ input signals. GTLREF[1:0] are used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

Datasheet 69

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 5 of 8)

Name Type Description

IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an

IERR# Output

IGNNE# Input

IMPSEL Input

INIT# Input

ITP_CLK[1:0] Input

LINT[1:0] Input

LL_ID[1:0] Output

LOCK#

Input/

Output

external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.

This signal does not have on-die termination. Refer to Section 2.4 for termination requirements.

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output write bus transaction.

IMPSEL input will determine whether the processor uses a 50 Ω or 60Ω buffer. This pin must be tied to GND on 50 Ω platforms and left as NC on 60 Ω platforms.

INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents.

If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST).

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.

Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these signals as LINT[1:0] is the default configuration.

The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.

LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# de-asserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock.

70 Datasheet

Table 4-3. Signal Description (Sheet 6 of 8)

Name Type Description

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents.

MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options:

MCERR#

MSID[1:0] Input

PROCHOT#

PWRGOOD Input

REQ[4:0]#

RESET# Input

RS[2:0]# Input

Input/

Output

Input/

Output

Input/

Output

• Enabled or disabled.

• Asserted, if configured, for internal errors along with IERR#.

• Asserted, if configured, by the request initiator of a bus transaction after it observes an error.

• Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32 Software Developer’s Manual, Volume 3: System Programming Guide.

MSID0 is used to indicate to the processor whether the platform supports processors with the Platform Requirement Bit (PRB) set. A processor with PRB = 1 will only boot if its MSID0 pin is electrically low. A processor with PRB = 0 will ignore this input.

MSID1 is ignored by the processor. For the Pentium D processor PROCHOT# can be configured via BIOS as an

output or a bi-directional signal. As an output, PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled.

As a bi-directional signal, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#. See Section 5.2.3 for more details.

PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD.

The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity checking of these signals.

Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after V

and BCLK have reached their proper specifications. On observing active

RESET#, all FSB agents will de-assert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1.

This signal does not have on-die termination and must be terminated on the system board.

RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents.

Land Listing and Signal Descriptions

Datasheet 71

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 7 of 8)

Name Type Description

RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the

RSP# Input

SKTOCC# Output

SMI# Input

STPCLK# Input

TCK Input

TDI Input

TDO Output

TESTHI[13:0] Input

THERMDA Other Thermal Diode Anode. See Section 5.2.7. THERMDC Other Thermal Diode Cathode. See Section 5.2.7.

THERMTRIP# Output

appropriate pins/lands of all processor FSB agents. A correct parity signal is high if an even number of covered signals are low and

low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent ensuring correct parity.

SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enters System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the processor will tristate its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is de-asserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port).

TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.

TESTHI[13:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See Section 2.4 for more details.

In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum T processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (V

Driving of the THERMTRIP# signal is enabled within 10 us of the assertion of PWRGOOD (provided VTTPWRGD, VTT, and VCC are asserted) and is disabled on de-assertion of PWRGOOD (if VTTPWRGD, VTT, or VCC are not valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, VTTPWRGD, VTT or VCC is de-asserted. While the de-assertion of the PWRGOOD, VTTPWRGD, VTT or VCC signal will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 us of the assertion of PWRGOOD (provided VTTPWRGD, VTT, and VCC are asserted).THERMTRIP# should not be sampled until 10 us after PWRGOOD assertion.

. Assertion of THERMTRIP# (Thermal Trip) indicates the

) must be removed following the assertion of THERMTRIP#.

72 Datasheet

Table 4-3. Signal Description (Sheet 8 of 8)

Name Type Description

TMS Input

TRDY# Input

TRST# Input

VCC Input VCCA Input VCCA provides isolated power for the internal processor core PLLs.

VCCIOPLL Input VCCIOPLL VCCPLL Input VCCPLL is available for compatibility with future processors.

VCC_SENSE Output

VCC_MB_ REGULATION

Output

VID[5:0] Output

VSS Input VSSA Input VSSA is the isolated ground for internal PLLs. VSS_SENSE Output

VSS_MB_ REGULATION

Output

VTT Miscellaneous voltage supply. VTT_OUT_LEFT

VTT_OUT_RIGHT

Output

VTT_SEL Output

VTTPWRGD Input

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents.

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Refer to the eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms for complete implementation details.

VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[5:0] pins.

VCC_SENSE is an isolated low impedance connection to processor core power (V

). It can be used to sense or measure voltage near the silicon with little

noise. This land is provided as a voltage regulator feedback sense point for V

connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775.

VID[5:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (V processor and must be pulled up on the motherboard. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more information.

The voltage supply for these signals must be valid before the VR can supply V

to the processor. Conversely, the VR output must be disabled until the

voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table2-1 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable itself.

VSS are the ground lands for the processor and should be connected to the system ground plane.

VSS_SENSE is an isolated low impedance connection to processor core V can be used to sense or measure ground near the silicon with little noise.

This land is provided as a voltage regulator feedback sense point for V connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775.

The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to V motherboard.

The VTT_SEL signal is used to select the correct V processor.

The processor requires this input to determine that the V and within specification.

Land Listing and Signal Descriptions

provides isolated power for internal processor FSB PLLs.

). These are open drain signals that are driven by the

on the

voltage level for the

voltages are stable

. It is

. It

Datasheet 73

Land Listing and Signal Descriptions

74 Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

5.1 Processor Thermal Specifications

The Intel® Pentium® D processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attemp t to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation.

A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal soluti ons may con sis t of system fans combined with ducting and venting.

For more information on designing a component level thermal solution, refer to the Intel

Pentium Mechanical Design Guidelines.

Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on

the boxed processor.

D Processor and Intel® Pentium® Processor Extreme Edition 840 Thermal and

5.1.1 Thermal Specifications

T o allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T Thermal Design Power (TDP) value listed per frequency in Table 5-1. Thermal solut ions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate processor thermal design guidelines.

The Pentium D processor has a methodology for managing processor temperatures that is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed will be based on the temperature reported by the processor’s Thermal Diode. If the diode temperature is greater than or equal to T at or below the temperature as specified by the thermal profile. If the diode temperature is less than T

CONTROL

temperature must remain at or below T be designed to take these conditions into account. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications.

, then the case temperature is permitted to exceed the thermal profile, but the diode

CONTROL

) specifications when operating at or below the

, then the processor case temperature must remain

. Systems that implement fan speed control must

To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions.

Datasheet 75

Thermal Specifications and Design Considerations

Refer to the Intel® Pentium® D Processor and Intel® Pentium® Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines and the Processor Power Characterization Methodology for the details of this methodology.

The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption. The Thermal Monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.2. In all cases, the Thermal Monitor feature

must be enabled for the processor to remain within specification.

Table 5-1. Processor Thermal Specifications

Processor

Number

805 2.66 GHz (PRB = 0) 95 5 See Table 5-3 and Figure 5-2 820 2.80 GHz (PRB = 0) 95 5 See Table 5-3 and Figure 5-2 830 3 GHz (PRB = 1) 130 5 See Table 5-2 and Figure 5-1 840 3.20 GHz (PRB = 1) 130 5 See Table 5-2 and Figure 5-1

NOTES:

1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate.

2. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the maximum T for the allowed combinations of power and T

Core Frequency

(GHz)

will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table

Thermal Design

Power (W)

Minimum

(°C)

Maximum T

(°C) Notes

1, 2 1, 2 1, 2 1, 2

76 Datasheet

Thermal Specifications and Design Considerations

Table 5-2. Thermal Profile for the Pentium D Processor with PRB=1

Power

(W)

0 2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32

Maximum TC

(°C)

43.8

44.2

44.6

45.0

45.4

45.8

46.2

46.6

47.0

47.4

47.8

48.2

48.6

49.0

49.4

49.8

50.2

Power

(W)

34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

Maximum TC

(°C)

50.6

51.0

51.4

51.8

52.2

52.6

53.0

53.4

53.8

54.2

54.6

55.0

55.4

55.8

56.2

56.6

57.0

Power

(W)

68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98

100

Maximum TC

(°C)

57.4

57.8

58.2

58.6

59.0

59.4

59.8

60.2

60.6

61.0

61.4

61.8

62.2

62.6

63.0

63.4

63.8

Figure 5-1. Thermal Profile for the Pentium D Processor with PRB=1

Power

(W)

102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

Maximum TC

(°C)

64.2

64.6

65.0

65.4

65.8

66.2

66.6

67.0

67.4

67.8

68.2

68.6

69.0

69.4

69.8

75.0

70.0

65.0

60.0

Tcase (C)

55.0

50.0

45.0

40.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Power (W)

y = 0.20x + 43.8

Datasheet 77

Thermal Specifications and Design Considerations

Table 5-3. Thermal Profile for the Pentium D Processor with PRB=0

Power

(W)

0 2 4 6

8 10 12 14 16 18 20 22 24

Maximum TC

(°C)

43.2

43.6

44.1

44.5

45.0

45.4

45.8

46.3

46.7

47.2

47.6

48.0

48.5

Power

(W)

26 28 30 32 34 36 38 40 42 44 46 48 50

Maximum TC

(°C)

48.9

49.4

49.8

50.2

50.7

51.1

51.6

52.0

52.4

52.9

53.3

53.8

54.2

Power

(W)

52 54 56 58 60 62 64 66 68 70 72 74 76

Maximum TC

(°C)

54.6

55.1

55.5

56.0

56.4

56.8

57.3

57.7

58.2

58.6

59.0

59.5

59.9

Figure 5-2. Thermal Profile for the Pentium D Processor with PRB=0

70.0

65.0

Power

(W)

78 80 82 84 86 88 90 92 94 95

Maximum TC

(°C)

60.4

60.8

61.2

61.7

62.1

62.6

63.0

63.4

63.9

64.1

60.0

55.0

Tcase (C)

50.0

45.0

40.0 0 102030405060708090

Power (W)

y = 0.22x + 43.2

78 Datasheet

5.1.2 Thermal Metrology

The maximum and minimum case temperatures (TC) are specified in Table 5-1. These temperature specifications are meant to help ensure proper operation of the processor. Figure 5-3 illustrates where Intel recommends T temperature measurement methodology, refer to the Intel

Pentium

Processor Extreme Edition 840 Thermal and Mechanica l Design Guidelines.

thermal measurements should be made. For detailed guidelines on

Thermal Specifications and Design Considerations

Pentium® D Processor and Intel®

Figure 5-3. Case Temperature (T

37.5 mm

) Measurement Location

37.5 mm

5.2 Processor Thermal Features

5.2.1 Thermal Monitor

Meas ure TCat this point

(geometric center of the package)

The Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than

3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.

Datasheet 79

Thermal Specifications and Design Considerations

With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel

and Intel

Pentium® Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines

for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and

cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.

5.2.2 On-Demand Mode

The Pentium D processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as "On-Demand" mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the Pentium D processor must not rely on software usage of this mechanism to limit the processor temperature.

that exceeds the

Pentium® D Processor

If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor . If the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.

5.2.3 PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture Software Developer's Manuals for specific register and programming details.

For the Pentium D processor, PROCHOT# can be configured via BIOS as an output or a bidirectional signal. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#.

If PROCHOT# is configured as an output only, the FORCEPR# signal can be driven from an external source to activate the TCC. This will prevent one core from asserting the PROCHOT# signal of the other core and unnecessarily activating the TCC of that core. Refer to Section 5.2.4 for details on the FORCEPR# signal.

80 Datasheet

As a bi-directional signal, PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components.

Bi-directional PROCHOT# (if enabled) can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for details on implementing the bi-directional PROCHOT# feature. Contact your Intel representative for further details and documentation.

5.2.4 FORCEPR# Signal Pin

The FORCEPR# (force power reduction) input can be used by the platform to cause the processor (both cores) to activate the TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal. The TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an asynchronous input.

Thermal Specifications and Design Considerations

FORCEPR# can be used to thermally protect other system components. To use the VR as an example, when the FORCEPR# pin is asserted, the TCC circuit in the processor (both cores) will activate, reducing the current consumption of the processor and the corresponding temperature of the VR.

It should be noted that assertion of the FORCEPR# does not automatically assert PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high temperature situation is detected. A minimum pulse width of 500 µs is recommend when the FORCEPR# is asserted by the system. Sustained activation of the FORCEPR# pin may cause noticeable platform performance degradation.

One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting FORCEPR# (pulled-low) and activating the TCC, the VR can cool down as a result of reduced processor power consumption. FORCEPR# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on FORCEPR# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that FORCEPR# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of FORCEPR# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for details on implementing the FORCEPR# feature. Contact your Intel representative for further details and documentation.

Datasheet 81

Thermal Specifications and Design Considerations

5.2.5 THERMTRIP# Signal

Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 4-3). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 4-3. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.

5.2.6 T

T The value for T When T profile in Table 5-2 T

CONTROL

DIODE

CONTROL

and Fan Speed Reduction

is a temperature specification based on a temperature reading from the thermal diode.

CONTROL

is above T

and Figure 5-1; otherwise, the processor temperature can be maintained at

(or lower) as measured by the thermal diode.

The purpose of this feature is to support acoustic optimization through fan speed control.

5.2.7 Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 5-4 and Table 5-5 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.

Table 5-4. Thermal Diode Parameters

Symbol Parameter Min Typ Max Unit Notes

Forward Bias Current 11 187 µA

n Diode Ideality Factor 1.0083 1.011 1.023

Series Resistance 3.242 3.33 3.594 Ω

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized at 75 °C.

3. Not 100% tested. Specified by design characterization.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the di ode equation:

= saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann

where I

Constant, and T = absolute temperature (Kelvin).

5. Devices found to have an ideality factor of 1.0183 to 1.023 will create a temperature error approximately 2 °C higher than the actual temperature. To minimize any potentia l acoust ic imp act of thi s temper atu re err or, T by 2 °C on these parts.

6. The series resistance, RT, is provided to allow for a more accurate measurement of the thermal diode temperature. RT, as defined, includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation:

where T charge.

= sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic

error

will be calibrated in manufacturing and configured for each processor.

CONTROL

IFW = IS * (e

= [RT * (N-1) * I

error

, then TC must be at or below T

qVD/nkT

–1)

] / [nk/q * ln N]

FWmin

as defined by the thermal

C-MAX

will be increased

CONTROL

2, 3, 4, 5

2, 3, 6

82 Datasheet

Table 5-5. Thermal Diode Interface

Signal Name Land Number Signal Description

THERMDA AL1 diode anode THERMDC AK1 diode cathode

Thermal Specifications and Design Considerations

Datasheet 83

Thermal Specifications and Design Considerations

84 Datasheet

6 Features

6.1 Power-On Configuration Options

Several configuration options can be configured by hardware. The Intel® Pentium® D processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1.

The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

Table 6-1. Power-On Configuration Option Signals

Configuration Option Signal

Output tristate SMI# Execute BIST INIT# In Order Queue pipelining (set IOQ depth to 1) A7# Disable MCERR# observation A9# Disable BINIT# observation A10# APIC Cluster ID (0-3) A[12:11]# Disable bus parking A15# Single Logical Processor Mode Symmetric agent arbitration ID BR0# RESERVED A[6:3]#, A8#, A[14:13]#, A[16:30]#, A[32:35]#

NOTES:

1. Asserting this signal during RESET# will select the corresponding option.

2. Address signals not identified in this table as configuration options should not be asserted during RESET#.

3. This mode is not tested.

Features

1, 2

A31#

6.2 Clock Control and Low Power States

The processor allows the use of AutoHAL T and S top-Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See

Figure 6-1 for a visual representation of the processor low power states.

The Pentium D processor includes support for the Enhanced HALT powerdown state. Refer to

Figure 6-1 and the following sections.

Datasheet 85

Features

Figure 6-1. Processor Low Power State Machine

Normal State

Normal execution

STPCLK# Asserted

STPCLK# De-asserted

HALT or MWAIT Instruction and HALT Bus Cycle Generated

INIT#, BINIT#, INTR, NMI, SMI#, RESET#, FSB interrupts

Enhanced HALT or HALT State

BCLK running Snoops and interrupts allowed

Snoop

Event

Occurs

Enhanced HALT Snoop or HALT Snoop State

BCLK running Service snoops to caches

Snoop

Event

Serviced

Stop-Grant State

BCLK running Snoops and interrupts allowed

Snoop Event Occurs

Snoop Event Serviced

Grant Snoop State

BCLK running Service snoops to caches

6.2.1 Normal State

This is the normal operating state for the processor.

6.2.2 HALT and Enhanced HALT Powerdown States

The Pentium D processor supports the HAL T or Enhanced HALT powerdown state. The Enhanced HALT Powerd own state is configured and enabled via the BIOS. The Enhanced HALT state is a lower power state as compared to the Stop Grant State. If Enhanced HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the sections below for details about the HALT and Enhanced HALT states.

6.2.2.1 HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed th e HALT or MWAIT instructions. When one of the logical processors executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Devel oper's Manual, Volume III: System Programmer's Guide for more information.

86 Datasheet

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process bus snoops.

6.2.2.2 Enhanced HALT Powerdown State

Enhanced HAL T is a low power state entered when all logical processors have executed the HALT or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the logical processors executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation.

The processor will automatically transition to a lower frequency and voltage operating point before entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.

While in Enhanced HALT state, the processor will process bus snoops. The processor exits the Enhanced HAL T state when a break event occurs. When the processor exits

the Enhanced HALT state, it will first transition the VID to the original value and then change the bus ratio back to the original value.

Features

6.2.3 Stop-Grant State

When the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Since the GTL+ signals receive power from th e FSB , these signals should not be driven (allowing the level to return to V addition, all other input signals on the FSB should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4).

While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop.

) for minimum power drawn by the termination resistors in this state. In

Datasheet 87

Features

6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State

The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State.

6.2.4.1 HALT Snoop State, Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT:Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop-Grant state or HALT Power Down state, as appropriate.

6.2.4.2 Enhanced HALT Snoop State

The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of the Enhanced HALT state.

While in the Enhanced HALT Snoop State, snoops are handled the same way as in the HALT Snoop State. After the snoop is serviced the processor will return to the Enhanced HALT Power Down state.

6.2.5 Enhanced Intel SpeedStep® Technology

Enhanced Intel SpeedStep Technology enables the processor to switch between frequency and voltage points, which may result in platform power savings. To support this technology, the system must support dynamic VID transitions. Switching between voltage/frequency states is software controlled.

Note: Not all processors are capable of supporting Enhanced Intel SpeedStep Technology. More details

on which processor frequencies support this feature will be provided in future releases of the Intel

Pentium

Enhanced Intel SpeedStep Technology is a technology that creates processor performance states (P states). P states are power consumption and capability states within the Normal state as shown in

Figure 6-1. Enhanced Intel SpeedStep Technol ogy enables real-time dynamic switching between

frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. Note that the front side bus is not altered; only the internal core frequency is changed. To run at reduced power consumption, the voltage is altered in step with the bus ratio.

The following are key features of Enhanced Intel SpeedStep Technology:

Processor Extreme Edition and Intel® Pentium D Processor Specification Update.

• Voltage/Frequency selection is software controlled by writing to processor MSRs (Model

Specific Registers), thus eliminating chipset dependency.

— If the target frequency is higher than the current frequency, V

(+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded.

— If the target frequency is lower than the current frequency, the processor shifts to the new

frequency and V through the VID signals.

is then decremented in steps (-12.5 mV) by changing the target VID

is incremented in steps

88 Datasheet

Boxed Processor Specifications

7 Boxed Processor Specifications

The Intel® Pentium® D processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed Pentium D processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed Pentium D processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed Pentium D processor.

Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These

dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the Intel

Processor and Intel

Figure 7-1. Mechanical Representation of the Boxed Processor

Guidelines for further guidance. Contact your local Intel Sales Representative for this do cument.

Pentium® Processor Extreme Edition 840 Thermal and Mechanical Design

Pentium® D

NOTE: The airflow of th e fan heatsink is into the center and out of the sides of the fan heatsink.

Datasheet 89

Boxed Processor Specifications

7.1 Mechanical Specifications

7.1.1 Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed Pentium D processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium D processor.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7-2 (Side View), and Figure 7-3 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 7-7 and Figure 7-8. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.

Figure 7-2. Side View Space Requirements for the Boxed Processor (Applies to all four side

views)

3.74

[95.0]

3.2

[81.3]

0.39

[10.0]

Figure 7-3. Top View Space Requirements for the Boxed Processor

3.74

[95.0]

3.74

[95.0]

0.98

[25.0]

NOTES:

1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.

90 Datasheet

Boxed Processor Specifications

Figure 7-4. Overall View Space Requirements for the Boxed Processor

7.1.2 Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the

Intel

Pentium® D Processor and Intel® Pentium® Processor Extreme Edition 840 Thermal and

Mechanical Design Guidelines for details on the processor weight and heatsink requirements.

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the bas eboard socket. The boxed processor will ship with the heatsink attach clip assembly.

7.2 Electrical Requirements

7.2.1 Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V power supply. An attached fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 7-5. Baseboards must provide a matched power header to support the boxed processor. Table 7-1 contains specifications for the input and output signals at the fan heatsink connector.

The fan heatsink outputs a SENSE signal that is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.

Datasheet 91

to match the system board-

Boxed Processor Specifications

The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL.

The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 7-6 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket.

Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description

Signal

1 2 3 4

GND +12 V

SENSE CONTROL

Straight square pin, 4-pin t er minal housing with polarizing ri bs and fr iction locking ramp.

0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on

mainboard.

Table 7-1. Fan Heatsink Power and Signal Specifications

Description Min Typ Max Unit Notes

+12 V: 12 volt fan power supply 11.4 12 12.6 V IC:

Peak fan steady-state current draw Average fan steady-state current draw Max fan start-up current draw

Fan start-up current draw maximum duration Sense frequency — 2 — CONTROL frequency 21 25 28 kHz

NOTES:

1. Baseboard should pull this pin up to 5 V with a resistor.

2. Open drain type, pulse width modulated.

3. Fan will have pull-up resistor to 4.75 V maximum of 5.25 V.

3.0

2.0

3.0

1.0

Boxed_Proc_P wrCable

A A A

Second

pulses per fan

revolution

2, 3

92 Datasheet

Boxed Processor Specifications

Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket

7.3 Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor.

7.3.1 Boxed Processor Cooling Requirements

The boxed processor may be di rectly coo led wi th a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is found in Chapter 5 of this document. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 5-1) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 7-7 and Figure 7-8 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 39 ºC. A Thermally Advantaged Chassis with an Air Guide 1.1 is recommended to meet the 39 ºC requirement. Again, meeting the processor's temperature specification is the responsibility of the system integrator.

Note: The processor fan is the primary source of airflow for cooling the V

voltage regulator cooling components may be necessary if the selected fan is not capable of keeping regulator components below maximum rated temperatures.

voltage regulator. Dedicated

Datasheet 93

Boxed Processor Specifications

Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)

Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)

94 Datasheet

7.3.2 Variable Speed Fan

If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows:

The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point. These set points, represented in

Figure 7-9 and Table 7-2, can vary by a few degrees from fan heatsink to fan heatsink. The

internal chassis temperature should be kept below 39 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator.

The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to Table 7-1 for the specific requirements.

Figure 7-9. Boxed Processor Fan Heatsink Set Points

Boxed Processor Specifications

Increasing Fan

Speed & Noise

Lower Set Point

Lowest Noise Level

Internal Chassis Temperature (Degrees C)

Table 7-2. Fan Heatsink Power and Signal Specifications

Boxed Processor Fan

Heatsink Set Point (

X ≤ 30

Y = 35

Z ≥ 39

NOTES:

1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.

ºC)

When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment.

When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. Recommended maximum internal chassis temperature for worst-case operating environment.

When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed.

Boxed Processor Fan Speed Notes

Higher Set Point

Highest Noise Level

Datasheet 95

Boxed Processor Specifications

If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (For details on CONTROL, see Table 7-1) and remote thermal diode measurement capability the boxed processor will operate as follows:

As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.

The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by more accurate measurement of processor die temperature through the processor's temperature diode (T

). Fan RPM is modulated through the use of an ASIC located on the motherboard

DIODE

that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on the actual processor temperature instead of internal ambient chassis temperatures.

If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header, it will default back to a thermistor controlled mode. This allows compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the T

For more details on specific motherboard requirements for 4-wire based fan speed control, see the

Intel

Pentium® D Processor and Intel® Pentium® Processor Extr eme Edition 840 Thermal and

temperature measured by a thermistor located at the fan inlet.

inlet

Mechanical Design Guidelines.

96 Datasheet

Balanced Technology Extended (BTX) Type I Boxed Processor Specifica tions

8 Balanced Technology Extended

(BTX) Type I Boxed Processor Specifications

The Intel® Pentium® D processor will also be offered as an boxed Intel processor. Boxed Intel processors are intended for system integrators who build systems from largely standard components. The boxed Intel Pentium D processor will be supplied with a cooling solution known as the Thermal Module Assembly (TMA). Figure 8-1 shows a mechanical representation of a boxed Pentium D processor. This chapter documents mainboard and system requirements for the TMA that will be supplied with the boxed Pentium D processor. This chapter is particularly important for OEMs that manufacture mainboards for system integrators.

Note: Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches

[in brackets].

Note: Drawings in this section reflect only the specifications on the boxed Intel processor product. These

dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designer’s responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the Intel

Processor and Intel Guidelines for further guidance.

Figure 8-1. Mechanical Representation of the Boxed Processor

Pentium® Processor Extreme Edition 840 Thermal and Mechanical Design

Pentium® D

NOTE: The duct, clip, heatsink, and fan can differ from this drawing representation; however, the basic shape

and size will remain the same.

Datasheet 97

Balanced Technology Extended (BTX) Type I Boxed Processor Specifications

8.1 Mechanical Specifications

8.1.1 Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed Pentium D processor TMA. The boxed processor will be shipped with an unattached TMA. Figure 8-2 shows a mechanical representation of the boxed Pentium D processor TMA. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown.

Figure 8-2. Requirements for the Balance d Technology Extended (BTX) Type I Keep-out

Volumes

NOTE: The diagram does not show the attached hardware for the clip design and is provided only as a

mechanical representation.

8.1.2 Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 1290 grams. See Chapter 3 and the

Intel

Pentium® D Processor and Intel® Pentium® Processor Extr eme Edition 840 Thermal and

Mechanical Design Guidelines for details on the processor weight and heatsink requirements.

98 Datasheet

Balanced Technology Extended (BTX) Type I Boxed Processor Specifica tions

8.1.3 Boxed Processor Support and Retention Module (SRM)

The boxed processor TMA requires a SRM assembly to attach directly to the chassis base pan and to secure the processor and TMA in the mainboard socket. The boxed processor TMA will ship with the heatsink attach clip assembly, duct, and screws for attachment. The SRM must be supplied by the chassis hardware vendor. See the Support and Retention Module (SRM) External Design

Requirements Document, Balanced Technology Extended (BTX) System Design Guide, and the

Intel

Pentium® D Processor and Intel® Pentium® Processor Extreme Edition 840 Thermal and

Mechanical Design Guidelines for more detailed design information regarding the support and

retention module.

Figure 8-3. Assembly Stack Including the Support and Retention Module

Thermal Module Assembly

•Heatsink & Fan

• Clip

• Stru c tura l D u c t

Motherboard

SRM

Chassis Pan

8.2 Electrical Requirements

8.2.1 Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 8-4. Baseboards must provide a matched power header to support the boxed processor. Table 8-1 contains specifications for the input and output signals at the fan heatsink connector.

The fan heatsink outputs a SENSE signal that is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V

to match the system board-

mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.

Datasheet 99

Balanced Technology Extended (BTX) Type I Boxed Processor Specifications

The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL.

Note: The boxed processor’s fan heatsink requires a constant +12 V supplied to pin 2 and does not

support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 8-5 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 4.33 inches from the center of the processor socket.

Figure 8-4. Boxed Processor Fan Heatsink Power Cable Connector

Signal

1 2

GND +12 V

SENSE CONTROL

Straight square pin, 4- pin terminal housing with polarizi ng r ibs and fric tion locking ramp.

0.100" pitch, 0.025" square pin width. Match with straight pin, fr iction l ock header on

mainboard.

Table 8-1. Fan Heatsink Power and Signal Specifications

Description Min Typ Max Unit Notes

+12 V: 12 volt fan power supply 10.2 12 13.8 V IC:

Peak Fan current draw Fan start-up current draw

Fan start-up current draw maximum duration SENSE: SENSE frequency — 2 — CONTROL 21 25 28 kHz 2,3

NOTES:

1. Baseboard should pull this pin up to 5 V with a resistor.

2. Open Drain Type, Pulse Width Modulated.

3. Fan will have a pull-up resistor to 4.75 V, maximum 5.25 V.

— — —

—

1.0 —

1.5

2.0

1.0

A A

Second

pulses per fan

revolution

100 Datasheet

Intel 830 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Terminology

1.1.1 Processor Packaging Terminology

1.2 References

2 Electrical Specifications

2.1 Power and Ground Lands

2.2 Decoupling Guidelines

2.2.1 VCC Decoupling

2.2.2 VTT Decoupling

2.2.3 FSB Decoupling

2.3 Voltage Identification

2.4 Reserved, Unused, FC and TESTHI Signals

2.5 Voltage and Current Specifications

2.5.1 Absolute Maximum and Minimum Ratings

2.5.2 DC Voltage and Current Specifications

2.5.3 VCC Overshoot Specification

2.5.4 Die Voltage Validation

2.6 Signaling Specifications

2.6.1 FSB Signal Groups

2.6.2 GTL+ Asynchronous Signals

2.6.3 FSB DC Specifications

2.6.3.1 GTL+ Front Side Bus Specifications

2.7 Clock Specifications

2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking

2.7.2 FSB Frequency Select Signals

2.7.3 Phase Lock Loop (PLL) and Filter

Package Mechanical Specifications

3.1 Package Mechanical Drawing

3.2 Processor Component Keep-Out Zones

3.3 Package Loading Specifications

3.4 Package Handling Guidelines

3.5 Package Insertion Specifications

3.6 Processor Mass Specification

3.7 Processor Materials

3.8 Processor Markings

3.9 Processor Land Coordinates

Land Listing and Signal Descriptions

4.1 Processor Land Assignments

4.2 Alphabetical Signals Reference

Thermal Specifications and Design Considerations

5.1 Processor Thermal Specifications

5.1.1 Thermal Specifications

5.1.2 Thermal Metrology

5.2 Processor Thermal Features

5.2.1 Thermal Monitor

5.2.2 On-Demand Mode

5.2.3 PROCHOT# Signal

5.2.4 FORCEPR# Signal Pin

5.2.5 THERMTRIP# Signal

5.2.7 Thermal Diode

6 Features

6.1 Power-On Configuration Options

6.2 Clock Control and Low Power States

6.2.1 Normal State

6.2.2 HALT and Enhanced HALT Powerdown States

6.2.2.1 HALT Powerdown State

6.2.2.2 Enhanced HALT Powerdown State

6.2.3 Stop-Grant State

6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State

6.2.4.1 HALT Snoop State, Grant Snoop State

6.2.4.2 Enhanced HALT Snoop State

6.2.5 Enhanced Intel SpeedStep® Technology

7 Boxed Processor Specifications

7.1 Mechanical Specifications

7.1.1 Boxed Processor Cooling Solution Dimensions

7.1.2 Boxed Processor Fan Heatsink Weight

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

7.2 Electrical Requirements

7.2.1 Fan Heatsink Power Supply

7.3 Thermal Specifications

7.3.1 Boxed Processor Cooling Requirements

7.3.2 Variable Speed Fan

Balanced Technology Extended (BTX) Type I Boxed Processor Specifica tions

8.1 Mechanical Specifications

8.1.1 Cooling Solution Dimensions

8.1.2 Boxed Processor Fan Heatsink Weight