Intel 82810 (GMCH0), 810-DC100 (Whitney) Intel 810 Chipset Family Programmer’s Reference Manual 298026-001 (Nov 1999)
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Intel
Programmer’s Reference Manual
November 1999
Revision 1.0
810 Chipset Family
Order Number: 298026-001
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Intel
810 Chipset Family PRM
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THIS DOCUMENT IS PROVIDED "AS IS," WITH NO WARRANTIES WHATSOEVER, INCLU DING ANY
WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE,
OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel
disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this
specification.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied
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purpose, merchantability or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, lifesaving, or life-sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or
“undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Intel
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810 family of chipsets may contain design defects or errors known as errata that may cause the product to
deviate from published specifications. Current characterized errata are available upon request.
Copyright © Intel Corporation, 1999
* Third-party brands and names are the property of their respective owners.
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Contents
1. Introduction...............................................................................................................................................1
1.1 Audience ..............................................................................................................................................1
1.2 Reference Documents .........................................................................................................................1
1.3 Intel
2. Product Features of Intel
2.1 GMCH Overview ..................................................................................................................................9
3. System Address Map .............................................................................................................................11
3.1 GC Register Memory Address Map...................................................................................................15
3.2 Graphics Address Translation............................................................................................................18
3.3 Instruction Parser...............................................................................................................................19
3.4 Ring Buffers (RB)...............................................................................................................................20
3.4.1 Ring Buffer Registers....................................................................................................................21
3.4.2 Ring Buffer Initialization ................................................................................................................22
3.4.3 Ring Buffer Use.............................................................................................................................22
3.5 Batch Buffers......................................................................................................................................23
4. Graphics Translation Table Range Definition .....................................................................................25
5. Basic Initialization Procedures .............................................................................................................27
5.1 Initialization Sequence .......................................................................................................................27
5.2 Hardware Detection (Probe) ..............................................................................................................27
5.3 Frame Buffer Initialization ..................................................................................................................29
5.4 Hardware Register Initialization .........................................................................................................29
5.4.1 Color vs. Monochrome Monitors...................................................................................................29
5.4.2 Protect Registers: Locking and Unlocking....................................................................................30
5.4.3 Checking Memory Frequency.......................................................................................................30
5.5 Hardware State ..................................................................................................................................31
5.6 Saving the Hardware State ................................................................................................................31
5.7 Restoring the Hardware State............................................................................................................32
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82810 Chipset System ...............................................................................................................2
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82810 Chipset & Intel® 82810-DC100 Chipset ..........................................5
6. BLT Engine Programming .....................................................................................................................37
6.1 BLT Engine Programming Considerations.........................................................................................37
6.1.1 When the Source and Destination Locations Overlap..................................................................37
6.2 Basic Graphics Data Considerations .................................................................................................41
6.2.1 Contiguous vs. Discontinuous Graphics Data ..............................................................................41
6.2.2 Source Data ..................................................................................................................................42
6.2.3 Monochrome Source Data............................................................................................................43
6.2.4 Pattern Data..................................................................................................................................44
6.2.5 Destination Data............................................................................................................................47
6.3 BLT Programming Examples.............................................................................................................48
6.3.1 Pattern Fill — A Very Simple BLT.................................................................................................48
6.3.2 Drawing Characters Using a Font Stored in System Memory......................................................51
7. Initialization Registers ...........................................................................................................................55
7.1 Standard VGA Registers....................................................................................................................55
7.2 SMRAM Registers..............................................................................................................................55
7.2.1 SMRAM—System Management RAM Control Register (Device 0).............................................55
7.3 Graphics Controller Registers............................................................................................................57
7.3.1 GR10Address Mapping.............................................................................................................57
7.3.2 GR11Page Selector ..................................................................................................................60
7.4 CRT Controller Register.....................................................................................................................61
7.4.1 CR30Extended Vertical Total Register .....................................................................................61
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7.4.2 CR31Extended Vertical Display End Register .......................................................................... 62
7.4.3 CR32Extended Vertical Sync Start Register.............................................................................63
7.4.4 CR33Extended Vertical Blanking Start Register.......................................................................64
7.4.5 CR35Extended Horizontal Total Time Register ........................................................................ 65
7.4.6 CR39Extended Horizontal Blank Time Register ....................................................................... 65
7.4.7 CR40Extended Start Address Register.....................................................................................66
7.4.8 CR41Extended Offset Register.................................................................................................67
7.4.9 CR42Extended Start Address High Register............................................................................67
7.4.10 CR70Interlace Control Register ..............................................................................................68
7.4.11 CR80I/O Control......................................................................................................................68
7.4.12 CR82Blink Rate Control ..........................................................................................................69
7.5 Display Control Registers...................................................................................................................70
7.5.1 FW_BLC—FIFO Watermark and Burst Length Control................................................................70
7.6 I/O Control Registers..........................................................................................................................72
7.6.1 HVSYNC—HSYNC/VSYNC Control Register ..............................................................................72
7.7 GPIO Registers..................................................................................................................................73
7.7.1 GPIOAGeneral-Purpose I/O Control Register A.......................................................................73
7.7.2 GPIOBGeneral-Purpose I/O Control Register B.......................................................................75
7.8 Clock Control Registers .....................................................................................................................77
7.8.1 Programming Notes ......................................................................................................................77
7.8.2 DCLK_0D—Display Clock 0 Divisor Register...............................................................................79
7.8.3 DCLK_1D—Display Clock 1 Divisor Register...............................................................................80
7.8.4 DCLK_2D—Display Clock 2 Divisor Register...............................................................................81
7.8.5 LCD_CLKD—LCD Clock Divisor Register....................................................................................82
7.8.6 DCLK_0DS—Display & LCD Clock Divisor Select Register.........................................................83
7.8.7 PWR_CLKC—Power Management and Miscellaneous Clock Control ........................................85
7.9 LCD / TV-Out Registers .....................................................................................................................86
7.9.1 HTOTAL—Horizontal Total Register.............................................................................................86
7.9.2 HBLANK—Hor i zontal Bl ank Register ...........................................................................................87
7.9.3 HSYNC—Horizont al S ync Register ..............................................................................................88
7.9.4 VTOTAL—Vertical Total Register.................................................................................................88
7.9.5 VBLANK— Vert ical Bl ank Register................................................................................................89
7.9.6 VSYNC—Vertical Sync Register...................................................................................................90
7.9.7 LCDTV_C—LCD/TV-Out Control Register...................................................................................91
7.9.8 OVRACT—Overlay Active Register..............................................................................................94
7.9.9 BCLRPAT— Border Color Pattern Register .................................................................................94
7.10 Pixel Pipeline Control Registers........................................................................................................95
7.10.1 PIXCONF—Pixel Pipeline Configuration ....................................................................................95
7.11 Initialization Values for VGA Registers..............................................................................................98
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8. Frame Buffer Access............................................................................................................................101
9. VGA and Extended VGA Registers.....................................................................................................103
9.1 General Control & Status Registers.................................................................................................103
9.1.1 ST00Input Status 0..................................................................................................................104
9.1.2 ST01Input Status 1..................................................................................................................105
9.1.3 FCRFeature Control................................................................................................................106
9.1.4 MSRMiscellaneous Output...................................................................................................... 107
9.2 Sequencer Registers........................................................................................................................108
9.2.1 SRXSequencer Index..............................................................................................................108
9.2.2 SR00Sequencer Reset............................................................................................................109
9.2.3 SR01Clocking Mode................................................................................................................109
9.2.4 SR02Plane/Map Mask............................................................................................................. 110
9.2.5 SR03Character Font ...............................................................................................................111
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9.2.6 SR04Memory Mode Register..................................................................................................112
9.2.7 SR07Horizontal Character Counter Reset..............................................................................113
9.3 Graphics Controller Registers..........................................................................................................113
9.3.1 GRXGRX Graphics Controller Index Register ........................................................................113
9.3.2 GR00Set/Reset Register.........................................................................................................114
9.3.3 GR01Enable Set/Reset Register............................................................................................. 114
9.3.4 GR02Color Compare Register................................................................................................115
9.3.5 GR03Data Rotate Register ..................................................................................................... 115
9.3.6 GR04Read Plane Select Register...........................................................................................116
9.3.7 GR05Graphics Mode Register................................................................................................116
9.3.8 GR06Miscellaneous Register.................................................................................................. 119
9.3.9 GR07Color Don’t Care Register..............................................................................................120
9.3.10 GR08Bit Mask Register.........................................................................................................120
9.3.11 GR10Address Mapping ......................................................................................................... 121
9.3.12 GR11Page Selector............................................................................................................... 123
9.3.13 GR[14:1F]Software Flags x...................................................................................................123
9.4 Attribute Controller Registers...........................................................................................................124
9.4.1 ARXAttribute Controller Index Register................................................................................... 124
9.4.2 AR[00:0F]Palette Registers [0:F]............................................................................................. 125
9.4.3 AR10Mode Control Register ...................................................................................................126
9.4.4 AR11Overscan Color Register................................................................................................127
9.4.5 AR12Memory Plane Enable Register .....................................................................................128
9.4.6 AR13Horizontal Pixel Pannin g Regist er..................................................................................129
9.4.7 AR14Color Select Register .....................................................................................................130
9.5 VGA Color Palette Registers ...........................................................................................................131
9.5.1 DACMASKPixel Data Mask Register......................................................................................132
9.5.2 DACSTATEDAC State Register..............................................................................................132
9.5.3 DACRXPalette Read Index Register.......................................................................................133
9.5.4 DACWXPalette Write Index Register ...................................................................................... 133
9.5.5 DACDATAPalette Data Register.............................................................................................133
9.6 CRT Controller Register...................................................................................................................134
9.6.1 CRXCRT Controller Index Register ........................................................................................135
9.6.2 CR00Horizontal Total Register................................................................................................ 135
9.6.3 CR01Horizontal Display Enable End Register........................................................................135
9.6.4 CR02Horizontal Blanking Start Register.................................................................................136
9.6.5 CR03Horizontal Blanking End Register ..................................................................................136
9.6.6 CR04Horizontal Sync Start Register....................................................................................... 137
9.6.7 CR05Horizontal Sync End Register........................................................................................137
9.6.8 CR06Vertical Total Register.................................................................................................... 138
9.6.9 CR07Overflow Register........................................................................................................... 138
9.6.10 CR08Preset Row Scan Register...........................................................................................142
9.6.11 CR09Maximum Scan Line Register ......................................................................................143
9.6.12 CR0AText Cursor Start Register ...........................................................................................144
9.6.13 CR0BText Cursor End Register ............................................................................................145
9.6.14 CR0CStart Address High Register ........................................................................................ 146
9.6.15 CR0DStart Address Low Register.........................................................................................147
9.6.16 CR0EText Cursor Location High Register.............................................................................147
9.6.17 CR0FText Cursor Location Low Register..............................................................................148
9.6.18 CR10Vertical Sync Start Register ......................................................................................... 148
9.6.19 CR11Vertical Sync End Register ..........................................................................................149
9.6.20 CR12Vertical Display Enable End Register ..........................................................................150
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9.6.21 CR13Offset Register ............................................................................................................. 150
9.6.22 CR14Underline Location Register.........................................................................................151
9.6.23 CR15Vertical Blanking Start Register ...................................................................................152
9.6.24 CR16Vertical Blanking End Register.....................................................................................152
9.6.25 CR17CRT Mode Control .......................................................................................................153
9.6.26 CR18Line Compare Register ................................................................................................156
9.6.27 CR22Memory Read Latch Data Register..............................................................................156
9.6.28 CR24 Test Register for Toggle State of Attribute Controller Register ..................................157
9.6.29 CR30Extended Vertical Total Register..................................................................................157
9.6.30 CR31Extended Vertical Display End Register ......................................................................158
9.6.31 CR32Extended Vertical Sync Start Register.........................................................................159
9.6.32 CR33Extended Vertical Blanking Start Register...................................................................160
9.6.33 CR34 Extended Vertical Blank Time Register (Reserved, Not Implemented)..........................161
9.6.34 CR35 Extended Horizontal Total Time Register ...................................................................161
9.6.35 CR39Extended Horizontal Blank Time Register ...................................................................161
9.6.36 CR40Extended Start Address Register.................................................................................161
9.6.37 CR41Extended Offset Register.............................................................................................163
9.6.38 CR42Extended Start Address High Register ........................................................................163
9.6.39 CR70Interlace Control Register ............................................................................................164
9.6.40 CR80I/O Control....................................................................................................................164
9.6.41 CR81Reserved......................................................................................................................165
9.6.42 CR82Blink Rate Control ........................................................................................................165
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10. Programming Interface.....................................................................................................................167
10.1 Reserved Bits and Software Compatibility......................................................................................167
10.2 Overview..........................................................................................................................................167
10.3 GC Register Programming..............................................................................................................168
10.4 GC Instruction Streams...................................................................................................................169
10.4.1 Instruction Use ..........................................................................................................................169
10.4.2 Instruction Transport Overview.................................................................................................169
10.4.3 Instruction Parser......................................................................................................................169
10.4.4 Ring Buffers (RB)......................................................................................................................170
10.4.5 Batch Buffers.............................................................................................................................173
10.4.6 Instruction Arbitration ................................................................................................................173
10.5 Instruction Format............................................................................................................................176
10.5.1 Instruction Parser Instructions...................................................................................................176
10.5.2 2D Instructions ..........................................................................................................................176
10.5.3 3D Instructions ..........................................................................................................................176
11. Instruction Parser Instructions........................................................................................................181
11.1 Introduction......................................................................................................................................181
11.2 Instruction Descriptions...................................................................................................................181
11.2.1 GFXCMDPARSER_NOP_IDENTIFICATION...........................................................................181
11.2.2 GFXCMDPARSER_BREAKPOINT_INTERRUPT....................................................................182
11.2.3 GFXCMDPARSER_USER_INTERRUPT.................................................................................182
11.2.4 GFXCMDPARSER_WAIT_FOR_EVENT................................................................................. 183
11.2.5 GFXCMDPARSER_FLUSH......................................................................................................184
11.2.6 GFXCMDPARSER_CONTEXT_SEL........................................................................................185
11.2.7 GFXCMDPARSER_DEST_BUFFER_INFO............................................................................. 186
11.2.8 GFXCMDPARSER_FRONT_BUFFER_INFO..........................................................................187
11.2.9 GFXCMDPARSER_Z_BUFFER_INFO ....................................................................................188
11.2.10 GFXCMDPARSER_REPORT_HEAD.....................................................................................189
11.2.11 GFXCMDPARSER_ARB_ON_OFF........................................................................................189
11.2.12 GFXCMDPARSER_OVERLAY_FLIP .....................................................................................190
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11.2.13 GFXCMDPARSER_LOAD_SCAN_LINES_INCL ...................................................................190
11.2.14 GFXCMDPARSER_LOAD_SCAN_LINES_EXCL .................................................................. 191
11.2.15 GFXCMDPARSER_STORE_DWORD_IMM ..........................................................................191
11.2.16 GFXCMDPARSER_STORE_DWORD_INDEX ......................................................................192
11.2.17 GFXCMDPARSER_BATCH_BUFFER ................................................................................... 193
12. 2D Instructions ..................................................................................................................................195
12.1 Introduction......................................................................................................................................195
12.2 BLTs to and from Cacheable Memory.............................................................................................195
12.3 BLT Engine Instructions ..................................................................................................................196
12.3.1 SETUP_BLT..............................................................................................................................196
12.3.2 SETUP_MONO_PATTERN_SL_BLT.......................................................................................198
12.3.3 PIXEL_BLT ...............................................................................................................................199
12.3.4 SCANLINE_BLT........................................................................................................................200
12.3.5 TEXT_BLT ................................................................................................................................201
12.3.6 TEXT_Immediate_BLT..............................................................................................................202
12.3.7 COLOR_BLT.............................................................................................................................203
12.3.8 PAT_BLT...................................................................................................................................204
12.3.9 MONO_PAT_BLT .....................................................................................................................205
12.3.10 SRC_COPY_BLT....................................................................................................................206
12.3.11 SRC_COPY_IMMEDIATE_BLT..............................................................................................207
12.3.12 MONO_SRC_COPY_BLT.......................................................................................................208
12.3.13 MONO_SRC_COPY_IMMEDIATE_BLT.................................................................................210
12.3.14 FULL_BLT...............................................................................................................................212
12.3.15 FULL_MONO_SRC_BLT........................................................................................................213
12.3.16 FULL_MONO_PATTERN_BLT...............................................................................................215
12.3.17 FULL_MONO_PATTERN_MONO_SRC_BLT........................................................................217
12.4 BLT Engine Instruction Definitions ..................................................................................................219
12.4.1 BR00—BLT Opcode & Control .................................................................................................219
12.4.2 BR01—Setup BLT Raster OP, Control, and Destination Offset...............................................222
12.4.3 BR02—Clip Rectangle Y1 Address ..........................................................................................224
12.4.4 BR03—Clip Rectangle Y2 Address ..........................................................................................224
12.4.5 BR04—Clip Rectangle X1 and X2 ............................................................................................225
12.4.6 BR05—Setup Expansion Background Color ............................................................................225
12.4.7 BR06—Setup Expansion Foreground Color............................................................................. 226
12.4.8 BR07—Setup Color Pattern Address ........................................................................................ 226
12.4.9 BR08—Destination X1 and X2..................................................................................................227
12.4.10 BR09—Destination Address and Destination Y1 Address...................................................... 228
12.4.11 BR10—Destination Y2 Address..............................................................................................228
12.4.12 BR11—BLT Source Pitch (Offset) or Monochrome Source Quadwords ................................229
12.4.13 BR12—Source Address..........................................................................................................230
12.4.14 BR13—BLT Raster OP, Control, and Destination Pitch .........................................................230
12.4.15 BR14—Destination Width & Height.........................................................................................232
12.4.16 BR15—Color Pattern Address................................................................................................233
12.4.17 BR16—Pattern Expansion Background & Solid Pattern Color ...............................................234
12.4.18 BR17—Pattern Expansion Foreground Color.........................................................................234
12.4.19 BR18—Source Expansion Background, and Destination Color .............................................235
12.4.20 BR19—Source Expansion Foreground Color.........................................................................235
12.4.21 S_SLADD—Source Scan Line Address..................................................................................236
12.4.22 D_SLH—Destination Scan Line Height...................................................................................236
12.4.23 D_SLRADD—Destination Scan Line Read Address ..............................................................237
13. Rendering Engine Instructions........................................................................................................239
13.1 GFXPRIMITIVE...............................................................................................................................239
13.1.1 Axis-Aligned Rectangles ...........................................................................................................239
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13.1.2 Primitive Winding Order ............................................................................................................239
13.1.3 Position Mask............................................................................................................................240
13.1.4 Bias ...........................................................................................................................................240
13.2 Primitive Rendering Instruction Format...........................................................................................240
13.2.1 Variable-Length Vertex Formats for Rendering Instructions.....................................................241
13.3 GFXVERTEX...................................................................................................................................242
13.4 GFXRENDERSTATE_VERTEX_FORMAT..................................................................................... 243
13.4.1 Non-Pipelined State Variables..................................................................................................244
13.5 GFXRENDERSTATE_MAP_TEXELS.............................................................................................244
13.6 GFXRENDERSTATE_MAP_COORD_SETS.................................................................................. 246
13.7 GFXRENDERSTATE_MAP_INFO..................................................................................................248
13.8 GFXRENDERSTATE_MAP_FILTER..............................................................................................254
13.9 GFXRENDERSTATE_MAP_LOD_LIMITS .....................................................................................256
13.10 GFXRENDERSTATE_MAP_LOD_CONTROL..............................................................................257
13.11 GFXRENDERSTATE_MAP_PALETTE_LOAD.............................................................................258
13.12 GFXRENDERSTATE_MAP_COLOR_BLEND_STAGES............................................................. 259
13.13 GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES..............................................................262
13.14 GFXRENDERSTATE_COLOR_FACTOR.....................................................................................264
13.15 GFXRENDERSTATE_COLOR_CHROMA_KEY ..........................................................................265
13.16 GFXRENDERSTATE_SRC_DST_BLEND_MONO ......................................................................266
13.17 GFXRENDERSTATE_Z_BIAS_ALPHA_FUNC_REF...................................................................270
13.18 GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_MODE...................................................... 271
13.19 GFXRENDERSTATE_BOOLEAN_ENA_1....................................................................................273
13.20 GFXRENDERSTATE_BOOLEAN_ENA_2....................................................................................274
13.21 GFXRENDERSTATE_FOG_COLOR............................................................................................275
13.22 GFXRENDERSTATE_DRAWING_RECTANGLE_INFO ..............................................................276
13.23 GFXRENDERSTATE_SCISSOR_ENABLE..................................................................................277
13.24 GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO ............................................................... 278
13.25 Stipple Pattern ...............................................................................................................................279
13.26 GFXRENDERSTATE_ANTI_ALIASING........................................................................................279
13.27 GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION_RULE .............................................281
13.28 GFXRENDERSTATE_DEST_BUFFER_VARIABLES ..................................................................283
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14. Clock Control Registers ...................................................................................................................285
14.1 Programming Notes.........................................................................................................................285
14.2 DCLK_0D — Display Clock 0 Divisor Register ...............................................................................287
14.3 DCLK_1D — Display Clock 1 Divisor Register ...............................................................................288
14.4 DCLK_2D — Display Clock 2 Divisor Register ...............................................................................289
14.5 LCD_CLKD — LCD Clock Divisor Register ....................................................................................290
14.6 DCLK_0DS — Display & LCD Clock Divisor Select Register .........................................................291
14.7 PWR_CLKC — Power Management and Miscellaneous Clock Control.........................................294
15. Video Registers .................................................................................................................................297
15.1 OV0ADD—Overlay 0 Register Update Address Register............................................................... 299
15.2 DOV0STA—Display/Overlay 0 Status Register..............................................................................300
15.3 Gamma Correction..........................................................................................................................302
15.3.1 GAMC[5:0]—Gamma Correction Registers..............................................................................302
15.3.2 Mathematical Gamma Correction for Overlay...........................................................................304
15.4 Overlay Buffer Pointer Registers.....................................................................................................306
15.4.1 OBUF_0Y—Overlay Buffer 0 Y Pointer Register......................................................................307
15.4.2 OBUF_1Y—Overlay Buffer 1 Y Pointer Register......................................................................307
15.4.3 OBUF_0U—Overlay Buffer 0 U Pointer Register .....................................................................307
15.4.4 OBUF_0V—Overlay Buffer 0 V Pointer Register......................................................................308
15.4.5 OBUF_1U—Overlay Buffer 1 U Pointer Register .....................................................................309
15.4.6 OBUF_1V—Overlay Buffer 1 V Pointer Register......................................................................309
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15.5 Overla y Stride Registers..................................................................................................................310
15.5.1 OV0STRIDE—Overlay 0 Stride Register.................................................................................. 310
15.6 Overla y Initia l Phase Reg isters .......................................................................................................311
15.6.1 YRGB_VPH—Y/RGB Vertical-Phase Register.........................................................................311
15.6.2 UV_VPH—UV Vertical-Phase Register .................................................................................... 312
15.6.3 HORZ_PH—Horizontal-Phase Register...................................................................................312
15.6.4 INIT_PH—Initial Phase Register...............................................................................................313
15.7 Overlay Destination Window Position/Size Registers ..................................................................... 314
15.7.1 DWINPOS—Destination Window Position Register ................................................................. 314
15.7.2 DWINSZ—Destination Window Size Register..........................................................................315
15.8 Overlay Source Size Registers........................................................................................................316
15.8.1 SWID—Source Width Register.................................................................................................316
15.8.2 SWIDQW—Source Width in Qwords Register..........................................................................317
15.8.3 SHEIGHT—Source Height Register .........................................................................................318
15.9 Overlay Scale Factor Registers.......................................................................................................319
15.9.1 YRGBSCALE—Y/RGB Scale Factor Register..........................................................................319
15.9.2 UVSCALE—U V Scale Factor Register....................................................................................320
15.10 Overlay Color Correction Registers...............................................................................................321
15.10.1 OV0CLRC0—Overlay 0 Color Correction 0 Register .............................................................321
15.10.2 OV0CLRC1—Overlay 0 Color Correction 1 Register .............................................................321
15.11 Overlay Destination Color Key Registers......................................................................................322
15.11.1 DCLRKV—Destination Color Key Value Register...................................................................322
15.11.2 DCLRKM—D estin ati on Color Key Mask Register................................................................... 322
15.12 Overlay Source Color Key Registers.............................................................................................323
15.12.1 SCLRKVH—Source Color Key Value High Register ..............................................................324
15.12.2 SCLRKVL—Source Color Key Value Low Register................................................................324
15.12.3 SCLRKM—Source Color Key Mask Register .........................................................................325
15.13 Overlay Configuration Registers....................................................................................................326
15.13.1 OV0CONF—O verla y Configurat ion Reg ister..........................................................................326
15.14 OV0CMD—Overlay Command Register .......................................................................................327
15.15 Overlay Alpha Blend Window Positi on/ Si ze Reg isters..................................................................331
15.15.1 AWINPO S— Alp ha Bl end Window Position Register..............................................................331
15.15.2 AWINSZ—Alpha Blend Window Size Register.......................................................................332
15.16 Overlay Flip Instruction..................................................................................................................332
16. Instruction and Interrupt Control Registers ...................................................................................333
16.1 Instruction Control Registers...........................................................................................................333
16.1.1 FENCE—Graphics Memory Fence Table Registers ................................................................333
16.1.2 PGTBL_CTL—Page Table Control Register ............................................................................335
16.1.3 PGTBL_ER—Page Table Error Register (Debug)....................................................................337
16.1.4 RINGBUF—Ring Buffer Registers............................................................................................338
16.1.5 HWS_PGA—Hardware Status Page Address Register ...........................................................339
16.1.6 IPEIR—Instruction Parser Error Identification Register (Debug)..............................................340
16.1.7 IPEHR—Instruction Parser Error Header Register (Debug).....................................................340
16.1.8 INSTDONE—Instruction Stream Interface Done Register .......................................................341
16.1.9 NOPID—NOP Identification Register........................................................................................ 342
16.1.10 INSTPM—Instruction Parser Mode Register ..........................................................................342
16.1.11 INSTPS—Instruction Parser State Register (Debug) .............................................................344
16.1.12 BBP_PTR—Batch Buffer Parser Pointer Register (Debug)....................................................344
16.1.13 ABB_STR—Active Batch Buffer Start Address Register (Debug) ..........................................345
16.1.14 ABB_END—Active Batch Buffer End Address Register (Debug)........................................... 346
16.1.15 DMA_FADD—DMA Engine Fetch Address (Debug)..............................................................347
16.2 Interrupt Control Registers ..............................................................................................................348
16.2.1 HWSTAM—Hardware Status Mask Register............................................................................350
16.2.2 IER—Interrupt Enable Register.................................................................................................351
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16.2.3 IIR—Interrupt Identity Register..................................................................................................352
16.2.4 IMR—Interrupt Mask Register...................................................................................................353
16.2.5 ISR—Interrupt Status Register..................................................................................................354
16.2.6 Error Identity, Mask and Status Registers ................................................................................355
17. LCD / TV-Out Register Description..................................................................................................359
17.1 HTOTAL — Horizontal Total Register.............................................................................................359
17.2 HBLANK — Horizontal Blank Register............................................................................................360
17.3 HSYNC — Horizontal Sync Register...............................................................................................360
17.4 VTOTAL — Vertical Total Register .................................................................................................361
17.5 VBLANK — Vertical Blank Register................................................................................................362
17.6 VSYNC — Vertical Sync Register...................................................................................................363
17.7 LCDTV_C — LCD/TV-Out Control Register....................................................................................364
17.8 OVRACT — Overlay Active Register ..............................................................................................367
17.9 BCLRPAT — Border Color Pattern Register...................................................................................368
17.10 Reserved Registers .......................................................................................................................368
18. Local Memory Interface .................................................................................................................... 369
18.1 DRT—DRAM Row Type..................................................................................................................369
18.2 DRAMCL—DRAM Control Low.......................................................................................................370
18.3 DRAMCH—DRAM Control High......................................................................................................371
19. I/O Control Registers ........................................................................................................................373
19.1 HVSYNC—HSYNC/VSYNC Control Register.................................................................................373
19.2 GPIO Registers ...............................................................................................................................374
19.2.1 GPIOAGeneral-Purpose I/O Control Register A ...................................................................374
19.2.2 GPIOBGeneral-Purpose I/O Control Register B ...................................................................376
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20. Display and Cursor Registers..........................................................................................................379
20.1 DISP_S L—D ispl a y Scan Line Count...............................................................................................379
20.2 DISP_SLC—Display Scan Line Count Range Compare ................................................................ 380
20.3 Pixel Pipeline Control ......................................................................................................................381
20.3.1 PIXCONF—Pixel Pipeline Configuration ..................................................................................381
20.4 BLTCNTL—BLT Control..................................................................................................................384
20.5 Reserved Register...........................................................................................................................385
20.6 SWF[1:3]—Software Flag Registers ...............................................................................................385
20.6.1 DPLYBASE—Display Base Address Register..........................................................................386
20.6.2 DPLYSTAS—Display Status Select Reg is ter ...........................................................................387
20.7 Hardware Cursor .............................................................................................................................389
20.7.1 CURCNTR—Cursor Control Register....................................................................................... 389
20.7.2 CURBASE—Cursor Base Address Register ............................................................................390
20.7.3 CURPOS—Cursor Position Register........................................................................................391
21. Mode Parameters ..............................................................................................................................393
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Figures
Figure 1. GMCH simplified block diagram ........................................................................................................3
Figure 2. Intel
Figure 3. Intel
Figure 4. GMCH block diagram ........................................................................................................................9
Figure 5. System memory map.......................................................................................................................12
Figure 6. Graphics controller I/O and memory map........................................................................................13
Figure 7. GTT mapping...................................................................................................................................19
Figure 8. Graphics controller instruction interface ..........................................................................................20
Figure 9. Ring buffers......................................................................................................................................20
Figure 10. Batch buffer sequence...................................................................................................................23
Figure 11. Memory with overlay active ...........................................................................................................24
Figure 12. Source corruption in BLT with overlapping source and des tination locations...............................38
Figure 13. Correctly performed BLT with overlapping source and destination locations................................39
Figure 14. Suggested starting points for possible source and destination overlaps....................................... 40
Figure 15. Representation of on-screen single 6-pixel line in the frame buffer ..............................................41
Figure 16. Representation of on-scr een 6×4 array of pixels in the frame buffer ............................................42
Figure 17. Pattern data (always an 8×8 array of pixels) .................................................................................44
Figure 18. 8-bpp pattern data — Occupies 64 bytes (8 quadwords)..............................................................45
Figure 19. 16-bpp pattern data — Occupies 128 bytes (16 quadwords)........................................................45
Figure 20. 24-bpp pattern data — Occupies 256 bytes (32 quadwords)........................................................46
Figure 21. 32-bpp pattern data — Occupies 256 bytes (32 quadwords)........................................................46
Figure 22. On-screen destination for example pattern fill BLT .......................................................................48
Figure 23. Pattern data for example pattern fill BLT .......................................................................................49
Figure 24. Results of example pattern fill BLT................................................................................................50
Figure 25. On-screen destination for example character drawing BLT ..........................................................51
Figure 26. Source data in system memory for example character drawing BLT............................................51
Figure 27. Results of example character-drawing BLT...................................................................................53
Figure 28. Graphics controller I/O and memory map....................................................................................168
Figure 29. Graphics controller instruction interface ......................................................................................170
Figure 30. Ring buffers..................................................................................................................................170
Figure 31. Batch buffer sequence.................................................................................................................173
Figure 32. Instruction format for first dword..................................................................................................176
Figure 33. Rectangle vertices .......................................................................................................................239
Figure 34. State variable relationships..........................................................................................................244
Figure 35. State variable relationships..........................................................................................................246
Figure 36. State variable relationships..........................................................................................................248
Figure 37. State variable relationships..........................................................................................................254
Figure 38. State variable relationships..........................................................................................................256
Figure 39. State variable relationships..........................................................................................................257
Figure 40. State variable relationships..........................................................................................................258
Figure 41. State variable relationships..........................................................................................................259
Figure 42. State variable relationships..........................................................................................................262
®
82810 chipset system block diagram with Intel® 82810 GMCH and either ICH or ICH0.........7
®
82810 chipset system block diagram with Intel® 82810-DC100 GMCH and ICH.................... 8
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Intel
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Tables
Table 1. Memory-Mapped Registers...............................................................................................................15
Table 2. Ring Buffer Characteristics ...............................................................................................................21
Table 3. VGA Address Range.........................................................................................................................59
Table 4. CRT Display Sync Polarities...........................................................................................................108
Table 5. VGA Address Range.......................................................................................................................122
Table 6. Memory Address Counter Address Bits [15:0]................................................................................155
Table 7. Frame Buffer Address Decoder ......................................................................................................155
Table 8. Ring Buffer Characteristics .............................................................................................................172
Table 9. Graphics Controller Instructions......................................................................................................177
Table 10. Summary of Source Surface Formats with Filter Output Channel Mappings...............................248
Table 11. Overlay Register/Instruction Categories .......................................................................................298
Table 12. Bit Definition for Interrupt Control Registers .................................................................................348
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1. Introduction
The Intel® 82810 chipset is a highly integrated chipset designed for the basic graphics/multimedia PC platform. The
chipset consists of a Graphics and Memory Controller Hub (GMCH) host bridge and an I/O Controller Hub (ICH/ICH0)
bridge for the I/O subsystem. The GMCH integrates a system memory DRAM controller that supports a 64-bit, 100MHz DRAM array. The DRAM controller is optimized for maximum efficiency.
There are two versions of the GMCH (i.e., 82810, 82810-DC100), which are pin compatible. The difference between the
two versions is that the Intel
®
82810-DC100 integrates a display cache DRAM controller that supports a 4-MB, 32-bit,
100-MHz DRAM array for enhanced 2D and 3D performance.
This document describes both versions of the GMCH (i.e., 82810, 82810-DC100).
An overview of the Intel 82810 chipset is provided in the next section.
Notes: In this document “GMCH” refers to both the 82810 and 82810-DC100 chipsets, unless otherwise specified. The
Intel 82810 and Intel 82810-DC100 chipsets may contain design defects or errors known as errata, which may
cause the product to deviate from published specifications. Current characterized errata are available upon
request.
1.1 Audience
This document is intended for hardware, software, and firmware designers who seek to implement or utilize the graphic
functions of the Intel 82810 and Intel 82810-DC100 chipsets. Familiarity with 2D and 3D graphics programming is
assumed.
1.2 Reference Documents
The following documents should be available for reference when using this specification:
®
Inte1
•
•
•
82810/82810-DC100 Graphics and Memory Controller Hub (GMCH) Datasheet
®
Intel
82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub Datasheet
®
Intel
82802AB/82802AC Firmware Hub (FWH) Datasheet
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Intel® 810 Chipset Family PRM
1.3 Intel® 82810 Chipset System
The Intel 82810 Chipset uses a hub architecture, with the GMCH as the host bridge hub and the 82801xx I/O Controller
Hub (ICH) as the I/O hub. The ICH is a highly integrated, multifunctional I/O controller hub that provides the interface
to the PCI bus and integrates many of the functions needed in today’s PC platforms. The GMCH and ICH communicate
over a dedicated hub interface. As for the GMCH, there are two versions of the ICH (i.e., 82801AA: ICH, 82801AB:
ICH0). This provides added flexibility in designing cost-effective system solutions. These devices are pin compatible
and are housed in 241-pin packages. The GMCH devices are designed to work with either ICH or ICH0.
82801AA (ICH) / 82801AB (ICH0) functions and capabilities include:
PCI Rev. 2.2 compliance, with support for 33-MHz PCI operations
•
ICH0 supports up to 4 Req/Gnt pairs (PCI slots). ICH supports up to 6 Req/Gnt pairs (PCI slots).
•
Power management logic support
•
Enhanced DMA controller, interrupt controller, and timer functions
•
Integrated IDE controller. ICH0 supports Ultra ATA/33. ICH also supports Ultra ATA/66.
•
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USB host interface, with support for 2 USB ports
•
System Management Bus (SMBus) compatible with most I
•
AC ’97 2.1-compliant link for audio and telephony CODECs
•
Low Pin Count (LPC) interface
•
Firmware Hub (FWH) interface support
•
Alert On LAN* (82801AA ICH only)
•
2
C devices
2
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Figure 1. GMCH simplified block diagram
®
Intel
810 Chipset Family PRM
HA[31:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
CPURST#
SMAA[11:0]
SMAB[7:4]#
SBS[1:0]
SMD[63:0]
SDQM[7:0]
SCS[3:0]#
SRAS#
SCAS#
SWE#
SCKE[1:0]
LCS#
LDQM[3:0]#
LSRAS#
LSCAS#
LMA[11:0]
LWE#
LMD[31:0]
System Bus
Interface
System
Memory
Interface
Display
Cache
Interface
®
(Intel
82810-
DC100
Chipset only)
Display
Interface
Digital
TV
Out
Clock
Signals
Misc.
Interface
Signals
Hub
Interface
VSYNC
HSYNC
IREF
RED
GREEN
BLUE
DDCSCL
DDCSDA
LTVCL
LTVDA
TVCLKIN/INT#
CLKOUT[1:0]
BLANK#
LTVDATA[11:0]
TVSYNC
TVHSYNC
HCLK
SCLK
LTCLK
LOCLK
LRCLK
DCLKREF
HLCLK
GLRREFA
GTLREFB
RESET#
HUBREF
HL[10:0]
HLSTRB
HLSTRB#
HCOMP
Note: The Display Cache Interface is only avaliable on the
Intel
®
82810-DC100 chipset.
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2. Product Features of Intel® 82810 Chipset &
Intel
®
82810-DC100 Chipset
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Intel® 810 Chipset Family PRM
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Processor/Host Bus Support
Optimized for the Intel
•
Supports processor 370-pin socket connector
•
Supports 32-bit system bus addressing
•
4-deep in-order queue; 4- or 1-deep request queue
•
Supports uniprocessor systems only
•
In-order & dynamic deferred transaction support
•
66/100-MHz system bus frequency
•
AGTL+ I/O buffer
•
Integrated DRAM Controller
8 MB to 256 MB using 16-Mb/64-Mb technology
•
®
CeleronTM processor
(512 MB usin g 128-Mb technolo gy)
Supports up to 2 double-sided DIMM modules
•
64-bit data interface
•
100-MHz system memory bus frequency
•
Support for asymmetrical DRAM addressing only
•
Support for ×8, ×16 and ×32 DRAM device width
•
Refresh mechanism: CBR ONLY supported
•
Enhanced open page arbitration SDRAM paging
•
scheme
Suspend to RAM support
•
Integrated Graphics Controller
3D hyper-pipelined architecture
•
Parallel data processing (PDP)
•
Precise pixel interpolation (PPI)
•
2D H/W acceleration
•
3D Graphics Visual Enhancements
Flat & Gouraud shading
•
Bilinear and anisotropic filtering
•
Fogging atmospheric effects
•
Z-buffering
•
3D pipe 2D clipping
•
Backface culling
•
3D Graphics Texturing Enhancements
Per-pixel perspective correction texture mapping
•
Texture compositing
•
Display
Integrated 24-bit, 230-MHz RAMDAC
•
Gamma-corrected video
•
DDC2B compliant
•
2D Graphics
Hardware-accelerated function s
•
3-operand raster BitBLTs
•
•64×64×
Arithmetic Stretch Blitter Video
•
•
•
3-color transparent cursor
NTSC and PAL TV-out support
H/W overlay engine with bilinear filtering
Independent gamma correction, saturation,
brightness, and contrast for overlay
Display Cache I/F (Intel® 82810-DC100 chipset only)
32-bit data interface
•
100-MHz SDRAM interface
•
Support for 1M×16, (4 MB only)
•
Arbitration Scheme and Concurrency
Centralized arbitration model for optimum
•
concurrency support
Concurrent operations of processor and system
•
busses, supported via dedicated arbitration and data
buffering
Data Buffering
Distributed data buffering model for optimum
•
concurrency
DRAM write buffer with read-around-write
•
capability
Dedicated CPU-DRAM, hub in t erface-DRAM, and
•
graphics-DRAM read buffers
Power Management Functions
SMRAM space remapping to A0000h (128 KB)
•
Optional extended SMRAM space above 256 MB;
•
additional 512-KB/1-MB TSEG from top of memory;
cacheable
Stop clock grant and halt special cycle translation
•
from the host to the hub interface
ACPI-compliant power management
•
APIC buffer management
•
SMI, SCI, and SERR error indication
•
Supporting I/O Bridge
241-pin BGA I/O controller hub (ICH0/ICH)
•
Packaging/Power
421 BGA
•
1.8V core with 3.3V CMOS I/O
•
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Figure 2. Intel® 82810 chipset system block diagram with Intel® 82810 GMCH and either ICH or ICH0
Digital Video Out
2 IDE Ports
ICH = Ultra ATA/66
ICH0 = Ultra ATA/33
2 USB
Ports
Intel
®
Intel
Intel
®
Pentium
®
III
Processor,
®
Pentium
II
Processor,
and
®
Celeron™ Processor
System Bus (66/100 MHz)
Intel® 810 Chipset
Encoder
®
82810 Chipset
TV
Display
Intel
(GMCH0)
- Memory Controller
- Graphics Controller
- 3D Engine
- 2D Engine
- Video Engine
64 Bit /
100 MHz Only
System
Memory
PCI Slots
(ICH = 6 Req/Gnt pairs)
(ICH0 = 4 Req/Gnt pairs)
PCI Bus
ISA
Option
LAN
Option
USB
USB
ICH and ICH0
(I/O Controller Hub)
FWH
(Firmware Hub)
AC'97
Super
I/O
Audio Codec
Modem Codec
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Intel® 810 Chipset Family PRM
Figure 3. Intel® 82810 chipset system block diagram with Intel® 82810-DC100 GMCH and ICH
Intel® Pentium® lll processor,
®
Pentium® II processor,
Intel
Intel
and
®
Celeron™ Processor
System Bus (66/100 MHz)
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Digital Video Out
Display Cache
(4-MB SDRAM,
100 MHz Only)
2 IDE Ports
Ultra ATA/66
TV
2 USB
Ports
USB
Encoder
Display
USB
Intel® 810 Chipset
®
Intel
82810-DC100
Chipset (GMCH)
- Memory Controller
- Graphics Controller
- 3D Engine
- 2D Engine
- Video Engine
ICH
(I/O Controller Hub)
FWH
(Firmware Hub)
64 Bit /
100 MHz Only
PCI Bus
Super
I/O
AC'97
System
Memory
PCI Slots
(ICH=6 Req/Gnt pairs)
Audio Codec
Modem Codec
ISA
Option
LAN
Option
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2.1 GMCH Overview
Figure 4 is a block diagram of the GMCH, illustrating the various interfaces and integrated components of the GMCH
chip.
GMCH functions and capabilities include:
Support for a single-processor configuration
•
64-bit GTL+-based system bus interface at 66 MHz / 100 MHz
•
32-bit host address support
•
64-bit system memory interface with optimized support for SDRAM at 100 MHz
•
Integrated 2D & 3D graphics engines
•
Integrated 230-MHz DAC
•
Integrated digital video out port
•
4-MB display cache (82810-DC100 only)
•
Figure 4. GMCH block diagram
Display Engine 3D Engine
HW Motion Comp
Analog
Display
Out
Digital
Video
Out
DDC
I
2
C
DAC Overlay
HW Cursor
Digital Video Out
Port
3D
Engine
2D Engine
Stretch
BLT Eng
BLT Eng
System Bus Interface
Buffer
Buffer
Hub Interface
Memory Interface
System
Memory
Display Cache
Memory
(Intel
82810DC100
Chipset only)
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3. System Address Map
The following figure shows the system memory address map for the Intel® 82810 chipset. The GMCH memory map
includes a number of programmable ranges. ALL of these ranges must be unique and non-overlapping. There are NO
hardware interlocks to prevent problems in the case of overlapping ranges. Accesses to overlapped ranges may produce
indeterminate results.
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Intel® 810 Chipset Family PRM
64 GB
4 GB
FEEC 0000h
FEEB FFFFh
FEEA 0000h
FEE9 FFFFh
Size=0/512 KB (fixed)
Base=MMADR Reg.
(14h); Dev 1
Size=0/32/64MB; MISCC Reg.
SMRAM Reg. (70h); Dev 0
SMRAM Reg. (70h); Dev 0
Base Programmed in GC Unit
(72h); Dev 0
Base=GMADR Reg.
(10h); Dev 1
TOM (512 MB Max.)
Size=0KB/512KB/1MB;
Size=0KB/512KB/1MB;
Size=64KB
100000h
0FFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
00000h
System Memory Space
Extended CPU
Memory Space
Optional HSEG
Graphics Controller (GC)
(memory-mapped
control/status registers)
Logical Graphics
Memory
(32MB/64MB)
Optional TSEG
Optional Graphics Buffer
GFX Trans. Tbl (GTT)
Optional ISA Hole
Video BIOS
(shadowed in memory)
Graphics Adapter
(128 KB)
System/Application SW
PCI Memory
PCI Memory
PCI Memory accesses
to GC registers
PCI Memory
PCI Memory Accesses to
Graphics Logical Memory
Translated Through
Graphics Translation
Table (GTT)
PCI Memory
Main
Memory
GTT Access via GC
Control Registers
16 MB
15 MB
1 MB
DOS
Compatibility
Memory
Optionally
mapped to the
internal GC
0FFFFFh 1 MB
Segment F
(BIOS Shadow Area, etc.)
0F0000h
0EFFFFh
0E0000h
0DFFFFh
0DC000h
0DBFFFh
0D0000h
0CFFFFh
0C0000h
0BFFFFh
0A0000h
09FFFFh
000000h
Segment E
(BIOS Shadow Area, etc.)
Optional CD Hole
Segment D
(BIOS Shadow Area, etc.)
Segment C
(BIOS Shadow Area, etc.)
Std PCI/ISA Video Mem
(SMM Mem) 128 KB
DOS Area
(640 KB)
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960 KB
896 KB
880 KB
832 KB
768 KB
640 KB
0 KB
Figure 5. System memory map
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Except for the PCI Configuration registers, all of the GC registers are memory mapped. The base address of this 512-KB
memory block is programmed in the MMADR PCI configuration register. The following figure shows the high-level
memory map of the GC registers. Note that 2D control registers (VGA and extended VGA registers) also are located at
their standard I/O locations.
Note:
1. Some Overlay registers are double buffered with an additional address range
in graphics memory. See Overlay Register
Chapter for details.
I/O Space Map
(Standard graphics locations)
Memory Space Map
(512 KB allocation)
- Cursor Registers
- Display Registers
- Pixel Pipe Registers
Reserved
- Video Capture Registers
- DVD Registers
Blt Engine Control Status (RO)
Overlay Registers
Reserved
Page Table Range
Reserved
Clock Control Registers
Misc I/O Control Registers
Reserved
Local Memory Interface
Control Registers
- Instruction Control Regs.
- Fence Table Registers
- Interrupt Control
VGA and Ext. VGA RegistersVGA and Ext. VGA Registers
1
Offset From
Base_Reg
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
07000h
06FFFh
06000h
05FFFh
05000h
04FFFh
04000h
03FFFh
03000h
02FFFh
01000h
00FFFh
00000h
MMADR Register
(Base Address)
1931
.
Figure 6. Graphics controller I/O and memory map
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Intel® 810 Chipset Family PRM
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VGA and Extended VGA Control Registers (00000h
00FFFh)
−−−−
These registers are located in both I/O space and memory space. The VGA and extended VGA registers contain the
following register sets: General Control/Status, Sequencer (SRxx), Graphics Controller (GRxx), Attribute Controller
(ARxx), VGA Color Palette, and CRT Controller (CRxx) registers. Detailed b it d e scriptions are provided in the
chapter that discusses the VGA and extended VGA registers. The registers within a set are accessed using an indirect
addressing mechanism, as described at the beginning of each section. Note that some register description sections
have additional operational information at the beginning of the section.
Instruction, Memory, and Interrupt Control Registers (01000h
02FFFh)
−−−−
The instruction and interrupt control registers are located in main memory space and contain the following types of
registers:
Instruction Control Registers
••••
Ring buffer registers and page table control registers are located in this address range. Various instruction status,
error, and operating registers are located in this group of registers.
Graphics Memory Fence Registers
••••
The graphics memory fence registers are used for memory tiling capabilities.
Interrupt Control/Status Registers
••••
This register set provides interrupt control/status for various GC functions.
Display Interface Control Register
••••
This register controls the FIFO watermark and provides burst length control.
Local Memory Registers (03000h
03FFFh)
−−−−
These registers are located in main memory space and provide local memory DRAM control.
I/O Control Registers (05000h
05FFFh)
−−−−
This chapter provides I/O control register functions.
Clock Control Registers (06000h
06FFFh)
−−−−
This memory address space is the location of the GC clock control and power management registers.
Page Table Range (10000h
Overlay Registers (30000h
1FFFFh)
−−−−
3FFFFh)
−−−−
These registers provide control of the GC overlay engine. The overlay registers are double-buffered, with one register
buffer located in graphics memory and the other on the GC chip. On-chip registers are not directly writeable. To
update the on-chip registers, software writes to the register buffer area in graphics memory and instructs the GC to
update the on-chip registers.
Blitter Status Registers (40000h
4FFFFh)
−−−−
For debug purposes only, a set of read-only registers provides visibility into the BLT engine stat us.
LCD/TV-out, and HW DVD Registers (60000h
6FFFFh)
−−−−
This memory address range is used for LCD/TV-out control registers and for HW DVD control registers.
Cursor, Display, and Pixel Pipe Registers (70000h
7FFFFh)
−−−−
This memory address range is used for cursor control, display, and pixel pipe control registers.
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3.1 GC Register Memory Address Map
All GC registers are memory-mapped. In addition, the VGA and extended VGA registers are I/O mapped.
Table 1. Memory-Mapped Registers
Address Offset Symbol Register Name Access
00000h−00FFFh
01000h−01FFFh
02000h−0201Fh
02020h−02023h
02024h−02027h
02030h–0207Fh
02030h–0203Fh
02040h–0204Fh
02050h–0207Fh
02080h–02083h HWS_PGA Hardware Status Pa ge Ad dress Register R/W
02084h–02087h
02088h–0208Bh IPEIR Instruction Parser Error Identification R egister RO
0208Ch–0208Fh IPEHR Instruction Parser Error Header Register RO
02090h–02091h INSTDONE Instruction Stream Interface Don e Register RO
02092h–02093h
02094h–02097h NOPID NOP Identification Regist er RO
02098h−002099h
0209Ah–0209Fh
020A0h−020A1h
020A2h–020A3h
020A4h−020A5h
020A6h–020A7h
020A8h−020A9h
020AAh–020ABh
020ACh−020ADh
020AEh−020AFh
020B0h−020B1h
020B2h−020B3h
020B4h−020B5h
020B6h−020B7h
020B8h−020B9h
020BAh−020BBh
Instruction and Interrupt Control Registers (01000h−02FFFh)
FENCE[0:7] Graphics Memory Fence Table Register [0:7] R/W
PGTBL_CTL Page Table Control Register R/W
PGTBL_ER Page Table Error Register RO
RINGBUF Ring Buffer Registers
HWSTAM Hardware Status Mask Register R/W
IER Interrupt Enable Register R/W
IIR Interrupt Identity Register R/WC
IMR Interrupt Mask Registe r R/W
ISR Interrupt Status Register RO
EIR Error Identit y Regist er R/WC
EMR Error Mask Register R/W
ESR Error Status Register RO
VGA and VGA Extended Registers
These registers are both memory- and I/O-mapped and are listed in the
following table. Note that the I/O address and memory offset address
are the sam e value for each register.
Reserved
Low Priority Ring Buffer (4 DWs)
Interrupt Ring Buffer (4 DWs)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
020BDh−020BFh
020C0h INSTPM Instruction Parser Mode Regist er R/W
020C1h–020C3h
020C4h–020C7h INSTPS Instruction Pa rs er State Register RO
020C8h–020CBh BBP_PTR B atch Buffer Parser Point er Register RO
020CCh–020CFh ABB_SRT Active Batch Buffer Start Ad dress Register RO
Reserved
Reserved
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Table 1. Memory-Mapped Registers
Address Offset Symbol Register Name Access
020D0h–020D3h ABB_END Active Batch Buffer End Address Register RO
020D4h–020D7h DMA_FADD DMA Engine Fetch Address Register RO
020D8h–020DBh FW_BLC FIFO Watermark and Burst Length Control R/W
020DCh–020DBh
020DCh–020DFh MEM_MODE Memory Interface Mod e Register R/W
020E0h−02FFFh
03000h DRT DRAM Row Type R/W
03001h DRAMCL DRAM Control Low R/W
03002h DRAMCH DRAM Control High R/W
03003h−03FFFh
04000h−04003h
04004h−04007h
04008h−0400Bh
0400Ch−04FFFh
05000h−05003h
05010h−05013h
05014h−05017h
05018h−05FFFh
UI_SC_CTL Span Cur s o r Co ntr ol R/W
HVSYNC HSYNC/VSYNC Control R/W
GPIOA General-Purpose I/O Control A R/W
GPIOB General-Purpose I/O Control B R/W
Clock Control and Power Management Registers (06000h−06FFFh)
06000h−06003h
06004h−06007h
06008h−0600Bh
0600Ch−0600Fh
06010h−06013h
06014h−06017h
07000h−0FFFFh
DCLK_0D Display Clock 0 Divisor R/W
DCLK_1D Display Clock 1 Divisor R/W
DCLK_2D Display Clock 2 Divisor R/W
LCD_CLKD LCD Clock Divisor R/W
DCLK_0DS Display and LCD Clock Divisor Select R/W
PWR_CLKC Power Management and Miscellaneous Clock Control R/W
Graphics Translation Table Range Definition (10000h−1FFFFh)
10000h−1FFFFh
20000h−2FFFFh
30000h−30003h
30004h−30007h
30008h−3000Bh
3000Ch−3000Fh
30010h−30027h
30028h−300FFh
GTT Graphics Translation Table Range Definition WO
OV0ADDR Overlay 0 Register Update Address Overlay 0 R/W
— Reserved —
DOV0STA Display/Overlay 0 Status RO
— Reserved —
GAMMA[5:0] Gamma Correction [5:0] (6 registers) R/W
— Reserved —
30100h–30103 OBUF_0 Y Overlay Buffer 0 Y Pointer RO
30104h−30107h
30108h−3010Bh
3010Ch−3010Fh
30110h−30113h
30114h−30117h
OBUF_1Y Overlay Buffer 1 Y Pointer RO
OBUF_0U Overlay Buffer 0 U Pointer RO
OBUF_0V Overlay Buffer 0 V Pointer RO
OBUF_1U Overlay Buffer 1 U Pointer RO
OBUF_1V Overlay Buffer 1 V Pointer RO
Reserved
Reserved
Memory Control Registers (03000h−03FFFh)
Reserved
Span Cursor Registers (04000h−04FFFh)
Reserved
Reserved
Reserved
I/O Control Registers (05000h−05FFFh)
Reserved
Reserved (07000h−0FFFFh)
Reserved
Reserved (20000h−2FFFFh)
Reserved
Overlay Registers (30000h−03FFFFh)
R
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Table 1. Memory-Mapped Registers
Address Offset Symbol Register Name Access
30118h−3011Bh
3011Ch−3011Fh
30120h−30123h
30124h−30127h
30128h−3012Bh
3012Ch−3012Fh
30130h−30133h
30134h−30137h
30138h−3013Bh
3013Ch−3013Fh
30140h−30143h
30144h−30147h
30148h−3014Bh
3014Ch−3014Fh
30150h−30153h
30154h−30157h
30158h−3015Bh
3015Ch−3015Fh
30160h−30163h
30164h−30167h
30168h−3016Bh
30170h−30173h
30174h−30177h
30178h−3FFFFh
40000h–40003h BR00 BLT Opcode and Control RO
40004h–40007h BR01 Setup BLT Raster OP, Control, and Destination Offset RO
40008h–4000Bh BR02 Clip Rectangle Y1 Address RO
4000Ch–4000Fh BR03 Clip Rectangle Y1 Address RO
40010h–40013h BR04 Clip Rectangle X1 and X2 Address RO
40014h–40017h BR05 Setup Expansion Background Color RO
40018h–4001Bh BR06 Setup Expansion Foreground Color RO
4001Ch–4001Fh BR07 Setup Color Pattern Address RO
40020h–40023h BR08 Destination X1 and X2 RO
40024h–40027h BR09 Destination Address and Destination Y1 Address RO
40028h–4002Bh BR10 Destination Y2 Address RO
4002Ch–4002Fh BR11 BLT Source Pitch (Offset) or Monochrome Source Quadwords RO
40030h–40033h BR12 Source Address RO
40034h–40037h BR13 BLT Raster OP Control, and Destination Pitch RO
40038h–4003Bh BR14 Destination Width and Height RO
4003Ch–4003Fh BR15 Color Pattern Address RO
40040h–40043h BR16 Pattern Expansion Background and Solid Pattern Color RO
40044h–40047h BR17 Pattern Expansion Foreground Color RO
40048h–4004Bh BR18 Source Expan sion Background and Destination Color RO
4004Ch–4004Fh BR19 Source Expansion Foreground Color RO
40074h–40077h SSLADD Source Scan Line Address RO
40078h–4007Bh DSLH Destination Scan Line Height RO
4007Ch–4007Fh DSLRADD Destination Scan Line Read Address RO
OV0STRIDE Overlay 0 Stride RO
YRGB_VPH Y/RGB Vertical Phase RO
UV_VPH UV Vertical Phase RO
HORZ_PH Horizontal Phase RO
INIT_PH Initial Phase RO
DWINPOS Destination Window Position RO
DWINSZ Destin at ion Window Size RO
SWID Source Width RO
SWIDQW Source Width In qwords RO
SHEIGHT Source Height RO
YRGBSCALE Y/RGB Scale Factor RO
UVSCALE U V Scale Factor RO
OV0CLRC0 Overlay 0 Color Correction 0 RO
OV0CLRC1 Overlay 0 Color Correction 1 RO
DCLRKV Destination Color Key Value RO
DCLRKM Destination Color Key Mask RO
SCLRKVH Source Color Key Value High RO
SCLRKVL S ource Color Key Value Low RO
SCLRKM Source Color Key Mask RO
OV0CONF Overlay 0 Configuration RO
OV0CMD Overlay 0 Command RO
AWINPOS Alpha Blend Window Position RO
AWINZ Alpha Blend Window Size RO
BLT Engine Status (40000h−4FFFFh) (Software Debug)
Reserved
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Table 1. Memory-Mapped Registers
Address Offset Symbol Register Name Access
40080h–4FFFFh
LCD/TV-Out
60000h–60003h HTOTAL Horizontal Total R/W
60004h–60007h HBLANK Horizontal Blank R/W
60008h–6000Bh HSYNC Horizontal Sync R/W
6000Ch–6000Fh VTOTAL Verti cal Total R/W
60010h–60013h VBLANK Vertical Blank R/W
60014h–60017h VSYNC Vertical Sync R /W
60018h–6001Bh LCDTV_C LCD / TV-out Control R/W
6001Ch–6001Fh OVRACT Overlay Active Register R/W
60020h–60023h BCLRPAT Border Color Pattern R/W
70000h–70003h DISP_SL Display Scan Line Count R/W
70004h–70007h DISP_SLC Display Scan Line Count Range Compare R/W
70008h–7000Bh PIXCONF Pixel Pipelin e Configuration R/W
7000Ch–7000Fh BLTCNTL BLT Control R/W
70014h–7001Fh SWF[1:3] Software Flags [1:3] (3 registers) R/W
70020h–70023h DPLYBASE Display Base Address R/W
70024h–70027h DPLYSTAS Disp lay Status Select R/W
70080h–70083h CURCNTR Cursor Control and Vertical Extension R/W
70084h–70087h CURBASE Cursor Base Address R/W
70028h–7002Bh CURPOS Cursor Position R/W
7002Ch–7FFFFh
LCD/TV-Out and HW DVD Registers (60000h–6FFFFh)
Display and Cursor Control Registers (70000h–7FFFFh)
Reserved
Reserved
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3.2 Graphics Address Translation
The Intel 82180 chipset employs a logical memory addressing concept for accessing graphics data. The GC supports a
64-MB logical address space, where each 4-KB logical page can be mapped to a physical memory page in system RAM,
PCI memory or an optional display cache memory. This mapping is performed by means of a Graphics Translation Table
(GTT).
GC engines can address the full 64-MB logical address space. The CPU is provided access to either the full 64-MB space
or just the lower 32 MB, via a PCI memory range associated with the graphics device.
The GTT is allocated in system RAM and maintained by the graphics driver. The 4 KB-aligned physical address of the
64-KB GTT is programmed via the GC’s PGTBL register.
Each 16K-dword GTT entry can map a 4-KB logical page to a physical memory page. Fields in the GTT entry control
the mapping of that logi cal page in the following manner:
(GTT register field “V”) whether or not that logical 4-KB page is mapped to a physical memory page. Accesses to
invalid pages will result in an error interrupt.
(GTT register field “T1T0”) the physical memory address space of the mapped page:
System RAM page (no processor cache snoop)
PCI memory page (processor cache snooped if below TOM)
Display cache page
The page number of the mapped page (within the particular physical memory address space)
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Although the GTT format permits any logical page to be mapped to any page in the supported physical memory address
spaces, the GC imposes restrictions on the how specific graphics operands (buffers, etc.) can be mapped to physical
memory.
The GTT entries must be written via a GTT alias in the graphics device’s memory-mapped register space (10000h1FFFFh). This allows the GC to snoop GTT entry writes and invalidate graphics TLBs as required. The GTT entries
must not be written directly in system memory.
System Memory
31 0
4 GB
Base + 64 MB
Virtual
Graphics
Memory
Base
TOM
4 KB
4 KB
Figure 7. GTT mapping
Translation Table
31 0 31 0
Base + 32 MB
GTT Maps 4KB blocks of Virtual
Graphics Memory to 4 KB pages in
System Memory
Graphics
(GTT)
64 KB
0 KB
GTT Maps 4KB blocks of
Virtual Graphics Memory
to 4 KB pages in Display
Cache
Graphics Engine
Address Space
Optional Display
Cache
64 MB
0
gtt.vs
3.3 Instruction Parser
The GC's Instruction Parser (IP) unit is responsible for
Detecting the presence of instructions (within the ring buffers)
•
Arbitrating the execution of instruction streams
•
Reading instructions from ring buffe rs and batch buffers via DMA
•
Parsing the common "client" (destination) field of instructions
•
Executing instruction parser instructions (which control IP functionality, provide synchronization functions, and
•
provide miscellaneous GC control functions)
Redirecting 2D and 3D instructions to the appropriate destination, while following drawing engine concurrency and
•
coherency rules
Figure 8 is a high-level diagram of the GC instruction interface.
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Batch Buffers
Low Priority Ring
(Graphics Memory)
Instruction
R
Batch Buffers
Batch Buff Instr
Instruction
Interrupt Ring
(Graphics Memory)
Instruction
Batch Buff Instr
Instruction
DMA
DMA
Instruction access and decoding
DMA
FIFO
Instruction Parser Instructions
- Parser Control
(e.g., Batch Buffer Instr., NOP,
Sync ID, Flush, breakpoint )
- Memory Interface Control
(e.g., Store DWord to memory)
- Display/Overlay Control
(e.g., Front Buffer, Scan
Lines, Overlay Flip
Instr
Parser
2D Instructions
3D Instructions (3D state,
3D Primitives, STRBLT,
Motion Compensation)
BLT
Engine
3D
Engine
Display
Engine
Overlay
Engine
cmd_str.vsd
Figure 8. Graphics controller instruction interface
3.4 Ring Buffers (RB)
The GC provides two Ring Buffer (RB) mechanisms via which instructions can be passed to the instruction parser. They
are referred to as the interrupt and low-priority RBs, and they are basically identical, except for differences in arbitration
rules and priority.
Figure 9. Ring buffers
20
Buffer
Length
Buffer
Length
Graphics Memor y
Low Priorit y Ring
Buffer
Interrupt Ring
Buffer
Wrap A r ou nd
Starting Address
Head P oi n ter
DMA Po inter
Ta il Poin ter
Starting Address
Head P oi n ter
DMA Po inter
Ta il Poin ter
RingBuf.vsd
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3.4.1 Ring Buffer Registers
A ring buffer is defined by a set of four ring buffer registers. Before an RB can be used for instruction transport, software
needs to program these registers. The fields contained within these registers are as follows:
Ring Buffer Valid: This bit controls whether the RB is included in the instruction arbitration process. Software must
program all other RB parameters before enabling an RB. An RB can be disabled and later re-enabled. Enabling or
disabling an RB does not, of itself, change any other RB register fields.
Start Address: This field points to a contiguous, 4KB-aligned, linear (e.g., not tiled) memor y address regio n, which
provides the actual instruction buffer area.
Buffer Length: The size of the buffer, in 4-KB increments, up to 2 MB.
Head Offset: This is the dword offset (from the start address) of the next instruction executed by the IP. The IP will
update this field as instructions are retired. (Note that, if instructions are pending execution, the IP likely will have
fetched instructions past the head offset). Because the GC does not “reset” the head offset when an RB is enabled,
software must program the head offset field before enabling the ring buffer. Although this allows software to enable
an RB with any legal values for head/tail (i.e., it can enable or re-enable the RB with instructions already pending),
the software is expected to initialize the head offset at 0. Once the head offset reaches the tail offset (head = tail), the
IP considers the RB "empty."
Head Wrap Count: This field is incremented by the IP each time the head offset wraps back to the start of the buffer.
As it is included in the dword written in the “report head” process, software can use this field to track IP progress as
if the RB had a “virtual” length 2048 times the size of the actual physical buffer.
Tail Offset: This is the qword offset (from the start address) where software will write the next instruction. After
writing instructions into the RB, software updates the tail offset field in orde r to submit the instructions for execution
(by setting it to the qword offset immediately following the last instructio n to be submitted). The submitted
instructions can wrap from the end of the buffer back to the top, in which case the tail offset written will be less than
the previous value. Note that, because the RB empty condition is defined as "head offset == tail offset," software
must leave at least one qword free at all times. (That is, the buffer is considered "full" when only one qword is free.)
Automatic Report Head Enable: Software can request that the hardware head pointer register contents be written
("reported") periodically to snooped system memory. This is desirable, as software needs to use the head offset to
determine the amount of free space in the RB, and having the head pointer periodically reported to system memory
provides a fairly accurate head offset value automatically (i.e., without having to explicitly store a head offset value
via an instruction). The head pointer register will be stored at an RB-specific displacement into the "hardware status
page" (defined by the HWSTAM register).
Table 2. Ring Buffer Characteristics
Characteristic Description
Alignment 4-KB-page aligned
Max. size 2 MB
Length Programmable in number of 4-KB pages
Start pointer Programmable page-aligned address of the buffer
Head pointer Programmable to initially setup ring
Hardware-maintained dword offset in the ring buffer. Pointer wraps.
DMA pointer Hardware-maintained DMA request double qword offset. Pointer wraps.
Tail pointer Programmable double qword offset in the ring buffer
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3.4.2 Ring Buffer Initialization
Before initializing an RB, software must first allocate the desired number of 4-KB pages for use as buffer space. Then
the RINGBUF registers associated with the RB are programmed. Once the Ring Buffer Valid bit is set, the RB will be
considered for instruction arbitration, and the head and tail offsets will either indicate an empty RB (i.e., head == tail) or
will define some number of instructions to be executed.
3.4.3 Ring Buffer Use
Software can write new instructions into the "free space" of the RB, from the tail offset up to (but not including) the
qword prior to the qword indicated by the head offset. (Remember, software must leave at least one qword empty in the
RB at all times.) Note that this "free space" may wrap from the end of the RB back to the start.
Software must use some mechanism to track instruction execution progress, in order to determine the "free space" in the
RB. This can either be:
A direct read of the Head Pointer register
The automatic reporting of the Head Pointer register
The explicit reporting of the Head Pointer register via the GFXCMDPARSER_REPORT_HEAD instruction
Another "implicit" means by which software can determine how far the IP has progressed in retiring instructions fro m
an RB. This could include the use of "Store DWORD" instructions to write sequencing data to system memory.
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Once the instructions have been written (and padded out to a qword, if necessary), software can write the Tail Pointer
register to submit the new instructions for execution.
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3.5 Batch Buffers
The GC provides for the execution of instruction sequences external to RBs. These sequences are called "batch buffers,"
and they are initiated through the use of GFXCMDPARSER_BATCH_ BUFFER instructions that specify the starting
address and length of the batch buffers. The arbitration rules used by the IP when executing batch buffers differ from
those employed when executing RBs, and they are described later in this chapter. When a batch buffer instruction is
executed out of an RB, an initiated batch buffer sequence allows the GC to read the instructions sequentially (via DMA)
from the batch buffer.
What happens when the end of the batch buffer is reached depends on the final instruction in the buffer. If the final
instruction is a GFXCMDPARSER_BATCH_BUFFER instruction, another batch buffer sequence is initiated. This
process, called "chaining," continues until a batch buffer terminates with an instruction other tha n
GFXCMDPARSER_BATCH_BUFFER, at which point execution will resume in the RB at the instruction follo wing the
initial GFXCMDPARSER_BAT CH_BUFFER.
Buff er
Chaining
Buff er
Chaining
Figure 10. Batch buffer sequence
Instruction
Instruction
Batc h Buff Inst r
Instruction
Instruction
Batc h Buff Inst r
Instruction
Instruction
Instruction
From R ing Buffer
Return to Ring Buffer
btch_buf.vsd
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System Memory
Graphics Controller
Register Range
(512 KB)
Base+301xxh
(Base = MMADR PCI Reg.)
Overlay 0 Reg
Graphics Memory
R
On-chip registers for Overlay 0
(read only; debug)
Base+xxh
Overlay 0 Reg
(Base = OV0ADD Reg.)
overlay1.vsd
Figure 11. Memory with overlay active
Memory buffer area for loading on-chip registers
- Software setsup register values
- HW updates on-chip regs for next VBLANK
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4. Graphics Translation Table Range Definition
Address offset: 10000h-1FFFFh
Default va l ue: Page table range 64 KB
Access: Aligned dword-qword, Write Only
This range defined within the graphics memory-mapped register space enables the memory manager to access the
graphics translation table. A page table write will invalidate that entry in internal translation table cache s (TLBs). The
translation table resides in system memory and can be accessed directly by the memory manager. However, to ensure
coherency between hardware-maintained translation caches and the translation table in main memory, the memory
manager must use this range to update the translation table.
The page table must be QW aligned, with each entry being dword aligned such that each QW stores the translation for
two 4-KB pages. The page table base address for graphics memory will be programmed in the PGTB_CNTL register.
For a graphics memory of 64 MB with a TLB block size of 4 KB, 16 K entries will be needed. Each entry can be
accommodated in 4Bs, so the page table will be 64 KB in size.
Page Table Entry: 1 dword per 4-KB page
31 30 29 12 11 3 2 1 0
XX=00 Physical address 29:12 Reserved T1T0 V
V: 1 = Valid page table entry (PTE)
0 = Invalid page table entry (PTE). An access to an invalid PTE will result in an interrupt.
T1T0: 01 = Physical address targets local memory.
00 = Physical address targets main memory (not snooped).
11 = Physical address targets cacheable main memory (results in snoop on processor bus) .
10 = Reserved.
Note: T1T0 = 11 is used only if the surface is a blit source or destination operand used within the conte xt of a
source copy command.
XX: Reserved. Must be 0.
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5. Basic Initialization Procedures
5.1 Initialization Sequence
The initialization of graphics driver resources can be broken down into three categories: hardware detection, frame
buffer initialization, and hardware register initialization. Each category is discussed in more detail in the following
sections.
In all discussions that follow, there is a basic assumption that the graphics adapter has completed the power-on video
BIOS initialization or video BIOS reset. Therefore, the adapter is in a known state and will respond in compliance with
the VGA and VESA specifications.
5.2 Hardware Detection (Probe)
Most operating systems will probe for installed devices. The Intel® 8281x family of devices advertises their presence in
PCI space by using unique values in the PCI VendorId and DeviceId locations. The following table lists the device IDs
used to identify the members of the 8281x family of graphics adapters:
Vendor Id
PCI Offset: 0
8086 7120 0 82810 bridge
8086 7121 1 82810
8086 7122 0 82810 DC100 bridge
8086 7123 1 82810 DC100
8086 7124 0 82810E bridge
8086 7125 1 82810E
8086 1100 0 82815 GMCH host-hub interface bridge /
8086 1101 1 82815 FSB limited to 100 MHz
8086 1102 2 82815 FSB limited to 100 MHz
8086 1110 0
8086 1112 2
8086 1120 0 82815 no internal graphics, AGP only
8086 1121 1 No internal graphics, AGP only
Device Id
PCI Offset: 2
PCI Device
Number Characteristics
DRAM controller FSB limited to 100 MHz
AGP bridge
Internal graphics device
82815 no AGP, internal graphics only
GMCH host-hub interface bridge / DRAM controller
82815 no AGP, internal graphics only
Internal graphics device
GMCH host-hub interface bridge / DRAM controller
AGP bridge
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8086 1130 0 82815 fully featured Solano
GMCH host-hub interface bridge / DRAM controller
8086 1131 1
82815 fully featured Solano
AGP bridge
8086 1132 2
82815 fully featured Solano
Internal graphics device
Once the operating system has identified the device, it can load the appropriate driver.
One of the first tasks of the driver is to make sure that the device matches the driver. Checking that the driver and device
match is done in much the same way that the operating system identifies the graphics adapter. That is, the PCI VendorId
and ProductId values are examined. Some operating systems will make available to the driver the values it found during
its scan. If not, the driver must scan the PCI space until it finds a match on the VendorId and ProductId values. The
driver normally caches this information so that it is accessible by other driver modules, when needed.
The next task of the device driver is to ensure that required resources are present. These resources include the minimum
memory requirements, IO address space requirements, and operating system support requirements (such as GART
support). If the driver detects that the operating system or the physical hardware does not meet the driver’s minimum
requirements, the driver should not load. The operating system should then be able to make use of the graphics adapter in
its VGA- and VESA-compliant mode.
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If the operating system and hardware support are present, the driver should acquire the blocks of memory and IO address
space that will be required. These blocks should include at least the following:
Memory-mapped IO address space: 512 KB beginning at 0x80000
•
Linear frame buffer space: 32 or 64 MB beginning at 0xfe000000
•
Legacy IO addresses to support monochrome or color monitors
•
VGA IO addresses
•
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5.3 Frame Buffer Initialization
The frame buffer initialization is responsible for setting up the memory that will contain the display data. Other objects
also can be stored in display memory.
The following steps should be performed:
Map a 0x80000-byte region in memory to the MMIO base address. The base address of the memory-
•
mapped region should be programmed into the MMADDR register, offset 14 in the PCI address space.
Allocate enough memory for the frame buffer from a memory pool created during initialization. The
•
amount of memory is determined by system characteristics, but should default to at least 8 MB.
If a hardware cursor is being used, allocate memory for the hardware cursor from the same memory
•
pool. The hardware does not use the GART to access the memory for the cursor, so local-to-physical
memory address translation must be performed. The hardware cursor memory address should be
programmed into the CURBASE register, memory-mapped address 70084h.
The low-priority ring buffer memory should be initialized to 0. The low-priority ring buffer pointers
•
should be programmed into the ring buffer pointer registers, RINGBUF, which begin at offset 2030h in
the memory-mapped IO space.
5.4 Hardware Register Initialization
5.4.1 Color vs. Monochrome Monitors
The mapping and initialization of some hardware registers depends in part on whether the graphics adapter is attached to
a monochrome or color monitor. The following steps illustrate how to determine the type of output device attached to the
graphics adapter:
Read the Miscellaneous Output Register (0x3cc).
•
Test the low-order bit of the Miscellaneous Output Regi ster, and interpret it as follows:
•
0: The adapter is in monochrome monitor mode. In this mode, the control register is 3b4 and
•
3b5, and status is at 3ba.
1: The adapter is in color monitor mode. In this mode, the control register is 3d4 and 3d5, and
•
status is at 3da.
See the section on VGA compatibility for a description of the register space that must be acquired.
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5.4.2 Protect Registers: Locking and Unlocking
In order to make use of some protected VGA registers, a locking and unlocking mechanism needs to be implemented.
The following steps illustrate how to unlock (or unprotect) the VGA registers:
Send a VERT_SYNC_END value to the register at vgaBase + 4.
•
Read the value in the register at vgaBase + 5.
•
Clear the high-order bit of the value just read.
•
Write the resulting value back into the register at vgaBase + 5.
•
5.4.3 Checking Memory Frequency
The driver behavior occasionally must be modified, depending on the frequency at which the memory is running. The
following steps illustrate how to determine the local memory frequency:
Read the contents of the Intel 82810 Chipset Configuration Register (PCI address space 0x50).
•
Examine the value of bit 4.
•
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The value is interpreted as follows:
•
0: Frequency is 100 MHz.
•
1: Frequency is 133 MHz.
•
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5.5 Hardware State
Under certain conditions, it may be necessary to save and restore the hardware state of the graphics adapter. These
conditions include mode switching, output device switching, processing changes in po wer state, and others. The next t wo
sections provide a brief description of the state saving and restoration requirements.
5.6 Saving the Hardware State
Note that the VGA register unlocking protocol must be performed in order to access some of the registers described
below.
The driver should preserve the following registers during a state change in order to provide complete state restoration in
the future:
IO Control CR80
Address Mapping GR10
Bit Blit Control MM 0x7000c
Video Clock 2 / M MM 0x6008
Video Clock 2 / N MM 0x600c
Video Clock 2 / Divisor Select MM 0x6012
Vertical Total CRX 30
Vertical Display End CRX 31
Vertical Sync Start CRX 32
Vertical Blank Start CRX 33
Horizontal Total CRX 35
Horizontal Blnk CRX 39
Ext Offset CRX 41
Interlace Control CRX 70
Hardware Status Mask Register MM 0x2098
Interrupt Enable Register MM 0x20a0
Interrupt Identity Register MM 0x20a4
Interrupt Mask Register MM 0x20a8
Error Mask Register MM 0x20b4
Display Control Register MM 0x70008
Pixel Pipeline Configuration 0 Register MM 0x70009
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Intel® 810 Chipset Family PRM
Pixel Pipeline Configuration 1 Register MM 0x7000a
Pixel Pipeline Configuration 2 Register MM 0x7000b
Watermark and Burstlength Control MM 0x20d8
Low-priority ring information MM 0x2030 – 0x203f
5.7 Restoring the Hardware State
The graphics adapter state should be restored by performing the following steps. Note some of the synchronization
operations, especially those that ensure that the local memory is idle during the state restore. Also, much of the work
involves reprogramming the registers with the values captured during the save-state operation.
Blank the screen.
•
Turn off DRAM refresh.
•
Read the value of the DRAM_CONTROL_HI Register (MM 0x3002).
•
Set the DRAM Refresh Rate bits (DDR Bits 4:3) to Disable_Refresh (value 0).
•
R
Write the modified value back to the DRAM_CONTROL_HI Register.
•
Write the M, N, and P (i.e., the Divisor Select value) values from the saved state information.
•
Restore the 8-bit DAC mode to what it was when the state was saved, but preserve the current value of
•
the rest of the register containing this flag:
Read the Pixel Pipeline Configuration 0 Register.
•
Clear the current value of the 8- or 6-bit DAC mode.
•
OR–in (only) the value of the DAC_8_BIT from saved register information of the Pixel
•
Pipeline Configuration 0 Register.
Write the result back to the Pixel Pipeline Configuration 0 Register.
•
Restore the generic VGA registers to the values captured at save-state time.
•
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Restore the following registers to their saved state values:
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Vertical Total CRX 30
Vertical Display End CRX 31
Vertical Sync Start CRX 32
Vertical Blank Start CRX 33
Horizontal Total CRX 35
Horizontal Blnk CRX 39
Ext Offset CRX 41
The following registers should restore only certain bits from the saved state values:
•
Interlace Control CRX 70
Read the current value.
•
Clear the interlace enable bit.
•
OR–in the saved value of the Interlace Control Register.
•
Write the result back into the Interlace Control Register.
•
Address Mapping: GR10
Read the current value of the Address Mapping Register.
•
Save only the reserved bits values (bits 7:5).
•
OR–in the saved value of the Address Mapping Register.
•
Write the result back into the Address Mapping Register.
•
Now the DRAM refresh can be turned on:
•
Read the value of the DRAM_CONTROL_HI Register.
•
Turn off the DRAM_REFRESH_RATE bits.
•
OR–in a 60-Hz refresh rate value.
•
Write the result back into the DRAM_CONTROL_HI Register.
•
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Intel® 810 Chipset Family PRM
Other registers that should restore only certain bits from the saved-state values:
•
Bit Blit Control MM 0x7000c
Read the current value of the Bit Blit Control Register.
•
Clear the bits pertaining to the Color Expansion Mode (bits 5:4).
•
OR–in the saved value of the Bit Blit Control Register.
•
Write the result back into the Bit Blit Control Re gister.
•
Display Control Register MM 0x70008
Read the current value of the Display Control Register.
•
OR–in the saved value of t he Display Cont rol Register.
•
Write the result back into the Display Control Regi ster.
•
R
Pixel Pipeline Configuration 0 Register MM 0x70009
Read the current value of the Pixel Pipeline Configuration 0 Register.
•
Save reserved bits 6:5 and 2. Clear all other bits.
•
OR–in the saved value of the Pixel Pipeline Configuration 0 Re gister.
•
Write the result back into the Pixel Pipeline Co nfiguration 0 Register.
•
Pixel Pipeline Configuration 2 Register MM 0x7000b
Read the current value of the Pixel Pipeline Configuration 2 Register.
•
Save reserved bits 7:4 and 1:0. Clear all other bits.
•
OR–in the saved value of the Pixel Pipeline Configuration 2 Re gister.
•
Write the result back into the Pixel Pipeline Co nfiguration 2 Register.
•
Pixel Pipeline Configuration 1 Register MM 0x7000a
Read the current value of the Pixel Pipeline Configuration 1 Register.
•
34
Clear the Display Color Mode bit (bits 3:0).
•
OR–in the saved value of the Pixel Pipeline Configuration 1 Re gister.
•
Write the result back into the Pixel Pipeline Co nfiguration 1 Register.
•
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®
Intel
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Hardware Status Mask Register MM 0x2098
Read the current value of the Hardware Status Mask Register.
•
Clear everything but the reserved bits (14:13).
•
OR–in the saved value of the Hardware Status Mask Register.
•
Write the result back into the Hardware Status Mask Register.
•
Interrupt Enable Register MM 0x20a0
Read the current value of the Interrupt Enable Register.
•
Clear everything but the reserved bits (14:13).
•
OR–in the saved value of the Interrupt Enable Register.
•
Write the result back into the Interrupt Enable Register.
•
Interrupt Mask Register MM 0x20a8
Read the current value of the Interrupt Mask Register.
•
Clear everything but the reserved bits (14:13).
•
OR–in the saved value of the Interrupt Mask Register.
•
Write the result back into the Interrupt Mask Register.
•
Error Mask Register MM 0x20b4
Read the current value of the Error Mask Register.
•
Clear everything but the reserved bits (15:6).
•
OR–in the saved value of the Error Mask Register.
•
Write the result back into the Error Mask Register.
•
Watermark and Burstlength Control MM 0x20d8
Read the current value of the Watermark and Burstlength Control Register.
•
Clear the burst length and watermark bits (bits 22:20, 17:12, 10:8 and 5:0).
•
OR–in the saved value of the Watermar k and Burstlength Control Register.
•
Write the result back into the Watermark and Burstlength Co ntrol Register.
•
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Intel® 810 Chipset Family PRM
Disable the low-priority ring buffer, in preparation for setting new values, by clearing the
•
RING_VALID bit in the Low-Priority Ring Buffer Length field at MM 0x203c.
Read the current value of the Low-Priority Ring Buffer Length field (MM 0x203c).
•
Clear the valid bit (bit 0).
•
Write the result back into the Low-Priority Ring Buffer Length field.
•
Set up the low-priority ring buffer.
•
Write a 0 to the low-priority ring buffer tail at MM 0x2030.
•
Write a 0 to the low-priority ring buffer head at MM 0x2034.
•
Restore the low-priority ring buffer start at MM 0x2038, but preserve the reserved bits.
•
Restore the Low-Priority Ring Buffer Length field, but preserve the Automatic Report Header
•
Pointer bits and set the Ring Buffer Valid flag.
Turn on the screen.
•
Relock the protected register space in order to complete the state restoration process.
•
R
At this point the graphics adapter should function completely, in the mode identified by the saved-state information.
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6. BLT Engine Programming
6.1 BLT Engine Programming Considerations
6.1.1 When the Source and Destination Locations Overlap
It is possible to have BLT operations in which the locations of the source and de stinat ion data overlap. This frequently
occurs in BLT operations where a user is shifting the position of a graphical item on the display by only a few pixels. In
these situations, the BLT engine must be progra mmed so that destination data is not written into destination locations
that overlap source locations, before the source data at those locations has been read. Otherwise, the source data will
become corrupted.
The following figure shows how the source data can be corrupted when a rectangular block is copied from a source
location to an overlapping destination location. The BLT engine reads fro m the so urce lo cation and writes to the
destination location, starting with the leftmost pixel in the top line of both, as shown in Step (a). As shown in Step (b),
corruption of the source data already started with the copying of the top line in Step (a). Part of the source that originally
contained lighter pixels now has been overwritten with darker pixels. More source data corruption occurs as Steps (b)
through (d) are performed. At Step (e), another line of source data is read, but the two rightmost pixels of this line are in
the region where the source and destination locations overlap and where the source has already been overwritten as a
result of the copying of the top line in Step (a). Starting in Step (f), darker pixels can be seen in the destination where
lighter pixels should be. This errant effect occurs repeatedly during the remaining steps of this BLT operation. As more
lines are copied from the source location to the destination location, it becomes clear that the end result is not what was
intended originally.
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Intel® 810 Chipset Family PRM
Source
R
(b)
(c)
(a)
Destination
(d)
(e)
(f)
Source
(g)
(i)
(h)
Destination
Figure 12. Source corruption in BLT with overlapping source and destination locations
38
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When necessary, the BLT engine can alter the order in which source data is read and destination data is writte n, in ord er
to avoid source data corruption problems when the source and destination locations overlap. The command packets
provide the ability to change the point at which the BLT engine begins reading and writing data from the upper-left-hand
corner (the usual starting point) to one of the other three corners. The BLT engine may be set to read data from the
source and write it to the destination, starting at any of the four corners of the panel.
(b)
Source
(c)
(a)
Destination
(d)
(e)
(f)
Source
(g)
(i)
(h)
Destination
Figure 13. Correctly performed BLT with overlapping source and destination locations
b_blt3.vsd
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Intel® 810 Chipset Family PRM
n
n
The figure below illustrates how this BLT engine feature can be used to perform the BLT operation illustrated in the
figure above, while avoiding source data corruption. As shown in the figure below, the BLT engine reads the source data
and writes the data to the destination, starting with the right-most pixel of the bottom line. In this manner, no pixel at the
overlap of the source and destination locations ever will be written to before it is read from by the BLT engine. B y the
time the BLT operation has reached Step (e), where two pixels at the overlap of the source and destination locations are
about to be overwritten, the source data for those two pixels has already been read.
R
Destination
Destination Source
OR
Destination Source
Source
Source
Destination Destination
OR
Source Source
Source Source
Destinatio
Source
DestinationSource
OR
DestinationSource
Source
OR
Destination
Destination Destination
Destinatio
b_blt4.vsd
Figure 14. Suggested starting points for possible source and destination overlaps
The figure above shows the recommended lines and pixels to be used as starting points in each of the eight possible ways
in which the source and destination locations may overlap. In general, the starting point should be within the area of
source and destination overlap.
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6.2 Basic Graphics Data Considerations
6.2.1 Contiguous vs. Discontinuous Graphics Data
Graphics data stored in memory, particularly in the frame buffer of a graphics system, has organizational characteristics
that often distinguish them from other varieties of data. The main distinction is the tende ncy for graphics data to be
organized in a discontinuous block made up of multiple sub-blocks of bytes, instead of a single contiguous block o f
bytes.
(0, 0)
256, 256 261, 256
256th Scan Line
Note: Drawing is not to scale
(0, 479) (639, 479)
(639, 0)
Figure 15. Representation of on-screen single 6-pixel line in the frame buffer
63
32 31 0
b_blt5.vsd
270F8h
28100h
28108h
The figure above shows an example of contiguous graphics data: a horizontal line made up of six adjacent pixels within a
single scan line on a display with a resolution of 640×480. Presuming that the graphics system driving this display has
been set to 8 bits per pixel and that the frame buffer’s starting address (0h) corresponds to the upper-leftmost pixel of this
display, the six pixels that make this horizontal line starting at coordinates (256, 256) would occupy six bytes, starting at
frame buffer address 28100h and ending at address 28105h.
In this case, there is only one scan line’s worth of graphics data in this single horizontal line, so the block of graphics
data for all six of these pixels exists as a single, contiguous block comprised only of these six bytes. The starting address
and the number of bytes are the only pieces of information that a BLT engine would require to read this block of data.
The simplicity of the preceding example of a single horizontal line contrasts sharply with the example of discontinuous
graphics data depicted in the following figure. The simple six-pixel line of the figure above now is accompanied by three
more six-pixel lines placed on subsequent scan lines, resulting in the 6×4 block of pixels shown.
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Intel® 810 Chipset Family PRM
R
(0, 0)
256, 256 261, 256
256, 259 261, 259
Note: Drawing is not to scale
(0, 479) (639, 479)
Figure 16. Representation of on-screen 6
(639, 0)
256th Scan Line
257th Scan Line
258th Scan Line
259th Scan Line
4 array of pixels in the frame buffer
××××
63
32 31 0
b_blt6.vsd
270F8h
28100h
28108h
270F8h
28100h
28108h
270F8h
28100h
28108h
270F8h
28100h
28108h
On each of the scan lines in which this 6×4 block exists, there are other pixels that are not part of this 6×4 block, so what
appears to be a single 6×4 block of pixels on the display must be represented by a discontinuous block of graphics data
made up of four separate sub-blocks of six bytes apiece, in the frame buffer at addresses 28100h, 28380h, 28600h, and
28880h. This situation makes more complex the task of reading what appears to be a simple 6×4 block of pixels.
However, there are two characteristics of this 6×4 block of pixels that help simplify the task of specifying the locations
of all 24 bytes of this discontinuous block of graphics data: all four of the sub-blocks are of the same length and the four
sub-blocks are separated from each other at equal intervals.
The BLT engine is designed to make use of these characteristics of graphics data, in order to simplify the programming
required to handle discontinuous blocks of graphics data. For such a situation, the BLT engine requires only four pieces
of information: the starting address of the first sub-block, the length of a sub-block, the offset (in b ytes) (i.e., the pitch) of
the starting address of each subsequent sub-block, and the quantity of sub-blocks.
6.2.2 Source Data
The source data may exist in the frame buffer or main memory graphics memory, where the BLT engine may read it
directly, or it may be provided to the BLT engine by the host CPU through the command packets. The block of source
graphics data may be either contiguous or discontinuous and may be either in color (with a color depth that matches that
to which the BLT engine has been set) or monochrome.
The source select bit in the command packets specifies whether the source data exists in the frame buffer or are provided
through the command packets. Monochrome source data always is specified as being supplied through an immediate
command packet.
If the color source data resides within the frame buffer or main memory’s graphics memory, then the Source Address
Register specified in the command packets is used to specify the address of the source. However, if the host CPU
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provides the source data, then this register takes on a different function, and the three least-significant bits of the Source
Address Register can be used to specify the number of bytes that must be skipped in the first quadword received from the
command packet, in order to reach the first byte of valid source data.
In cases where the host CPU provides the source data, it does so by writing the source data to the ring buffer directly
after the BLT command that requires the data or uses an IMMEDIATE_INDIRECT_BLT command packet that has a
size and pointer to the operand in main memory’s graphics memory.
There also is an address space used for debug, where the CPU can write the source data. It is a 64-KB memory space on
the host bus. There is no actual memory allocated to this memory space, so any data that is written to this locatio n cannot
be read back. This memory space is simply a range of memory addresses that the BLT engine’s address decoder watches
for the occurrence of any memory writes.
The BLT engine loads all data written to any memory address within this memory space or through the command packet,
in the order in which they are written, regardless of the specific memory address to which they are written, and it then
uses that data as the source data in the current BLT operation. The block of bytes sent by the host CPU to either t his data
port or through the command packets must be quadword-aligned, although the source data contained within the block of
bytes does not need to be aligned. As mentioned previously, the least-significant three bits of the Source Address
Register are used to specify the number of bytes that must be skipped in the first quadword of color data, in order to
reach the first byte of valid source data.
To accommodate discontinuous source data, the source and destination pitch registers can be used to specify the offset,
in bytes, from the beginning of one scan line’s worth of source data to the next. Otherwise, if the source data is
contiguous, then an offset equal to the length of a scan line’s worth of source data should be specified.
6.2.3 Monochrome Source Data
The opcode of the command packet specifies whether the source data is color or monochrome. Since monochrome
graphics data only uses one bit per pixel, each byte of monochrome source data typically carries data for eight pixels,
which hinders the use of byte-oriented parameters when specifying the location and size of valid source data.
Monochrome source data always is supplied through the command stream, which avoids the read latency during BLT
engine operation. Some additional parameters must be specified in order to ensure the proper reading and use of
monochrome source data by the BLT engine. The BLT engine also provides additional optio ns for the manipulation of
monochrome source data versus color source data.
Various bitwise logical operations and per-pixel write-masking operations were designed to work with color data. In
order to use monochrome data, the BLT engine converts it into color data through a process called color expansion,
which takes place as a BLT operation is performed. In color expansion, the single bits of monochrome source data are
converted into one, two, three or four bytes (depending on the color depth to which the BLT engine has been set) of color
data that are set to carry value corresponding to either the foreground or background color specified for use in this
conversion process. If a given bit of monochrome source data carries the value 1, then the byte(s) of color data resulting
from the conversion process will be set to carry the value of the foreground color. If a given bit of monochrome source
data carries the value 0, then the resulting byte(s) will be set to the value of the background color. The foreground and
background colors used in the color expansion of monochrome source data can be set in the source expansion foreground
color register and the source expansion background color register.
The BLT engine requires the specification of the bit alignment of each scan line’s worth of monochrome source data.
Each scan line’s worth of monochrome source data is word-aligned, but it actually can start on any bit boundary of the
first byte. Monochrome text is a special case and is bit-packed, such that there are no invalid pixels (bits) between scan
lines. Mono Source Start is a three-bit field that indicates the starting pixel position within the first b yte for each scan
line.
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Intel® 810 Chipset Family PRM
d
The BLT engine also provides various clipping options for use with specific BLT commands (BLT_TEXT), with a
monochrome source. Clipping is supported via clip rectangle Y addresses and X coordinates, scan line starting and
ending addresses, and X starting and ending coordinates.
6.2.4 Pattern Data
The color pattern data must exist within the frame buffer or main memory’s graphics memory, where the BLT engine
may read it directly. Monochrome pattern data is supplied by the command packet when it is to be used. As shown in
following figure, the block of pattern graphics data always is represented as an 8×8 block of pixels. The bits or bytes of a
block of pattern data may be organized in the frame buffer memory in only one of four ways, depending upon its color
depth, which may be 8, 16, 24 or 32 bits per pixel (whichever matches the color depth to which the BLT engine has been
set) or monochro me.
R
Pixel (0, 0)
Pixel (0, 7)
63 57 56 48 47 40 39 24 2332 31 16 15 8 7
Pixel
(0, 7)
Figure 17. Pattern data (always an 8
Pixel
(7, 7)
8 array of pixels)
××××
Pixel
(0, 0)
Pixel (7, 0)
Pixel (7, 7)
b_blt7.vsd
0
b_blt8.vs
Pixel
(7, 0)
The Pattern Address Register is used to specify the color pattern data address at which the block of pattern data begins.
The three least-significant bits of the address written to this register are ignored, because the address must be specified in
units of quadwords. This is because the pattern always must be located on an address boundary equal to its size.
Monochrome patterns take up 8 bytes (i.e., a quadword of space) and are loaded through the command packet that uses
it. Similarly, color patterns with color depths of 8, 16, and 32 bits per pixel must start on 64-byte, 128-byte, and 256-byte
boundaries, respectively. Color patterns with color depths of 24 bits per pixel must start on 256-byte boundaries, despite
the fact that the actual color data fills only 3 bytes per pixel. The next four figures show how monochrome, 8-bpp, 16bpp, 24-bpp, and 32-bpp pattern data, respectively, is organized in memory.
44
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Intel
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63 57 56 48 47 40 39 24 2332 31 16 15 8 7
Pixel (0, 7)
Pixel (7, 7)
Figure 18. 8-bpp pattern data — Occupies 64 bytes (8 quadwords)
63 48 47 32 31 16 15
Pixel (7, 0
Pixel (7, 7
Pixel (0, 0
Pixel (0, 7
Pixel (0, 0)
Pixel (7, 0)
0
00h
08h
10h
18h
20h
28h
30h
38h
b_blt9.vsd
0
00h
08h
68h
70h
78h
b_blt10.vsd
Figure 19. 16-bpp pattern data — Occupies 128 bytes (16 quadwords)
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Intel® 810 Chipset Family PRM
(
)
)
)
)
R
56 55 40 39 24 23 8 7
Pixel (0, 0)
Pixel (0, 7)
Red Green Blue
Red Green Blue
Pixel (7, 0)
"Throw-Away" Fourth Bytes for Pixels (0, 0) through (7, 0)
Pixel (7, 7)
"Throw-Away" Fourth Bytes for Pixels (0, 7) through (7, 7)
Red Green Blue
Red Green Blue
Figure 20. 24-bpp pattern data — Occupies 256 bytes (32 quadwords)
63 48 47 32 31 16 15
Pixel
3, 0
Pixel (0, 0
063 48 47 32 31 16 15
00h
08h
10h
18h
D8h
E0h
E8h
F0h
F8h
b_blt11.vsd
0
00h
08h
68h
70h
78h
b_blt10.vsd
Pixel (7, 7
Pixel (4, 7
Figure 21. 32-bpp pattern data — Occupies 256 bytes (32 quadwords)
As is shown in the 24-bpp pattern data figure, four bytes are allocated for each pixel on each scan line’s worth of pattern
data, which allows each scan line’s worth of 24-bpp pattern data to begin on a 32-byte boundary. The extra (i.e.,
“fourth”) unused bytes of each pixel on a scan line’s worth of pattern data are collected together in the last 8 bytes (i.e.,
the last quadword) of each scan line’s worth of pattern data.
The opcode of the command packet specifies whether the pattern data is color or monochrome. The various bitwise
logical operations and per-pixel write-masking operations were designed to work with color data. In order to use
monochrome pattern data, the BLT engine is designed to convert it to color, through a process called “color expansion”
that takes place as a BLT operation is performed. In color expansion, the single bits of monochrome pattern data are
converted to one, two, three or four bytes (depending on the color depth to which the BLT engine has been set) of color
data that are set to carry values corresponding to either the foreground or background color specified for use in this
process. The foreground color is used for pixels corresponding to a bit of monochrome pattern data that carries the value
1, while the background color is used where the corresponding bit of monochrome pattern data carries the value 0. The
foreground and background colors used in the color expansion of monochrome pattern data can be set in the Pattern
Expansion Foreground Color Register and Pattern Expansion Background Color Register.
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6.2.5 Destination Data
There are actually two different types of “destination data”: the graphics data already residing at the location designated
as the destination and the data to be written to that location, as a result of a BLT operation.
The location designated as the destination must be within the frame buffer or the main memory’s graphics memory,
where the BLT engine can directly read from it and write to it. The blocks of destination data to be read from and written
to the destination may be either contiguous or discontinuous. All data writte n to the destination will have the color depth
to which the BLT engine has been set. It is presumed that any data already existing at the destination to be read by the
BLT engine also will be of this same color depth. The BLT engine neither reads nor writes monochrome destination
data.
The Destination Address Register is used to specify the address of the destination.
To accommodate discontinuous destination data, the Source and Destination Pitch Registers can be used to specify the
offset, in bytes, from the beginning of one scan line’s worth of destination data to the next. Otherwise, if the destination
data is contiguous, then an offset equal to the length of a scan line’s worth of destination data should be specified.
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Intel® 810 Chipset Family PRM
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6.3 BLT Programming Examples
6.3.1 Pattern Fill — A Very Simple BLT
In this example, a rectangular area on the screen will be filled with a color pattern stored as pattern data in off-screen
memory. The screen has a resolution of 1024×768, and the graphics system has been set to a color depth of 8 bits per
pixel.
R
(0, 0)
(0, 767)
128, 128
Rectangular
Area to be Filled
(Destination)
128, 191 191, 191
Note: Drawing is not to scale
191, 128
Scan Lines 128 Through 191
(1023, 0)
(1023, 767)
63
128, 128
(191, 128)
(128, 191)
(191, 191)
0
20080h
20088h
20090h
20098h
200A0h
200A8h
200B0h
200B8h
2FC80h
2FC88h
2FC90h
2FC98h
2FCA0h
2FCA8h
2FCB0h
2FCB8h
On
128th
Scan
Line
On
191th
Scan
Line
b_blt20.vs
Figure 22. On-screen destination for example pattern fill BLT
As shown in the preceding figure, the upper left-hand corner of the rectangular area to be filled is at coordinates (128,
128), while its lower right-hand corner is at coordinates (191, 191). These coordinates define a rectangle covering 64
scan lines, each line of which is 64 pixels in length (i.e., an array of 64×64 pixels). Assuming that the pixel at
coordinates (0, 0) corresponds to the byte at address 00h in the frame buffer memory, the pixel at (128, 128) corresponds
to the byte at address 20080h.
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0
100000h
100008h
100010h
100018h
100020h
100028h
100030h
100038h
(0, 7)(7, 7)
b_blt22.vs
R
(0, 0)
(0, 7)
Pattern Data
63
(7, 0)
(7, 7)
Figure 23. Pattern data for example pattern fill BLT
As shown in the preceding figure, the pattern data occupies 64 bytes, starting at address 100000h. As always, the pattern
data represents an 8×8 array of pixels.
The BLT command packet is used to select the features to be used in this BLT operation, so it must be programmed
carefully. The vertical alignment field should be set to 0, in order to select the top horizontal row of the pattern as the
starting row used in drawing the pattern, starting with the top scan line covered by the destination. The pattern data is in
color with a color depth of 8 bits per pixel, so dynamic color enable should be asserted with the dynamic color depth
field set to 0. Since this BLT operation does not use per-pixel write-masking (i.e., the destination transparency mode),
this field should be set to 0. Finally, the raster operation field should be programmed with the 8-bit value F0h, in order to
select the bitwise logical operation in which a simple copy of the pattern data to the destination takes place. Selecting
this bitwise operation, in which no source data is used as an input, causes the BLT engine to automatically forego either
reading source data from the frame buffer or waiting for the host CPU to provide it.
The Destination Pitch Register must be programmed with number of bytes in the interva l from the start of one scan line’s
worth of destination data to the next. Since the color depth is 8 bits per pixel and the horizontal resolution of the display
is 1024, the value to be programmed into these bits is 400h, which is equal to the decimal value 1024.
Bits [31:3] of the Pattern Address Register must be programmed with the address of the pattern data.
Similarly, bits [31:0] of the Destination Address Register must be programmed with the byte address at the destination
that will be written to first. In this case, the address is 20080h, which corresponds to the byte representing the pixel at
coordinates (128, 128).
This BLT operation does not use the values in the Source Address Register or the Source Expansion Background or
Foreground Color Register s.
The Destination Width and Height Registers must be programmed with values that tell the BLT engine the 64×64 pixel
size of the destination location. The height should be set to carry the value 40h, indicating that the destination location
covers 64 scan lines. The width should be set to carry the value 40h, indicating that each scan line’s worth of destination
data occupies 64 bytes. All of this information is written to the ring buffer using the PAT_BLT command packet.
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(0, 0)
(0, 767)
128, 128
128, 191 191, 191
Note: Drawing is not to scale
191, 128
Scan Lines 128 Through 191
(1023, 0)
(1023, 767)
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128, 128
(191, 128)
(128, 191)
(191, 191)
0
20080h
20088h
20090h
20098h
200A0h
200A8h
200B0h
200B8h
2FC80h
2FC88h
2FC90h
2FC98h
2FCA0h
2FCA8h
2FCB0h
2FCB8h
On
128th
Scan
Line
On
191th
Scan
Line
b_blt21.vs
Figure 24. Results of example pattern fill BLT
The figure above shows the end result of performing this BLT operation. The 8×8 pattern has been repeatedly copied
(“tiled”) into the entire 64×64 area at the destination.
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6.3.2 Drawing Characters Using a Font Stored in System Memory
In this example BLT operation, a lowercase “f” is to be drawn in black on a display with a gray background. The
resolution of the display is 1024×768, and the graphics system has been set to a color depth of 8 bits per pixel.
(0, 0)
Note: Drawing is not to scale
Scan Lines 128 Through 135
128, 128
Destination
(135, 135)
(0, 767)
(1023, 0)
(1023, 767)
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128, 128
135, 135
0
20080h
128th Scan Line
20480h
129th Scan Line
20880h
130th Scan Line
20C80h
131th Scan Line
21080h
132nd Scan Line
21480h
133rd Scan Line
21880h
134th Scan Line
21C80h
135th Scan Line
b_blt12.vsd
Figure 25. On-screen destination for example character drawing BLT
The preceding figure shows the display on which this “f” is to be dr awn. As shown in this figure, the entire display has
been filled with gray. The “f” is to be drawn in an 8×8 region on the display, with the upper-left-hand corner at the
coordinates (128, 128).
Source Data
Pixel (0, 0)
Pixel (0, 7)
Pixel (7, 0)
063 57 56 48 47 40 39 24 2332 31 16 15 8 7
00000000 00010000 00010000 00111100 00010000 00010000 00001100 00000000
(0, 7) (7, 7) (7, 0) (0, 0)
Pixel (7, 7)
b_blt13.vs
Figure 26. Source data in system memory for example character drawing BLT
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The figure above shows both the 8×8 pattern making up the “f” and how it is represented somewhere in the host’s system
memory. (The actual address in system memory is not important.) The “f” is represented in system memory by a block of
monochrome graphics data that occupies 8 bytes. Each byte carries the 8 bits needed to represent the 8 pixels in each
scan line’s worth of this graphics data. This type of pattern often is used to store character fonts in system memory.
During this BLT operation, the host CPU will read this representation of “f” from system memory and will write it to the
BLT engine, by performing memory writes to the ring buffer as an immediate monochrome BLT operand following the
BLT_TEXT command. The BLT engine will receive this data through the command stream and will use it as the source
data for this BLT operation. The BLT engine will be set to the same color depth as the graphics system (in this case, 8
bits per pixel). Since the source data in this BLT operation is monochrome, color expansion must be used to convert it to
an 8-bpp color depth. To ensure that the gray background behind this “f” is preserved, per-pixel write-masking will be
performed, using the monochrome source data as the pixel mask.
The BLT Setup and Text command packets are used to select the features to be used in this BLT operation. Only the
fields required by these two command packets must be programmed carefully. The BLT engine ignores all other registers
and fields. The source select field must be set to 1, in order to indicate that the source data is provided by the host CPU
through the IMMEDIATE_BLT command packet. Finally, the raster operation field should be programmed with the 8bit value CCh, in order to select the bitwise logical operation that simply copies t he source d ata to the destination.
Selecting this bitwise operation, in which no pattern data is used as an input, causes the BLT engine to automatically
forego re ading pattern data from the frame buffer.
The Setup Pattern/Source Expansion Foreground Color Register is used to specify the color with which the “f” will be
drawn. There is no source address. All scan lines of the glyph are bit-packed, and the clipping is controlled by the
ClipRect registers from the SETUP_BLT command and the Destination Y1, Y2, X1, and X2 registers in the TEXT_BLT
command. Only the pixels that are within the clip rectangle are written to the destination surface.
R
The Destination Pitch Register must be programmed with a value equal to the number of bytes in the interval bet wee n
the first bytes of each adjacent scan line’s worth of destination data. Since the color depth is 8 bits per pixel and the
horizontal resolution of the display is 1024 pixels, the value to be programmed into these bits is 400h, which is equal to
the decimal value 1024. Since the source data used in this BLT operation is monochrome, the BLT engine will not use a
byte-oriented pitch value for the source data.
Since the source data is monochrome, color expansion is required to convert it to color with a color depth of 8 bits per
pixel. Since the Setup Pattern/Source Expansion Foreground Color Register is selected in order to specify the foreground
color of black to be used in drawing the “f”, this register must be programmed with the value for that color. With the
graphics system set for a color depth of 8 bits per pixel, the actual colors are specified in the RAMDAC palette, and the 8
bits stored in the frame buffer for each pixel actually specify the index used to select a color from that palette. This
example assumes that the color specified at index 00h in the palette is black, and therefore bits [7:0] of this register
should be set to 00h in order to select black as the foreground color. The BLT engine ignores bits [23:8] of this register
because the selected color depth is 8 bits per pixel. Even though the color expansion being performed on the source data
normally requires the specification of both the foreground and background colors, the value used to specify the
background color is not important in this example. Per-pixel write-masking is being performed with the monochrome
source data as the pixel mask, which means that none of the pixels in the source data converted to the background color
will ever be written to the destination. Since these pixels will never be seen, the value programmed into the
Pattern/Source Expansion Background Color Register in order to specify a background color is not important.
The Destination Width and Height Registers are not used. The Y1, Y2, X1, and X2 registers are programmed with values
that describe to the BLT engine the 8x8 pixel size of the destination location. T he Desti nation Y1 and Y2 address
registers must be programmed with the starting and ending scan line addresses of the destination data. These addresses
are specified as an offset from the start of the frame buffer of the scan line at the destination that will be written to first.
The destination X1 and X2 registers must be programmed with the starting and ending pixel offsets from the beginning
of the scan line.
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This BLT operation does not use the values in the Pattern Address Register, the Source Expansion Background Color
Register, or the Source Expansion Foreground Color Regi ster.
(0, 0)
Note: Drawing is not to scale
Scan Lines 128 Through 135
128, 128
(0, 767)
Figure 27. Results of example character-drawing BLT
Destination
135, 135
(1023, 0)
(1023, 767)
63
128, 128
135, 135
0
20080h
(128th Scan Line)
20480h
(129th Scan Line)
20880h
(130th Scan Line)
20C80h
(131th Scan Line)
21080h
(132nd Scan Line)
21480h
(133rd Scan Line)
21880h
(134th Scan Line)
21C80h
(135th Scan Line)
b_blt12.vsd
Figure 27 shows the end result of performing this BLT operation. Only the pixels that form part of the actual “f” have
been drawn in the 8×8 destination location on the display, leaving the other pixels with in t he de stination with their
original gray color.
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7. Initialization Registers
In order to function, all registers described in this section must be programmed for the Intel® 82180 chipset and family
products. The default states of these registers, with the exception of registers that deal with extended modes or
performance enhancements, will prevent the Intel 82180 chipset and family products from booting.
Note: The registers in this document are normally programmed by the video BIOS.
These registers also may be documented in other sections of this document.
7.1 Standard VG A Registers
All VGA registers are in standard locations and initialized by means of sta ndard procedures. This section will document
all nonstandard registers that are needed for initialization of the Intel 82180 chipset and family chipsets.
7.2 SMRAM Registers
7.2.1 SMRAM—System Management RAM Control Register (Device 0)
Address offset: 70h
Default value: 00h
Access: Read/Write
Size: 8 bits
The SMRAM register controls how accesses to compatible and extended SMRAM spaces are treated as well as how
much (if any) memory is “taken” from the system in order to support both SMRAM and graphics local memory needs.
76543210
Graphics Mode Select Upper SMM Select Lower SMM Select
SMM
Space
Locked
E_SMRA
M_ERR
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Bit Description
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7:6
5:4
3:2
1
0
Graphics Mode Select (GMS).
This field is used to enable/disable the internal graphics device and
select the amount of Main Memory that is “taken” to support the internal graphics device.
00 = Graphics device disabled, no memory “taken” (Device 1 is NOT accessible in this case.)
01 = Graphics device enabled, no memory “taken”
10 = Graphics device enabled, 512 KB of memory “taken”
11 = Graphics device enabled, 1 MB of memory “taken”
Note:
When the graphics device is disabled (00), the graphics device and all of its memory and I/O functions
are disabled, the clocks to this logic are turned off, memory accesses to the VGA range (A0000BFFFF) will be forwarded to the hub-link, and the graphics local memory space is NOT “taken” from
main memory. When this field is non-0, the GMCH graphics device and all of its memory and I/O
functions are enabled, all non-SMM memory accesses to the VGA range will be handled internally,
and the selected amount of graphics local memory space (0, 512K or 1M) is “taken” from the main
memory. Graphics memory is “taken” AFTER TSEG memory is “taken”.
Once D_LCK is set, these bits becomes Read Only.
GMCH does not support VGA on local memory. Software must not use the 01 mode for VGA.
Upper SMM Select (USMM).
This field is used to enable/disable the various SMM memory ranges
above 1 Meg. TSEG is a block of memory (“taken” from main memory at [TOM-Size] : [TOM]) that is
accessible only by the processor and only while operating in the SMM mode. HSEG is a remap of the
AB segment at FEEA0000 : FEEBFFFF. Both of these areas, when enabled, are usable as SMM RAM.
Non-SMM operations that use these address ranges are forwarded to the hub-link. HSEG is ONLY
enabled if LSMM = 00.
00 = TSEG and HSEG are both disabled.
01 = TSEG is disabled and HSEG is conditionally enabled.
10 = TSEG is enabled as 512 Kbytes and HSEG is conditionally enabled.
11 = TSEG is enabled as 1 Mbytes and HSEG is conditionally enabled.
Once D_LCK is set, these bits become Read Only.
Lower SMM Select (LSMM).
This field controls the definition of the A&B segment SMM space.
00 = AB segment disabled
01 = AB segment enabled as general system RAM
10 = AB segment enabled as SMM code RAM shadow. Only SMM code reads can access DRAM in the
AB segment. SMM data operations and all non-SMM operations either go to the internal graphics
device or are broadcast on the hub-link.
11 = AB segment enabled as SMM RAM. All SMM operations to the AB segment are serviced by
DRAM. All non-SMM operations either go to the internal graphics device or are broadcast on hublink.
When D_LCK is set, bit 3 becomes Read_Only and bit 2 is writeable ONLY if bit 3 is 1.
SMM Space Locked (D_LCK):
When D_LCK is set to 1, then D_LCK, GMS, USMM, and the mostsignificant bit of LSMM become Read Only. D_LCK can be set to 1 via a normal configuration space
write but can be cleared only by a reset. The combination of D_LCK and LSMM provides convenience
with security. The BIOS can use LSMM=01 to initialize SMM space and then use D_LCK to “lock down”
SMM space in the future, so that no application software (or the BIOS itself) can violate the integrity of
SMM space, even if the program has knowledge of the LSMM function. This bit also locks the DRP
register.
E_SMRAM_ERR (E_SMERR):
This bit is set when CPU accesses the defined memory ranges in
extended SMRAM (HSEG or TSEG) while not in SMM mode. It is software’s responsibility to clear this
bit. The software must write a 1 to this bit to clear it This bit is NOT set in the case of an explicit writeback operation.
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Initialization and Usage of “Taken” Memory
SMRAM Register bits 7:4 control the theft of memory from main memory space, for use as graphics local memory and
SMM TSEG memory. The blocks of memory selected by these fields are NOT accessible as general system RAM. When
bit 5 of the SMRAM register is 1, the TSEG segment of memory can ONLY be accessed by the CPU in the SMM mode.
(No other agent can access this memory.) Therefore, the BIOS should initialize this block of memory BEFORE setting
either bit 5 or bit 7 of the SMRAM register. The memory for TSEG is “taken” first, and then the graphics local memory
is “taken.” An example of this theft mechanism is as follows:
TOM = 64 Mbytes.
TSEG selected as 512 Kbytes in size.
Graphics local memory selected as 1 Mbyte in size.
General System RAM available in system = 62.5 Mbytes.
General system RAM range: 00000000h to 03E7FFFFh
TSEG address range: 03F80000h to 03FFFFFFh
TSEG “taken” from: 03F80000h to 03FFFFFFh
Graphics local memory “taken” from: 03E80000h to 03F7FFFFh
7.3 Graphics Controller Registers
The graphics controller registers are accessed via either I/O space or memory space. To access the registers, the VGA
Graphics Controller Index Register at I/O address 3CEh (or memory address 3CEh) is written with the index of the
desired register, and then the desired register is accessed through the data port for the graphics controller registers at I/O
address 3CFh (or memory address 3CFh).
7.3.1 GR10
I/O (and memory offset) address: 3CFh (Index=10h)
Default: 00h
Attributes: R/W
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Address Mapping
Reserved (0000)
4
Paging to
LM
3210
VGA
Buffer
/Memory
Packed
Mode
Enabling
Linear
Mapping
Page
Mapping
Map
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Bit Description
7:5 Reserved (000)
Page to Local Memory Enable:
4
Used only if GR10(0) = 1 {paging enabled} and (GR10(1) = 1 or GR10(2) = 1) {either packed mode or
linear mode is enabled) and GR10(3) = 0 {VGA buffer selected}.
0 = Page to VGA buffer
1 = Page to physical local memory
VGA Buffer/Memory Map Select.
3
0 = VGA buffer (default)
1 = Memory map
Packed Mode Enable.
2
0 = Address and data translation are bused register settings (default).
1 = Forced extended pack pixel address translation
In the page mapping mode, register GR06 selects the video memory address.
Linear Mapping (PCI).
1
0 = Disable (default)
1 = Enable
Page Mapping Enable.
0
local video memory) mode or all of local memory space through the [A0000:AFFFF] window (using bit 4 of
this register), which is a 64-KB page. An internal address is generated using GR11[6:0] as the address
line [22:16] extension to A[15:2].
0 = Disable (default)
1 = Enable
This mode allows the mapping of the VGA space allocated in main memory (non-
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GR10
[2]
00 0Std VGA
GR10
[1]
GR10
[0]
Note 1 Address Range (see Note 2)
A0000-AFFFF Range
B0, B8 Ranges
(No GTT)
VGA contro ller, no paging VGA contr oller, no paging
(No GTT)
xlations
0 0 1 Paging and
VGA controller, paged by GR11 VGA controller, no paging
VGA xlation
01 0
No paging, no
Bypass VGA, no paging Bypass VGA, no paging
VGA xlatio ns
0 1 1 Paging, no
Bypass VGA, paged by GR11 Bypass VGA, no paging
VGA xlatio ns
10 0
No paging, no
Bypass VGA, no paging Bypass VGA, no paging
VGA xlatio ns
1 0 1 Paging, no
Bypass VGA, paged by GR11 Bypass VGA, no paging
VGA xlatio ns
1 1 0 No paging, no
Bypass VGA, no paging Bypass VGA, no paging
VGA xlatio ns
1 1 1 Paging, no
Bypass VGA paged by GR11 Bypass VGA, no paging
VGA xlatio ns
Notes:
GR10[2:0]: 001 should not be used for paging, because all the VGA registers need to be setup correctly. An access
thru A0000 range is paged by GR11. Note that prefetch refers to the cache line size access to GM vs. without
prefetch (i.e., QW).
VGA Address Range is selected by GR06. Graphics range is selected through the graphics base address register in
the configuration space. Access to the VGA range does not require a translation table. VGA range paging
allows access to all of local memory, if it is set up with bit 4 of this register, or to all of the memory taken from
the VGA main memory space. Access to the graphics range requires GTT to be set up and will result in a
prefetch unless prefetch is disabled. Access to VGA range will not result in a prefetch.
The BIOS should access local memory through the "back door" mechanism, by setting gr10 = 17h, gr11 = 0, and gr6
= 0, only when local memory has been enabled (MMADR+3000h). Otherwise, the system will hang in a snoop
stall forever.
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7.3.2 GR11
Page Selector
I/O (and memory offset) address: 3CFh (Index=11h)
Default : 00h
Attributes: R/W
Bit Description
7:0
Page Select.
page mapping is enabled (GR10[0]=1). In addition, this register is used for page selection of memorymapped register addresses.
Selects a 64-KB window within VGA space in NLVM mode or all of local memory when
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7.4 CRT Controller Register
The CRT controller registers are accessed by writing the index of the desired register into the CRT Controller Index
Register at I/O address 3B4h or 3D4h, depending on whether the graphics system is configured for MDA or CGA
emulation. The desired register then is accessed through the data port for the CRT controller registers located at I/O
address 3B5h or 3D5h, again depending upon the choice of MDA or CGA emulation, as per MSR[0]. For memorymapped accesses, the Index register is at 3B4h (MDA mode) or 3D3h (CGA mode), and the data port is accessed at
3B5h (MDA mode) or 3D5h (CGA mode).
Notes:
Register CR80 enables / disables the CRTC extensions.
Group 0 Protection: In the original IBM VGA, CR[0:7] could write-protected by means of CR11[7]. In the BIOS
code, this write protection is set following each mode change. Other protection groups are not currently used and
will not by used in the future by the BIOS or by drivers. They are the result of an industry fad some years ago,
that attempted to write-protect other groups of registers. However, all such schemes were chip specific. Only
IBM-compatible write protection (Group 0 protection) is supported.
7.4.1 CR30
Extended Vertical Total Register
I/O (and memory offset) address: 3B5h/3D5h (index=30h)
Default: 00h
Attributes: Read/Write
7430
Reserved (0000) Vertical total bits 11:8
Bit Description
7:4
3:0
Reserved.
Vertical Total Bits [11:8].
scan lines. This includes the scan lines both inside and outside of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical total is
specified with a 10-bit value. The 8 least-significant bits of this value are supplied by bits [7:0] of the
Vertical Total Register (CR06), and the 2 most-significant bits are supplied by bits 5 and 0 of the Overflow
Register (CR07). In standard VGA modes, these 4 bits of this register are not used.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical total is specified
with a 12-bit value. The 8 least-significant bits of this value are supplied by bits [7:0] of the Vertical Total
Register (CR06), and the 4 most-significant bits are supplied by these 4 bits of this register.
This 10-bit or 12-bit value should be programmed to be equal to the total number of scan lines, minus 2.
Read as 0s. This field must be 0s when this register is written.
The vertical total is a 10-bit or 12-bit value that specifies the total number of
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7.4.2 CR31
Extended Vertical Display End Register
I/O (and memory offset) address: 3B5h/3D5h (index=31h)
Default: 00h
Attributes: Read/Write
7430
Reserved (0000) Vertical Display End Bits 11:8
Bit Description
7:4
3:0
Reserved.
Vertical Display End Bits [11:8].
the number of the last scan line within the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical display
enable end is specified with a 10-bit value. The 8 least-significant bits of this value are supplied by bits
[7:0] of the Vertical Display Enable End Register (CR12), and the 2 most-significant bits are supplied by
bits 6 and 1 of the Overflow Register (CR07). In standard VGA modes, these 4 bits of this register are not
used.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display enable
end is specified with a 12-bit value. The 8 least-significant bits of this value are supplied by bits [7:0] of the
Vertical Display Enable End Register (CR12), and the 4 most-significant bits are supplied by these 4 bits of
this register.
This 10-bit or 12-bit value should be programmed to be equal to the number of the last scan line within in
the active display area. Since the active display area always starts on the 0th scan line, this number should
be equal to the total number of scan lines within the active display area, minus 1.
Read as 0s. This field must be 0s when this register is written.
The vertical display enable end is a 10-bit or 12-bit value that specifies
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7.4.3 CR32
Extended Vertical Sync Start Register
I/O (and memory offset) address: 3B5h/3D5h (index=32h)
Default: 00h
Attributes: Read/Write
7430
Reserved (0000) Vertical Sync Start Bits 11:8
Bit Description
7:4
3:0
Reserved.
Vertical Sync Start Bits [11:8].
beginning of the vertical sync pulse relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical sync start is
specified with a 10-bit value. The 8 least-significant bits of this value are supplied by bits [7:0] of the
Vertical Sync Start Register (CR10), and the 2 most-significant bits are supplied by bits 7 and 2 of the
Overflow Register (CR07). In standard VGA modes, these 4 bits of this register are not used.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display end is
specified with a 12-bit value. The 8 least-significant bits of this value are supplied by bits [7:0] of the
Vertical Sync Start Register (CR10), and the 4 most-significant bits are supplied by these 4 bits of this
register.
This 10-bit or 12-bit value should be programmed to be equal to the number of scan lines from the
beginning of the active display area to the start of the vertical sync pulse. Since the active display area
always starts on the 0th scan line, this number should be equal to the number of the scan line on which the
vertical sync pulse begins.
Read as 0s. This field must be 0s when this register is written.
The vertical sync start is a 10-bit or 12-bit value that specifies the
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7.4.4 CR33
Extended Vertical Blanking Start Register
I/O (and memory offset) address: 3B5h/3D5h (index=33h)
Default: 00h
Attributes: Read/Write
7430
Reserved (0000) Vertical Blanking Start Bits 11:8
Bit Description
7:4
3:0
Reserved.
Vertical Blanking Start Bits [11:8].
beginning of the vertical blanking period relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical blanking
start is specified with a 10-bit value. The 8 least-significant bits of this value are supplied by bits [7:0] of the
Vertical Blanking Start Register (CR15), and the most-significant and second-most-significant bits are
supplied by bit 5 of the Maximum Scan Line Register (CR09) and bit 3 of the Overflow Register (CR07),
respectively. In standard VGA modes, these four bits are not used.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical blanking start is
specified with a 12-bit value. The 8 least-significant bits of this value are supplied by bits {7:0] of the
Vertical Blanking Start Register (CR15), and the 4 most-significant bits are supplied by these 4 bits of this
register.
This 10-bit or 12-bit value should be programmed to be equal to the number of scan lines from the
beginning of the active display area to the beginning of the blanking period. Since the active display area
always starts on the 0th scan line, this number should be equal to the number of the scan line on which the
vertical blanking period begins.
Read as 0s. This field must be 0s when this register is written.
The vertical blanking start is a 10-bit or 12-bit value that specifies the
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7.4.5 CR35
Extended Horizontal Total Time Register
I/O (and memory offset) address: 3B5h/3D5h (index=35h)
Default: 00h
Attributes: Read/Write
7 10
Reserved (0000000) Ext Horiz
Bit Description
7:1
7.4.6 CR39
Reserved.
Extended Horizontal Total (MSB that extends CR00).
0
When this register is written to, these bits should be set to 0.
Extended Horizontal Blank Time Register
I/O (and memory offset) address: 3B5h/3D5h (index=39h)
Default: 00h
Attributes: Read/Write
7 10
Reserved (0000000) Ext Horiz
Total
Total
Bit Description
7:1
Reserved.
Extended Horizontal Total (MSB that extends CR5[7], CR3[4:0]).
0
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7.4.7 CR40
Extended Start Address Register
I/O (and memory offset) address: 3B5h/3D5h (index=40h)
Default: 00h
Attributes: Read/Write
765 0
Start Addr
Enable
Bit Description
Extended Mode Start Address Enable.
7
Control Register (CR80) is set to 1, in order to signal the graphics controller to update the start address. In
extended modes, the start address is specified with a 30-bit value. These 30 bits, which are provided by
the Start Address Low Register (CR0D), the Start Address High Register (CR0C), the Extended Start
Address High Register (CR42), and bits [5:0] of this register, are double-buffered and synchronized to
VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always
have a smooth or instantaneous appearance. To change the start address in extended modes, all three
registers must be set for the new value, and then this bit of this register must be set to 1. Only if this is
done will the graphics controller update the start address on the next VSYNC. After this update has been
performed, the graphics controller will set bit 7 of this register back to 0.
Reserved.
6
5:0
Start Address Bits [23:18].
from the beginning of the frame buffer or a 32-bit buffer address at which begins the data t o be shown in the
active display area. (Default: 0)
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the start address is
specified with a 16-bit value. The eight bits of the Start Address High Register (CR0C) provide the eight
most-significant bits of this value, while the eight bits of the Start Address Low Register (CR0D) provide
the eight least-significant bits.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the start address is specified
with a 32-bit value. Bits 31:24 of this value are provided by the Extended Start Address High Register
(CR42). Bits 23:18 of this value are provided by bits 5:0 of this register. Bits 17:10 of this value are
provided by the Start Address High Register (CR0C). Bits 9:2 of this value are provided by the Start
Address Low Register (CR0D). Bits 1:0 of this value are always 0 and therefore are not provided. Note
that, in the extended modes, these 32 bits from these four registers are double-buffered and synchronized
to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address
always have a smooth or instantaneous appearance. To change the start address in extended modes, all
four registers must be set for the new value, and then bit 7 of this register must be set to 1. Only if this is
done will the graphics controller update the start address on the next VSYNC. After this update has been
performed, the graphics controller will set bit 7 of this register back to 0.
Reserved
Start Address Bits 23:18
(0)
This bit is used only in extended modes, where bit 0 of the I/O
Read as 0s. This field must be 0s when this register is written.
This start address is a 16-bit value that specifies the memory address off set
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7.4.8 CR41
Extended Offset Register
I/O (and memory offset) address: 3B5h/3D5h (index=41h)
Default: 00h
Attributes: Read/Write
7430
Reserved (0000) Offset Bits 11:8
Bit Description
7:4
3:0
Reserved.
Offset Bits [11:8].
buffer memory occupied by each horizontal row of characters. Whether this value is interpreted as the
number of words or dwords is determined by the settings of the bits in the Clocking Mode Register (SR01).
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the offset is described
with an 8-bit value, all bits of which are provided by the Offset Register (CR13).
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the offset is described with a
12-bit value. The four most-significant bits of this value are provided by bits [3:0] of this register, and the
eight least-significant bits are provided by the Offset Register (CR13).
This 8-bit or 12-bit value should be programmed to be equal to either the number of words or dwords
(depending on the setting of the bits in the Clocking Mode Register, SR01) of frame buffer memory that is
occupied by each horizontal row of characters.
7.4.9 CR42
Read as 0s. This field must be 0s when this register is written.
The offset is an 8-bit or 12-bit value describing the number of words or dwords of frame
Extended Start Address High Register
I/O (and memory offset) address: 3B5h/3D5h (index=42h)
Default: 00h
Attributes: Read/Write
Bit Description
7:0
Start Address High Bits [31:24].
begins the data to be shown in the active display area. (Default: 0)
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the start address is
specified with a 16-bit value. The eight bits of the Start Address High Register (CR0C) provide the eight
most-significant bits of this value, while the eight bits of the CR0D register provide the eight leastsignificant bits.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the start address is specified
as a 32-bit value. Bits [31:24] of this value are provided by this register. Bits [23:18] of this value are
provided by bits [5:0] of the Extended Start Address Register (CR40). Bits [17:10] of this value are
provided by the Start Address High Register (CR0C). Bits [9:2] of this value are provided by the Start
Address Low Register (CR0D). Bits [1:0] of this value are always 0 and therefore are not provided. It
should be further noted that, in extended modes, the 30 bits from these four registers are double-buffered
and synchronized to VSYNC, in order to ensure that changes occurring on the screen as a result of
changes in the start address always have a smooth or instantaneous appearance. To change the start
address in extended modes, all four registers must be set for the new value, and then bit 7 of the Extended
Start Address Register (CR40) must be set to 1. Only then will the graphics controller update the start
address on the next VSYNC. When the update is done, the graphics controller sets bit 7 of the Extended
Start Address Register (CR40) back to 0.
This register provides bits [31:24] of the 32-bit buffer address at which
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Intel® 810 Chipset Family PRM
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7.4.10 CR70
Interlace Control Register
I/O (and memory offset) address: 3B5h/3D5h (index=70h)
Default: 00h
Attributes: Read/Write
76 0
Interlace
CRT Half-Line Value
Enable
Bit Description
Interlace Enable.
7
0 = Selects non-interlaced CRT output (default).
1 = Selects interlaced CRT output.
6:0
7.4.11 CR80
CRT Half-Line Value.
the position along the length of a scan line at which the half-line vertical sync pulse occurs for the odd
frame. This half-line vertical sync pulse begins at a position between two horizontal sync pulses on the last
scan line, rather than at a position coincident with the beginning of a horizontal sync pulse at the end of a
scan line.
I/O Control
When interlaced CRT output has been selected, the value in this register specifies
I/O (and memory offset) address: 3B5h/3D5h(index 80h)
Default: 00h
Attributes: Read/Write
7 21 0
Reserved (000000) Attr Cntl
Ext Enbl
CRT Cntl
Int Enbl
Bit Description
7:2
Reserved.
Attribute Controller Extensions Enable.
1
index and data at 3C0h (strict VGA mode), or whether they are accessed with 3c0h as the index and with
3C1h as data. It is possible that the BIOS software or driver software might not use the non-VGA mode.
Either method should work, but it must be the method the software is using.
0 = Disable (i.e., strictly VGA compatible mode) (default)
1 = Enable attribute controller extensions
Index and Data of the Attribute Controller registers are accessible at 3C0h in standard VGA. When the
Attribute Controller Extensions are enabled, the index and data are accessible at addresses 3C0h and
3C1h, respectively.
CRT Controller Interpretation Enable.
0
beyond. See CR06, CR07, CR09, CR0C, CR0D, CR10, CR12, CR13, CR15, CR30, CR32, CR33, CR40,
CR41, and CR42.
0 = Registers have strict VGA interpretation (default).
1 = Registers have extended VGA Interpretation (i.e., access to 4-G space).
Controls whether the attribute registers are accessed with both
This bit modifies responses/functionality to/of registers CR30 and
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7.4.12 CR82
Blink Rate Control
I/O (and memory offset) address: 3B5h/3D5h(index 82h)
Default: 88h is the VGA default because it is more visually appealing (but the standard
VGA default is 83h).
Attributes Read/Write
The H/W default for this register does not match the VGA compatibility requirements. The BI OS must make sure to set
this register to correct value.
765 0
Character Blink Duty
VSync Blink Rate
Cycle
Bit Description
7:6
5:0
Character Blink Duty Cycle.
00 = 50% duty cycle.
01 = 25% duty cycle
10 = 50% duty cycle (power-on default)
VSync Blink Rate.
programmed value must be the (actual value/2) - 1. (Default: 3)
Controls the cursor blink rate in terms of the number of vsyncs, as follows: The
(Character blink also is known as attribute blink.)
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Intel® 810 Chipset Family PRM
7.5 Display Control Registers
7.5.1 FW_BLC—FIFO Watermark and Burst Length Control
Address Offset : 020D8h
Default value: 22 31 73 17h
Access: Read/Write
Size: 32 bits
These control values only apply to hi-res modes of o peration. VG A modes ignore the settings of these registers in favor
of fixed values.
For the VGA text mode, character buffer fetches are performed without regard to the space available in the FIFO (since
this data is stored in the character buffer, not the FIFO). Character buffer fetches are performed as a single request of 8
qwords. Font data is fetched one qword at a time, and it will begin when the FIFO has room for 8 character font qwords.
VGA graphics modes will perform requests one at a time, as long as there is room for 1 qword in the FIFO.
Note 1: FIFOs refer to ALL FIFOs in the DSI data path. (That is, the total FIFO space available is the sum of the DSI
FIFO depth and the display engine FIFO depth.) Currently, this depth is 48 qwords.
Note 2: The H/W default is an illegal value: These quantities should never be pr ogrammed to zeros.
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Note 3: The hardware depends on these registers being set properly, since it is possible to set the request length and
watermarks to states that would cause the overflow of the sync FIFO. For example, assume that a watermark is
set to 33 QW and the request length is set to 32 QWs. After the first two requests have been completed, 64 QWs
will have been written into the sync FIFO. During this time, only 16 QWs will be drained out of the FIFO in
order to be written to the display engine FIFO. Since the sync FIFO in the DSI is only 32QWs deep, this will
result in (64-16-32) = 16 QW overflow of the FIFO.
31 28 27 24
Overlay Delay Timer1 Overlay Delay Timer0
23 22 20 19 18 17 12 11 10 8
Reserved
MM Dply Burst
Reserved
Length
765 0
MM Display FIFO
Watermark
Reserved
LM Dply Burst
Length
Reserved LM Dply FIFO Watermark
Bit Description
31:28
27:24
23
Overlay Delay Timer1
this register is multiplied by 16 to determine the wait state clock count.
Overlay Delay Timer0
except between sets of YUVY. The value in this register is multiplied by 16 to determine the wait state
clock count.
Reserved
is used to insert wait states between sets of YUVY requests to MM. The value in
is used to insert wait states between any two overlay streamer requests to MM,
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Bit Description
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Intel
810 Chipset Family PRM
22:20
19:18
17:12
11
10:8
7:6
5:0
MM Display Burst Length :
Size in qwords of individual requests issued to memory. Use multiples of 16
QWs for tiled memory.
000 = 8 Qws N/A if trickle feed is on.
001 = 16 Qws
010 = 24 Qws
011 = 32 Qws
100 = 40 Qws
101 = 48 Qws
110 = 56 Qws
111 = 64 QWs
Reserved
MM Display FIFO Watermark :
Number of qwords stored in FIFOs, below which the DSI will generate
requests to LMI. (The value must be less than 32 and should be as recommended in the high-priority
bandwidth analysis spreadsheet.)
Reserved
LM Display Burst Length :
Size in qwords of individual requests issued to memory. Use multiples of 16
QWs for tiled memory.
000 = 8 Qws N/A if trickle feed is on.
001 = 16 Qws
010 = 24 Qws
011 = 32 Qws
100 = 40 Qws
101 = 48 Qws
110 = 56 Qws
111 = 64 QWs.
Reserved
LM Display FIFO Watermark :
Number of qwords stored in FIFOs, below which the DSI will generate
requests to LMI. (The value must be less than 32 and should be as recommended in the high-priority
bandwidth analysis spreadsheet.)
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Intel® 810 Chipset Family PRM
7.6 I/O Control Registers
7.6.1 HVSYNC—HSYNC/VSYNC Control Register
Address offset: 05000h
Default value: 00000000h
Size: 32 bits
Attribute: R/W
Bits 19:16 are for DPMS and DDC sync select.
DPMS MODE HSYNC/VSYNC Control[19:16]
Power On 0000 (i.e., pulse H and V)
Standby 0010 (i.e., pulse V)
Suspend 1000 (i.e., pulse H)
Power Off 1010 (no pulse on H & V)
31 20 19 18 17 16
Reserved VSYNC
Control
VSYNC
Data
HSYNC
Control
R
HSYNC
Data
15 10
Reserved HSYNC/
VSYNC
En
Bit Description
31:20
19
Reserved.
VSYNC Control.
Bit 19 (VSYNC Control) and bit 18 (VSYNC Data) are used by the BIOS to
take over the sync during DDC1 communication during POST. The BIOS can force the
VSYNC data at the same time as VSYNC control enables this signal as an output, so that the
VSYNC pulse occurs on every write by the BIOS. This is done to speed up some very slow
.
will go out to VSYNC pin.
will go out to HSYNC pin.
Module PowerDown 0
18
17
16
15:1
0
DDC communications
0 = Normal VSYNC output
1 = Contents of
VSYNC Data
VSYNC Data
HSYNC Control
0 = Normal HSYNC output
1 = Contents of
HSYNC Data
HSYNC Data.
Reserved
HSYNC/VSYNC Enable.
0 = HSync and Vsync are deactivated when the internal DAC is disabled. (Default)
1 = HSync and VSync remain active when the internal DAC is disabled via the
Register
.
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7.7 GPIO Registers
®
Intel
810 Chipset Family PRM
7.7.1 GPIOA
General-Purpose I/O Control Register A
Address offset : 05010h
Default value : 00h, 00h, 000U0000b, 000U0000b
Access : Read/Write
Size : 32 bits
This register controls the general-purpose I/O pins GPIO0 (DDCSCL pin) and GPIO1 (DDCSDA pin). These two pins
are specifically used to create a Display Data Channel (DDC) serial bus. GPIO0 = DDC Clock (DDCSCL pin) and
GPIO1 = DDC Data (DDCSDA pin). Refer to the Cspec for a description of the pin operation.
31 16
Reserved
15 13 12 11 10 9 8
Reserved GPIO1
data in
GPIO1
data value
GPIO1
data mask
GPIO1
direction
value
7 543210
Reserved GPIO0
data in
GPIO0
data value
GPIO0
data mask
GPIO0
direction
value
GPIO1
direction
mask
GPIO0
direction
mask
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Intel® 810 Chipset Family PRM
Bit Description
R
31:16
15:13
12
11
10
9
8
7:5
4
3
2
1
0
Reserved
Reserved
GPIO1 Data In (RO):
GPIO1 Data Value (R/W):
written into the register if
data value actually is written to this register and the
This value is sampled on the GPIO1 pin as an input.
This value should be placed on the GPIO1 pin as an output. This value only is
GPIO1 DATA MASK
also is asserted. The value will appear on the pin if this
GPIO1 DIRECTION VALUE
will configure the pin as an output.
GPIO1 Data Mask (R/W):
This is a mask bit to determine whether the
be written into the register.
0 = Do NOT write GPIO1 Data Value bit (default).
1 = Write GPIO1 Data Value bit.
GPIO1 Direction Value (R/W):
This value only is written into the register if
This value should be used to define the output enable of the GPIO1 pin.
GPIO1 DIRECTION MASK
will appear on the pin is defined by what is in the register for the
0 = Pin is configured as an input (default).
1 = Pin is configured as an output.
GPIO1 Direction Mask (R/W):
VALUE
bit should be written into the register.
This mask bit is used to determine whether the
0 = Do NOT write GPIO1 Direction Value bit (default).
1 = Write GPIO1 Direction Value bit.
Reserved
GPIO0 Data In (RO):
GPIO0 Data Value (R/W):
written into the register if
data value actually is written to this register and the
This value is sampled on the GPIO0 pin as an input.
This value should be placed on the GPIO0 pin as an output. This value only is
GPIO0 DATA MASK
also is asserted. The value will appear on the pin if this
GPIO0 DIRECTION VALUE
will configure the pin as an output.
GPIO0 Data Mask (R/W):
This mask bit is used to determine whether the
should be written into the register.
0 = Do NOT write GPIO0 Data Value bit (default).
1 = Write GPIO0 Data Value bit.
GPIO0 Direction Value (R/W):
This value only is written into the register if
This value should be used to define the output enable of the GPIO0 pin.
GPIO0 DIRECTION MASK
will appear on the pin is defined by what is in the register for the
0 = Pin is configured as an input (default).
1 = Pin is configured as an output.
GPIO0 Direction Mask (R/W):
VALUE
bit should be written into the register.
This mask bit is used to determine whether the
0 = Do NOT write GPIO0 Direction Value bit (default).
1 = Write GPIO0 Direction Value bit.
contains a value that
GPIO1 DATA VALUE
also is asserted. The value that
GPIO1 DATA VALUE
bit.
GPIO DIRECTION
contains a value that
GPIO0 DATA VALUE
also is asserted. The value that
GPIO0 DATA VALUE
bit.
GPIO DIRECTION
bit should
bit
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7.7.2 GPIOB
General-Purpose I/O Control Register B
Address offset : 05014h
Default value : 00h, 00h, 000U0000b, 000U0000b
Access : Read/Write
Size : 32 bit
This register controls general-purpose I/O pins GPIO2 (LTVCL pin) and GPIO3 (LTVDA pin). These two pins are used
specifically to create an I
2
C serial bus interface. GPIO2 = I2C clock (LTVCL pin) and GPIO3 = I2C data (LTVDA pin).
Refer to the Cspec for a description of the pin operation.
31 16
Reserved
15 13 12 11 10 9 8
Reserved GPIO3
Data In
GPIO3
Data value
GPIO3
Data mask
GPIO3
Direction
value
7 543210
Reserved GPIO2
Data In
GPIO2
Data value
GPIO2
Data mask
GPIO2
Direction
value
GPIO3
Direction
Mask
GPIO2
Direction
Mask
Bit Description
31:16
15:13
12
11
10
9
Reserved
Reserved
GPIO3 Data In (RO):
GPIO3 Data Value (R/W):
written into the register if
data value is actually written to this register and the
will configure the pin as an output.
GPIO3 Data Mask (R/W):
be written into the register.
0 = Do NOT write GPIO3 Data Value bit (default).
1 = Write GPIO3 Data Value bit.
GPIO3 Direction Value (R/W):
This value only is written into the register if
will appear on the pin is defined by what is in the register for the
0 = Pin is configured as an input (default).
1 = Pin is configured as an output.
This value is sampled on the GPIO3 pin as an input.
This value should be placed on the GPIO3 pin as an output. This value only is
GPIO3 DATA MASK
This is a mask bit to determine whether the
This value should be used to define the output enable of the GPIO3 pin.
is also asserted. The value will appear on the pin if this
GPIO3 DIRECTION VALUE
GPIO3 DIRECTION MASK
contains a value that
GPIO3 DATA VALUE
also is asserted. The value that
GPIO3 DATA VALUE
bit.
bit should
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Intel® 810 Chipset Family PRM
Bit Description
R
8
7:5
4
3
2
1
0
GPIO3 Direction Mask (R/W):
VALUE
bit should be written into the register.
This mask bit is used to determine whether the
0 = Do NOT write GPIO3 Direction Value bit (default).
1 = Write GPIO3 Direction Value bit.
Reserved
GPIO2 Data In (RO):
GPIO2 Data Value (R/W):
written into the register if
data value is actually written to this register and the
This value is sampled on the GPIO2 pin as an input.
This value should be placed on the GPIO2 pin as an output. This value only is
GPIO2 DATA MASK
also is asserted. The value will appear on the pin if this
GPIO2 DIRECTION VALUE
will configure the pin as an output.
GPIO2 Data Mask (R/W):
This mask bit is used to determine whether the
should be written into the register.
0 = Do NOT write GPIO2 Data Value bit (default).
1 = Write GPIO2 Data Value bit.
GPIO2 Direction Value (R/W):
This value only is written into the register if
This value should be used to define the output enable of the GPIO2 pin.
GPIO2 DIRECTION MASK
will appear on the pin is defined by what is in the register for the
0 = Pin is configured as an input (default).
1 = Pin is configured as an output.
GPIO2 Direction Mask (R/W):
This mask is used to determine whether the
bit should be written into the register.
0 = Do NOT write GPIO2 Direction Value bit (default).
1 = Write GPIO2 Direction Value bit.
GPIO DIRECTION
contains a value that
GPIO2 DATA VALUE
also is asserted. The value that
GPIO2 DATA VALUE
bit.
GPIO DIRECTION VALUE
bit
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7.8 Clock Control Registers
The clock control registers are accessed by writing to the memory-mapped address offset.
The Intel 82810 Chipset has 3 PLLs for generating all the clocks. The host PLL generates the host clock, whose
frequency is controlled by an external strap. In addition, the host PLL generates the system and local memory core clock
and the graphics core clock. The hub PLL generates the clock for the hub-link unit. The display PLL generates the
display or LCD clock.
The display clock can be controlled by three blocks of registers: DCLK0, DCLK1, and DCLK2. Each display clock has
its own Display Clock i Divisor registers for M, N, and a byte of the Display & LCD Clock Divisor Select Register,
within which are P (divisor) values and which can be programmed independently. DCLK0 and DCLK1 normally are
programmed to 25.175 MHz and 28.322 MHz, respectively (VGA-compatible clocks). DCLK2 is used for non-VGA
modes.
The Display Clock i Divisor register and the appropriate byte of the Display & LCD Clock Divisor Select Register
are programmed with the loop parameters to be loaded into the clock synthesizer. The MSR[3:2] register is used to select
between DCLK0(default), DCLK1 and DCLK2. The LCD clock is selected by writing to LCD / TV Out Control [31] = 1
and [0] = 1. MSR[3:2] are ignored when this condition is TRUE.
The data written to these registers is calculated based on the reference frequency, the desired output frequency, and
characteristic VCO constraints, as described in the functional description. From the calculation, the M, N, and P values
are obtained.
7.8.1 Programming Notes
Three blocks of registers exist for programming up to three unique frequencies for the display clock. These registers are
named dclk0, dclk1 and dclk2.
Each of these blocks can be programmed independently of each other. However, only one can be selected at any point in
time in order to control the DPLL
MSR register bits 3:2 are used to determine which DCLK0,1,2 register groups will control the DPLL.
Writing to MSR register bits 3:2 also transfers the Display Clock Divisor and Display & LCD Clock Divisor Select
Register contents to the VCO register file.
Example Programming Sequence ( DCLK0)
Write the Display Clock 0 Divisor register with the M-REG value and N-REG value.
Write the clock 0 byte of the Display & LCD Clock Divisor Select Register with the P-REG value.
Write the MSR register, bits 3:2 = '00', in order to select DCLK0. (NOTE: This is the default value.)
Example Programming Sequence ( DCLK1)
Write the Display Clock 1 Divisor register with the M-REG value and N-REG value.
Write the clock 1 byte of the Display & LCD Clock Divisor Select Register with the P-REG value.
Write the MSR register, bits 3:2 = '01', in order to select DCLK1.
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Intel® 810 Chipset Family PRM
Example Programming Sequence ( DCLK2)
Write the Display Clock 2 Divisor register with the M-REG value and N-REG value.
Write the clock 2 byte of the Display & LCD Clock Divisor Select Register with the P-REG value.
Write the MSR register, bit 3 = '1', to select DCLK2.
Example Programming Sequence (LCD CLK)
Write the LCD Clock Divisor register with the M-REG value and N-REG value.
Write the LCD byte of the Display & LCD Clock Divisor Select Register with the P-REG value.
Write the LCD / TV Out Control[31] = 1 and [0] = 1. MSR[3:2] are ignored when this condition is TRUE.
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7.8.2 DCLK_0D—Display Clock 0 Divisor Register
Address offset: 06000h–06003h
Default value: 00030013h
Attribute: R/W
Size: 32 bits
The Display Clock 0 Divisor register and Display & LCD Clock Divisor Select Register are programmed with the
loop parameters to be loaded into the clock synthesizer.
The data written to this register is calculated based on the reference frequency, the desired output frequency, and the
characteristic VCO constraints, as described in the datasheet.
Data is written to the Display Clock 0 Divisor register, followed by a write to clock 0 byte of the Display & LCD
Clock Divisor Select Register. The completion of the write to the clock 0 byte of the Video Clock Divisor Select
Register causes data from both registers to transfer simultaneously to the VCO register file. This preve nts wild fluctua-
tions in the VCO output during intermediate stages of a clock programming sequence.
31 26 25 16 15 10 9 0
Reserved VCO 0 N-Divisor Reserved VCO 0 M-Divisor
Bit Description
31-26
25-16
15-10
9-0
Reserved.
VCO 0 N-Divisor.
Reserved.
VCO 0 M-Divisor.
N-divisor value calculated for the desired output frequency. (Default: 03h)
M-divisor value calculated for the desired output frequency. (Default: 13h)
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Intel® 810 Chipset Family PRM
7.8.3 DCLK_1D—Display Clock 1 Divisor Register
Address offset: 06004h–06007h
Default value: 00100053h
Attribute: R/W
Size: 32 bits
The Display Clock 0 Divisor register and Display & LCD Clock Divisor Select Register are programmed with the
loop parameters to be loaded into the clock synthesizer.
The data written to this register is calculated based on the reference frequency, the desired output frequency, and the
characteristic VCO constraints, as described in the datasheet.
Data is written to Display Clock 0 Divisor register, followed by a write to the clock 1 byte of the Display & LCD
Clock Divisor Select Register. The completion of the write to Display & LCD Clock Divisor Select Register causes
data from both registers to transfer simultaneously to the VCO register file. This prevents wild fluctuations in the VCO
output during intermediate stages of a clock programming sequence.
31 26 25 16 15 10 9 0
Reserved VCO 1 N-Divisor Reserved VCO 1 M-Divisor
R
Bit Description
31-26
25-16
15-10
9-0
Reserved
VCO 1 N-Divisor.
Reserved
VCO 1 M-Divisor.
N-Divisor value calculated for the desired output frequency. (Default: 10h)
M-Divisor value calculated for the desired output frequency. (Default: 53h)
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7.8.4 DCLK_2D—Display Clock 2 Divisor Register
Address offset: 06008h–0600Bh
Default value: 00030013h
Attribute: R/W
Size: 32 bits
The Display Clock 2 Divisor register and Display & LCD Clock Divisor Select Register are programmed with the
loop parameters to be loaded into the clock synthesizer.
The data written to this register is calculated based on the reference frequency, the desired output frequency, and the
characteristic VCO constraints, as described in the datasheet.
Data is written to Display Clock 2 Divisor register, followed by a write to the clock 2 byte of the Display & LCD
Clock Divisor Select Register. The completion of the write to the Display & LCD Clock Divisor Select Register
causes data from both registers to transfer simultaneously to the VCO register file. This preve nts wild fluctuations in the
VCO output during intermediate stages of a clock programming sequence.
31 26 25 16 15 10 9 0
Reserved VCO 2 N-Divisor Reserved VCO 2 M-Divisor
Bit Description
31-26
25-16
15-10
9-0
Reserved.
VCO 2 N-Divisor.
Reserved.
VCO 2 M-Divisor.
N-divisor value calculated for the desired output frequency. (Default: 03h)
M-divisor value calculated for the desired output frequency. (Default: 13h)
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Intel® 810 Chipset Family PRM
7.8.5 LCD_ CLKD—LCD Clock Divisor Register
Address offset: 0600Ch–0600Fh
Default value: 00030013h
Attribute: R/W
Size: 32 bits
The LCD Clock Divisor register and Display & LCD Clock Divisor Select Register are programmed with the loop
parameters to be loaded into the clock synthesizer.
The data written to this register is calculated based on the reference frequency, the desired output frequency, and the
characteristic VCO constraints, as described in the datasheet.
Data is written to LCD Clock Divisor register, followed by a write to the LCD clock byte of the Display & LCD Clock
Divisor Select Register. The completion of the write to Display & LCD Clock Divisor Select Register causes data
from both registers to transfer simultaneously to the VCO register file. This prevents wild fluctuation s in the VCO output
during intermediate stages of a clock programming sequence.
31 26 25 16 15 10 9 0
Reserved VCO LCD N-Divisor Reserved VCO LCD M-Divisor
R
Bit Description
31:6 Reserved
25:16
15:10 Reserved
9:0
VCO LCD N-Divisor.
VCO LCD M-Divisor.
N-divisor value calculated for the desired output frequency. (Default: 03h)
M-divisor value calculated for the desired output frequency. (Default: 13h)
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®
Intel
810 Chipset Family PRM
7.8.6 DCLK_0DS—Display & LCD Clock Divisor Select Register
Address offset: 06010h–06013h
Default value: 40404040h
Attributes: R/W
Size: 32 bits
Display clock i {i=0 to 2} becomes effective after programming the appropriate byte i {i = 0 to 2}in this register. LCD
clock becomes effective after programming byte 3 in this register.
31 30 28 27 26 25 24
Reserved Post Divisor Select LCD Clk Reserved VCO
Loop Div
LCD clk
23 22 20 19 18 17 16
Reserved Post Divisor Select Clk 2 Reserved VCO
Loop Div
clk 2
Reserved
Reserved
15 14 12 11 10 9 8
Reserved Post Divisor Select Clk 1 Reserved
76 4321 0
Reserved Post Divisor Select Clk 0 Reserved
Bit Description
31
30:28
Reserved.
Post Divisor Select LCD Clock.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16 (default)
101 = Divide by 32
11x = Reserved
27
26
Reserved.
VCO Loop Divide LCD Clock.
0 = Divided by 4*M (default) (M = LCD Clock Divisor Register [9:0])
1 = Divided by 16*M
25:23
Reserved.
VCO
Loop Div
clk 1
VCO
Loop Div
clk 0
Reserved
Reserved Reserved
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Intel® 810 Chipset Family PRM
Bit Description
22:20
Post Divisor Select clock 2.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16 (default)
101 = Divide by 32
11x = Reserved
19
18
Reserved.
VCO Loop Divide clock 2.
0 = Divided by 4*M (default) (M = Display Clock 2 Divisor Register [9:0])
1 = Divided by 16*M
17:15
14:12
Reserved.
Post Divisor Select clock 1.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16 (default)
101 = Divide by 32
11x = Reserved
11
10
Reserved.
VCO Loop Divide clock 1.
0 = Divided by 4*M (default) (M = Display Clock 1 Divisor Register [9:0])
1 = Divided by 16*M
9:7
6:4
Reserved.
Post Divisor Select clock 0.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16 (default)
101 = Divide by 32
11x = Reserved
3
2
Reserved.
VCO Loop Divide clock 0.
0 = Divided by 4*M (default) (M = Display Clock 0 Divisor Register [9:0])
1 = Divided by 16*M
1
0
Reserved.
Reserved. 0
R
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Intel
810 Chipset Family PRM
7.8.7 PWR_CLKC—Power Management and Miscellaneous Clock Control
Address offset: 6014h–06017h
Default value: 00 00 01 03 h
Attribute: R/W
Size: 32 bits
31 17 16
Reserved
15 12 11 10 9 8
Reserved Reserved
.
7 21 0
Reserved Display
Clock
PLL
VCO
Internal
DAC
Enable
Bit Description
31:9
8
7:2
1
0
Reserved.
Reserved.
Display Clock PLL VCO
0 = Disable
1 = Enable (default)
Internal DAC Enable.
0 = Disables the internal DAC (power-down). If HSYNC/VSYNCControl[0] = 0, disables HSYNC and
VSYNC.
1 = Enables the internal DAC and does not allow disabling of HSYNC and VSYNC via HSYNC/VSYNC
Control[0]. (Default)
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Intel® 810 Chipset Family PRM
7.9 LCD / TV-Out Registers
During the LCD or TV-Out mode, the BIOS will program the following LCD / TV-out registers. These registers are 32bit, memory-mapped registers. These registers are not double-buffered and take effect when loaded. Further, this
subsystem takes into account modified CR register values during vertical blank time for centering.
This subsystem allows the timing generator to be programmed to pixel granularity. The only exception is during the
VGA pixel-doubling mode. During VGA pixel-doubling, active pixel time must be a multiple of 4 pixels to account for
centering with VGA pixel-doubling, and non-active times must be a multiple of 2 pixels clocks.
All fields are excess-0 encoded. This means that the hardware uses the value + 1, where the value is the entry in the field.
Therefore if a 0 is programmed into a field, the hardware uses the value 1 for that field.
7.9.1 HTOTAL—Horizontal Total Register
Address offset: 60000h
Default value: 00000000h
Access: Read/Write
Size: 32 bits
R
31 28 27 16 15 11 10 0
Reserved Horizontal Total Display Pixels Reserved Horizontal Active Display
Pixels
Bit Description
31:28
27:16
15:11
10:0
Reserved.
Horizontal Total Display Pixels.
encompassing 2048 active display pixels, front/back border pixels, and the horizontal retrace period. Any
pending event (HSYNC, VSYNC) is reset at htotal.
Reserved.
Horizontal Active Display Pixels.
2048 pixels. Note that the first horizontal active display pixel always starts at 0.
Read Only
This 12-bit field provides a horizontal total of up to 4096 pixels,
Read Only
This 11-bit field provides horizontal active display resolutions up to
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R
7.9.2 HBLANK—Horizontal Blank Register
Address offset: 60004h
Default value: 00000000h
Access: Read/Write
Size: 32 bits
31 28 27 16 15 12 11 0
Reserved Horizontal Blank End Reserved Horizontal Blank Start
Bit Description
®
Intel
810 Chipset Family PRM
31:28
27:16
15:12
11:0
Reserved.
Horizontal Blank End.
the horizontal active display start. Note: An asserted HBlank will be deasserted when HTotal occurs,
regardless of what is programmed in the HBlank end.
Reserved.
Horizontal Blank Start.
horizontal active display start
Read Only
Horizontal blank end expressed in terms of the absolute pixel number relative to
Read Only
Horizontal blank start, expressed in terms of absolute pixel number relative to the
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Intel® 810 Chipset Family PRM
7.9.3 HSYNC—Horizontal Sync Register
Address offset: 60008h
Default value: 00000000h
Access: Read/Write
Size: 32 bits
31 28 27 16 15 12 11 0
Reserved Horizontal Sync End Reserved Horizontal Sync Start
Bit Description
R
31:28
27:16
15:12
11:0
Reserved.
Horizontal Sync End.
horizontal active display start.
Note:
1. Minimum HSYNC width is 1 pixel clock.
An asserted HSYNC will be cleared as soon as HTOTAL end is reached, regardless of the value in the
HSYNC End register.
Reserved.
Horizontal Sync Start
horizontal active display start.
Note that when HSYNC Start is programmed equal to HBLANK Start, both HSYNC and HBLANK will be
asserted on the same pixel clock.
Read Only
Horizontal sync end, expressed in terms of absolute pixel number relative to the
Read Only
. Horizontal sync start expressed in terms of absolute pixel number relative to the
7.9.4 VTOTAL—Vertical Total Register
Address offset: 6000Ch
Default value: 00000000h
Access: Read/Write
Size: 32 bits
31 28 27 16 15 11 10 0
Reserved Vertical T o tal Display Pixels Reserved Vertical Active Display Pixels
Bit Description
31:28
27:16
15:11
10:0
Reserved.
Vertical Total Display Pixels.
4096 lines, encompassing 2048 active display lines, top/bottom border lines, and the vertical retrace
period.
Reserved.
Vertical Active Display Pixels.
display resolution up to 2048 lines. Note that the first vertical active display line always starts at 0.
Read Only
Vertical total display lines. This 12-bit field provides a vertical total up to
Read Only
Vertical active display lines. This 11-bit field provides a vertical active
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