Intel 82801EB User Manual

Intel® 82801EB (ICH5) I/O 82801ER (ICH5R), and 82801DB (ICH4) Controller Hub: AC ’97 PRM

Programmers Reference Manual (PRM)

April 2003

Document Number: 252751-001

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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® 82801EB (ICH5) I/O 82801ER (ICH5R), and 82801DB (ICH4) controller hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.

I Implementations of the I Corporation.

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*Other names and brands may be claimed as the property of others.

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

2 AC ’97 Programmer’s Reference Manual

Introduction.......................................................................................................................... 7

1.1 About This Document ............................................................................................. 7

1.2 Reference Documents and Information Sources ................................................... 9

2 Overview ...........................................................................................................................11

2.1 Intel® ICH5 AC ’97 Controller Compatibility .......................................................... 11

2.1.1 Third AC ’97 Component Specification Revision 2.1, Revision 2.2 and

Revision 2.3 Compliant Codecs ............................................................ 14

2.1.2 Dedicated S/P DIF DMA Output Channel ............................................. 15

2.1.3 20 Bits Surround PCM Output............................................................... 15

2.1.4 Memory Map Status and Control Registers .......................................... 15

2.1.5 Second Independent Input DMA Engines ............................................. 16

2.1.6 PCI Local Bus Specification, Revision 2.3 Power Management........... 16

2.2 General Requirements ......................................................................................... 16

3 Intel® ICH5 AC ’97 Controller Theory of Operation ...........................................................17

3.1 Intel® ICH5 AC ’97 Initialization............................................................................. 17

3.1.1 System Reset........................................................................................ 17

3.1.2 Codec Topology .................................................................................... 17

3.1.3 BIOS PCI Configuration ........................................................................ 18

3.1.4 Hardware Interrupt Routing................................................................... 19

3.1.5 PCI Lock ............................................................................................... 19

3.2 DMA Engines........................................................................................................ 20

3.2.1 Buffer Descriptor List ............................................................................ 20

3.2.2 DMA Initialization................................................................................... 21

3.2.3 DMA Steady State Operation................................................................ 23

3.2.4 Stopping Transfers................................................................................ 24

3.2.5 FIFO Error Conditions ........................................................................... 24

3.2.5.1 FIFO Underrun .................................................................... 24

3.2.5.2 FIFO Overrun ...................................................................... 24

3.3 Channel Arbitration ............................................................................................... 25

3.4 Data Buffers.......................................................................................................... 25

3.4.1 Memory Organization of Data ............................................................... 25

3.4.2 PCM Buffer Restrictions........................................................................ 25

3.4.3 FIFO Organization................................................................................. 26

3.5 Multiple Codec/Driver Support.............................................................................. 27

3.5.1 Codec Register Shadowing................................................................... 28

3.5.2 Codec Access Synchronization............................................................. 29

3.5.3 Data Request Synchronization in Audio Split Configurations................ 29

3.6 Power Management ............................................................................................. 30

3.6.1 Codec Topologies ................................................................................. 30

3.6.1.1 Tertiary Codec Topologies................................................... 31

3.6.2 Power Management Transition Maps ................................................... 31

3.6.3 Power Management Topology Considerations ..................................... 34

AC ’97 Programmer’s Reference Manual 3

3.6.3.1

Determining the Presence of Secondary and Tertiary

Codecs................................................................................. 34

3.6.3.2 Determining the Presence of a Modem Function ................ 35

3.6.4 Resume Context Recovery ................................................................... 35

3.6.5 Aggressive Power Management ........................................................... 35

3.6.5.1 Primary Audio Requested to D3 .......................................... 36

3.6.5.2 Secondary Modem Requested to D3................................... 36

3.6.5.3 Secondary Modem Requested to D0................................... 36

3.6.5.4 Audio Primary Requested to D0 .......................................... 37

3.6.5.5 Using a Cold or Warm Reset............................................... 37

4 Surround Audio Support.................................................................................................... 39

4.1 Determine Codec’s Audio Channels..................................................................... 39

4.2 Enabling Intel® ICH5 AC ’97 Controller Audio Channels ......................................40

5 20-Bits PCM Support......................................................................................................... 43

6 Independent S-P/DIF Output Capability ............................................................................ 45

7 Support for Double Rate Audio ......................................................................................... 47

8 Independent Input Channels Capability............................................................................. 49

8.1 Link Topology Determination ................................................................................ 49

9 Intel® ICH5 AC ’97 Modem Driver .....................................................................................51

9.1 Robust Host-Based Generation of a Synchronous Data Stream ......................... 51

9.1.1 Spurious Data Algorithm ....................................................................... 52

9.1.2 Intel® ICH5 AC ’97 Spurious Data Implementation ............................... 52

4 AC ’97 Programmer’s Reference Manual

Figures

Figure 1. Block Diagram of Platform Chipset with Intel® ICH5 Component ...................... 13

Figure 2. Intel® ICH5 AC ’97 Controller Connection to Its Companion Codecs ................ 14

Figure 3. Generic Form of Buffer Descriptor (One Entry in the List)................................. 20

Figure 4. Buffer Descriptor List ......................................................................................... 21

Figure 5. Compatible Implementation with Left and Right Sample Pair in Slot 3/4 Every

Frame......................................................................................................................... 26

Figure 6. Compatible Implementation with Sample Rate Conversion Slots 3 and 4

Alternating over Next Frame ...................................................................................... 26

Figure 7. Incompatible Implementation of Sample Rate Conversion with Repeating Slots

over Next Frames ...................................................................................................... 27

Tables

Table 1. Applicable Components ........................................................................................ 7

Table 2. Audio Features Distribution Matrix ...................................................................... 12

Table 3. Audio Registers ................................................................................................... 18

Table 4. Modem Registers ................................................................................................ 19

Table 5. BD Buffer Pointer (DWORD 0: 00-03h) .............................................................. 20

Table 6. BD Control and Length (DWORD 1: 04-07h) ...................................................... 21

Table 7. Audio Descriptor List Base Address.................................................................... 22

Table 8. Modem Descriptor List Base Address................................................................. 22

Table 9. Audio Last Valid Index......................................................................................... 22

Table 10. Modem Last Valid Index.................................................................................... 23

Table 11. FIFO Summary.................................................................................................. 27

Table 12. SDM Register Description ................................................................................. 28

Table 13. Dual Codecs Topologies ...................................................................................30

Table 14. Power State Mapping for Audio Single or Dual (Split) Codec Desktop

Transition ................................................................................................................... 32

Table 15. Power State Mapping for Modem Single Codec Desktop Transition ................32

Table 16. Power State Mapping for Audio in Dual Codec Desktop Transition.................. 33

Table 17. Power State Mapping for Modem in Dual Codec Desktop Transition ............... 34

Table 18. Extended Audio ID Register .............................................................................. 39

Table 19. Single Codec Audio Channel Distribution ......................................................... 39

Table 20. Multiple Codec Audio Channel Distribution ....................................................... 40

Table 21. CM 4/6 –PCM Channels Capability Bits............................................................ 40

Table 22. AC-Link PCM 4/6 -Channels Enable Bits .......................................................... 41

Table 23. Sample Capabilities........................................................................................... 43

Table 24. PCM Out Mode Selector ................................................................................... 43

Table 25. Global Control Register S-P/DIF Slot Map Bits ................................................. 45

Table 26. Topology Descriptor .......................................................................................... 49

Table 27. SDATA_IN Map................................................................................................. 49

Table 28. Codec Ready Bits.............................................................................................. 50

Table 29. MMBAR: Mixer Base Address Register ............................................................ 50

AC ’97 Programmer’s Reference Manual 5

Revision History

Revision

Number

-001 Initial Release. April 2003

Description Revision Date

6 AC ’97 Programmer’s Reference Manual

Introduction

)

1 Introduction

1.1 About This Document

This document was prepared to assist Independent Hardware and Software Vendors (IHVs and ISVs) in supporting the Intel document also applies to the previous generation of Intel I/O controller hub components and describes the general requirements to develop an audio driver that will make use of the AC ’97 audio interface.

This document also describes functions that the BIOS or Operating Systems (OS) must perform in order to ensure correct and reliable operation of the platform. This document will be supplemented from time to time with specification updates. The specification updates contain information relating to the latest programming changes. Check with your Intel representative for availability of specification updates.

The following table outlines ICH device information at a glance.

Table 1. Applicable Components

Device ID

Vendor ID

Device Name

Subsystem Vendor

Intel®

8086 2415 Default is 00h.

ICH

Value of this register varies according to the system

Subsystem Device

Default is 00h. Value of this register varies according to the system

I/O controller hub (ICH5) AC ’97 controller feature set. This

Addr

Revision ID

Prog. Interface

Sub-Class Code

Base Class Code

04h 01h 00h ALL 00h 1Fh 5 PCI\VEN_8086&DE

Device Number

Bus Number (PCI

Microsoft PNP

Function Number

Device Node ID

V_2415 (subsystem will also provide additional information)

Intel Desired Device

Intel Audio Controller (displayed by driver provider’s INF)

Description (INF

name) Name for:

Operating System

Microsoft Windows*

82801AA AC ‘97

Intel

8086 2416 Default is 00h.

ICH

Intel

8086 2425 Default is 00h.

ICH-0

Value of this register varies according to the system

Default is 00h. Value of this register varies according to the system

07h 03h 00h ALL 00h 1Fh 6 PCI\VEN_8086&DE

V_2416 (subsystem will also provide additional information)

04h 01h 00h ALL 00h 1Fh 5 PCI\VEN_8086&DE

V_2425

(subsystem will also provide additional information)

Intel 82801AA AC ‘97 Modem Controller (displayed by driver provider’s INF)

Intel

82801AB AC ‘97 Audio Controller (displayed by driver provider’s INF)

AC ’97 Programmer’s Reference Manual 7

Introduction

)

Device ID

Vendor ID

Device Name

Subsystem Vendor

Intel

8086 2426 Default is 00h.

ICH-0

Intel

8086 2435 Default is 00h.

ICH2

ICH2 8086 2436 Default is 00h.

Value of this register varies according to the system

Subsystem Device

Default is 00h. Value of this register varies according to the system

Addr

Revision ID

Prog. Interface

Sub-Class Code

Base Class Code

07h 03h 00h ALL 00h 1Fh 6 PCI\VEN_8086&DE

04h 01h 00h ALL 00h 1Fh 5 PCI\VEN_8086&DE

04h 01h 00h ALL 00h 1Fh 6 PCI\VEN_8086&DE

Device Number

Bus Number (PCI

Microsoft PNP

Function Number

Device Node ID

V_2426 (subsystem will also provide additional information)

V_2435 (subsystem will also provide additional information)

V_2436

(subsystem will also provide additional information)

Description (INF

name) Name for:

Intel Desired Device

Intel 82801AB AC ‘97 Modem Controller (displayed by driver provider’s INF)

Intel

“ICH2” AC ‘97 Audio Controller (displayed by driver provider’s INF)

Intel

ICH2 DT/Server /Mobile/Low End” AC ‘97 Modem Controller (displayed by driver provider’s INF)

Operating System

Microsoft Windows*

Intel

8086 2445 Default is 00h.

ICH3

ICH3 8086 2446 Default is 00h.

Intel

8086 24C5 Default is 00h.

ICH4

ICH4 8086 24C6 Default is 00h.

Value of this register varies according to the system

Default is 00h. Value of this register varies according to the system

04h 01h 00h ALL 00h 1Fh 5 PCI\VEN_8086&DE

V_2445 (subsystem will also provide additional information)

04h 01h 00h ALL 00h 1Fh 6 PCI\VEN_8086&DE

V_2446

(subsystem will also provide additional information)

04h 01h 00h ALL 00h 1Fh 5 PCI\VEN_8086&DE

V_24C5

(subsystem will also provide additional information)

04h 01h 00h ALL 00h 1Fh 6 PCI\VEN_8086&DE

V_24C6

(subsystem will also provide additional information)

Intel

“ICH3” AC ‘97 Audio Controller (displayed by driver provider’s INF)

Intel

ICH3 DT/Server /Mobile/Low End” AC ‘97 Modem Controller (displayed by driver provider’s INF)

Intel

“ICH4” AC ‘97 Audio Controller (displayed by driver provider’s INF)

Intel

ICH4 DT/Server /Mobile/Low End” AC ‘97 Modem Controller (displayed by driver provider’s INF)

8 AC ’97 Programmer’s Reference Manual

Introduction

)

Device ID

Vendor ID

Device Name

Subsystem Vendor

Intel

8086 24D5 Default is 00h.

ICH5

ICH5 8086 24D6 Default is 00h.

Value of this register varies according to the system

Subsystem Device

Default is 00h. Value of this register varies according to the system

Addr

Revision ID

Prog. Interface

Sub-Class Code

Base Class Code

04h 01h 00h ALL 00h 1Fh 5 PCI\VEN_8086&DE

04h 01h 00h ALL 00h 1Fh 6 PCI\VEN_8086&DE

Device Number

Bus Number (PCI

Microsoft PNP

Function Number

Device Node ID

V_24D5

(subsystem will also provide additional information)

V_24D6

(subsystem will also provide additional information)

Description (INF

name) Name for:

Intel Desired Device

Intel

“ICH5” AC ‘97 Audio Controller (displayed by driver provider’s INF)

Intel

ICH5 DT/Server / Low End” AC ‘97 Modem Controller (displayed by driver provider’s INF)

Microsoft Windows*

Operating System

1.2 Reference Documents and Information Sources

Document Name or Information Source Available From

Audio Codec ’97 Specification, Revision 2.1, Revision 2.2 and Revision 2.3

Communications and Networking Riser Specification, Version 1.0 and 1.2 http://developer.intel.com/technology

PCI Local Bus Specification, Revision 2.3 http://www.pcisig.com/specifications/

Microsoft Windows* Driver Development Kits

– http://www.microsoft.com/ddk

Microsoft Windows* Driver and Hardware Development

-- http://www.microsoft.com/hwdev

NOTE:

1. Contact your Intel representative for the current document revision.

http://www.intel.com/labs/media/audi o/index.htm

/cnr/

conventional/

Microsoft

AC ’97 Programmer’s Reference Manual 9

Introduction

This page is intentionally left blank.

10 AC ’97 Programmer’s Reference Manual

Overview

2 Overview

In this document, “ICH5” stands for I/O Controller Hub 5. The ICH5 provides an AC ’97compliant controller. References to the “AC ’97 Component Specification” refer to the Audio Codec ’97 Specification, Revision 2.1, Revision 2.2, and Revision 2.3. The ICH5 AC ’97 Digital Controller implementation interfaces to AC ’97 Component Specification, Revision 2.3 and below-compliant codecs. The ICH5 supports up to three AC ’97 Component Specification compliant codecs on the AC-link interface.

This document is limited to specifying the software requirements and driver interface for the ICH5 AC ’97 digital controller. Wherever possible, it has pointers to additional considerations for supporting future proliferation or derivatives of the ICH5 digital controller. However, considerations for these future devices are subject to change.

2.1 Intel® ICH5 AC ’97 Controller Compatibility

The ICH5 AC ’97 controller is fully compatible with the features found in the ICH1/2/3/4 versions. This allows for current drivers developed by ISVs and IHVs to work without modifications. The ICH5 however, provides capabilities not found in ICH family components prior to ICH4. The following matrix provides a description of the available features for each of the ICHx component generations. This document specifically addresses features on ICH5 while maintaining the original programming model reference for new developers working directly with ICH5 and not previously exposed to the ICH component.

Figure 1 displays a block diagram of the platform chipset with the ICH5 component. Figure 2 represents the typical configuration for the ICH5 AC ’97 controller and companion codecs.

AC ’97 Programmer’s Reference Manual 11

Overview

Table 2. Audio Features Distribution Matrix

AC ’97 Audio Controller Features Intel®

16 bits Stereo PCM Output ⌧

16 bits Stereo PCM Input ⌧

16 bits Microphone Input ⌧

GPIO and Interrupt Support ⌧

Two 2.1/2.2/2.3 Codec Support ⌧

16 bits 2/4/6 Ch. Surround PCM Output

20 bits 2/4/6 Ch. Surround PCM Output

Dedicated S/P DIF DMA Output Ch.

Third 2.1/2.2/ 2.3 Codec Support

Memory Map Control and Status

Second 16 bits Stereo PCM Input

Second 16 bits Microphone Input

PCI 2.3 Power Management

ICH

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

Intel

ICH2

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

Intel®

ICH3

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

Intel®

ICH4

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

⌧

⌧⌧⌧

Intel®

ICH5

⌧⌧⌧

The ICH5 AC ’97 audio controller provides a set of features that require significant software support. The following paragraphs provide a summary of these features.

The modem support infrastructure has not been changed in any generation of the I/O controller hub starting with the ICH.

12 AC ’97 Programmer’s Reference Manual

Overview

Figure 1. Block Diagram of Platform Chipset with Intel

ICH5 Component

Process

M e

MCH

USB 2.0

(Supports 6 USB ports)

IDE-Primary

IDE-Secondary

SATA (2 ports)

C’97 Codec(s)

LAN Connect

GPIO

OtherASICs

(Optional)

Intel

ICH5

LPC I/F

Super I/O

Firmware

Hub(s)

PCI Bus

S L

Power Management

Clock Generators

System Management

(TCO)

SMBus 2.0/I 2 C

...

LAN

AC ’97 Programmer’s Reference Manual 13

Overview

Figure 2. Intel

ICH5 AC ’97 Controller Connection to Its Companion Codecs

Digital Controller

RESET#

SDATA_OUT

SYNC

BIT_CLK

Intel® ICH

SDATA_IN_0

SDATA_IN_1

SDATA_IN_2

AC '97/AC '97 2.x/AMC '97

Primary Codec

AC '97/MC '97 2.x/AMC '97

Secondary

Codec

AC '97/AC '97 2.x/AMC '97

Tertiary Codec

2.1.1 Third AC ’97 Component Specification Revision 2.1, Revision 2.2 and Revision 2.3 Compliant Codecs

The AC ’97 Component Specification provides capability for up to four, SDATA_IN signals in support of up to four codecs. The ICH5 AC ’97 controller provides support for up to three codecs to allow for Audio channel expansion without sacrificing the Modem Codec (MC) support. Also, the third codec capability enables a better mobile docking infrastructure.

2751_2

14 AC ’97 Programmer’s Reference Manual

Overview

2.1.2 Dedicated S/P DIF DMA Output Channel

The ICH5 controller provides a dedicated DMA engine with the capability of outputting either PCM or AC-3 data to the S/P DIF link for pass-through to an external CE audio decoder. This capability allows for simultaneous output of PCM/AC-3 on the S/P DIF link while PCM data is output to the PCM Out DMA engine. As a result, an AC3 stream from DVD movie playback can be output on the S/P DIF link concurrently with other system audio data (e.g., voice audio from a telephony application).

2.1.3 20 Bits Surround PCM Output

The AC ’97 Component Specification provides a maximum bit resolution of 20 bits per sample. The ICH5 AC ’97 controller PCM Output DMA Engine fully exploits this capability to improve the audio output quality.

2.1.4 Memory Map Status and Control Registers

The ICH5 support PCI Memory Base Address Register that allows for higher performance access to the controller registers while expanding the register space to access the third codec support mechanism. All features can now be accessed via this Memory BAR making the I/O BAR capabilities obsolete. However, the ICH5 controller may maintain the I/O BAR capability to allow for the reuse of legacy code maintaining backward compatibility to deployed driver binaries.

Note: This document describes the programming interface using the Memory BAR registers unless

otherwise indicated. The default configuration for ICH5 Audio function is to use the PCI Memory Base Address Register. The I/O BAR is therefore disabled unless system BIOS enables the simultaneous backward-compatible capability on the register:

Device 31 Function 5 Audio

Offset Register Default Comments

41h CFG

Configuration

00h When cleared, the I/O space BARs at offset 10h and 14h become

read only registers. This is the default state for the I/O BARs. Initialized by BIOS when backward I/O Bar compatibility is required Memory BARs are always enabled.

AC ’97 Programmer’s Reference Manual 15

Overview

2.1.5 Second Independent Input DMA Engines

The ICH5 continues to provide two sets of input DMA engines that allow for the secondary or tertiary codecs to provide recording PCM data streams on the primary codec while simultaneously providing recording capabilities from the secondary or tertiary codec. A typical application is to provide independent input stream in a mobile docking configuration where an audio codec is located in the base system (notebook unit) and the secondary or tertiary codec is located in a docking unit for desktop replacement. The DMA engines provide the infrastructure for s/w to select the input stream from either source for stereo or microphone recording. Also the capability of simultaneous input streams opens the possibilities for more futuristic applications where a multiple microphone array can be created using two codecs. Refer to Section 3.2 for more information on how to program the DMA engines.

2.1.6 PCI Local Bus Specification, Revision 2.3 Power Management

The ICH5 provides PCI Local Bus Specification, Revision 2.3-compliant power management registers that allows for better OS power management support with reduced overhead to the BIOS programmers using ACPI control methodologies.

2.2 General Requirements

It is assumed that the reader has a working knowledge of AC ’97 architecture and the ICH5 AC’97 controller implementation. Also, the reader should have an understanding of audio driver development for the target operating systems.

This document outlines the software specification for the AC ’97 digital controller, and also includes details necessary for development of an audio device driver.

16 AC ’97 Programmer’s Reference Manual

+ 37 hidden pages

Intel 82801EB User Manual

Contents

Revision History

Introduction

1.1 About This Document

1.2 Reference Documents and Information Sources

Overview

2.1.1 Third AC ’97 Component Specification Revision 2.1, Revision 2.2 and Revision 2.3 Compliant Codecs

2.1.2 Dedicated S/P DIF DMA Output Channel

2.1.3 20 Bits Surround PCM Output

2.1.4 Memory Map Status and Control Registers

2.1.5 Second Independent Input DMA Engines

2.1.6 PCI Local Bus Specification, Revision 2.3 Power Management