INTEL 82559 User Manual

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82559 Fast Ethernet Multifunction
PCI/CardBus Controller

Stepping Information

October 2004

Revision 2.2

Notice: The 82559 Fast Ethernet Multifunction PCI/CardBus Controller may contain design
defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are documented in this specification update.

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
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fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82559 Fast Ethernet Multifunction PCI/CardBus Controller may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800­548-4725 or by visiting Intel's Web site at http://www.intel.com.

Copyright © 2004, Intel Corporation.

* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit without
intent to infringe.

82559 Stepping Information

Contents

Revision History ........................................................................................................................................ 1

Preface ...................................................................................................................................................... 1

Nomenclature ............................................................................................................................................ 1

Identification Information............................................................................................................................3

82559 Component Marking Identification ..................................................................................... 3

82559 Component Programming Interface Identification ............................................................4

Summary Table of Changes ...................................................................................................................... 4

Specification Changes................................................................................................... 6

1. Removal of Internal Pull-up Resistor from Isolate Pin ..................................................... 6

2. Unsupported End of List Bit in High Priority Queues ....................................................... 6

3. Supported Total Cost of Ownership (TCO) Frame Formats ............................................ 6

4. Deep Power-Down Current Consumption .......................................................................6

Errata............................................................................................................................. 7

1. Base Registers Restore After a Selective Reset ............................................................. 7

2. Base Registers Initialization Changes ............................................................................. 7

3. Receive Total Cost of Ownership (TCO) Packets Truncation .........................................7

4. Corrupted Byte Count on System Management Bus (SMB) upon Reset ........................ 8

5. Corrupted Alert Response Address on System Management Bus on Software Reset ...8

6. Premature Clamping of Electrostatic Discharge Circuitry................................................8

7. False Power Management Event Indication on Power Cycle ..........................................9

8. Modem Interrupt Propagation........................................................................................10

9. Corrupted PCI Burst Read with D0 System Management Bus Receive........................10

10. Programmable Filter Corruption ....................................................................................10

11. Invalid Alert Response Address (ARA) Return .............................................................. 11

12. Potential Receive Overrun in Dynamic Standby Mode..................................................11

13. False Detection of Security ASIC .................................................................................. 13

Specification Clarifications .......................................................................................... 14

1. 82559 Initialization During System Management Bus (SMB) Access ...........................14

2. 82559C Compliance ...................................................................................................... 14

3. Link Loss Deep Power-Down Noise Sensitivity ............................................................. 14

4. PCI Buffer Leakage When the Voltage Input/Output Pin (VIO) Not Powered ...............14

5. Load and Start Receive Unit Commands in IP Security Applications............................15

Documentation Changes............................................................................................. 16

1. 82559 LAN on Motherboard Design Guide.................................................................... 16

2. Software Technical Reference Manual..........................................................................17

82559 Stepping Information iii

3. 82559 Fast Ethernet Controller Datasheet .................................................................... 17

iv 82559 Stepping Information

Revision History

Date Version Description

Oct 2004 2.2

Mar. 2002 2.1 • Updated “82559 Component Marking Identification”.

Feb. 2002 2.0

Mar. 2001 1.6

Apr. 2000 1.5

May 1999 1.3 Added B-step clamping erratum.

Nov. 1998 0.8 Added clarification material.

Oct. 1998 0.7 Initial release.

• Removed Intel Confidential status.

• Removed references to A3 stepping, which does not exist.

• Added Specification Change 4, “Deep Power-Down Current Consumption”
and Errata 12, “Potential Receive Overrun in Dynamic Standby Mode” and

Errata 13, “False Detection of Security ASIC”.

• Changed references to Software Developer’s Manual (SDM) to Software
Technical Reference Manual (STRM).

• Added 82559 Fast Ethernet Controller Datasheet to the Document Changes
section.

• Combined Revision 1.3 of this document with 82559C Stepping Information
document.

• Revised tables in Identification Information section to reflect correct stepping
information and revision numbers.

• Updated document format to comply with current corporate templates.

Preface

This document is an update to the specifications contained in the Intel® 82559 Fast Ethernet
Multifunction PCI/CardBus Controller Data Sheet, and contains issues affecting all design using
the 82559 device.

This document is intended for hardware system manufacturers and software developers of
applications, operating systems or tools. It contains Specification Changes, Errata, Specification
Clarifications, and Document Changes.

All changes, errata, and clarifications described in this document will be incorporated into the next
release of the 82559 Fast Ethernet Multifunction PCI/CardBus Controller Data Sheet.

Nomenclature

Specification Changes are modifications to the current published specifications. These changes
will be incorporated in the next release of the specifications.

Errata are design defects or errors.
published specifications. Hardware and software designed to be used with any given stepping must
assume that all errata documented for that stepping are present on all devices.

Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation.
next release of the specifications.

Errata may cause the 82559’s behavior to deviate from

These clarifications will be incorporated in the

82559 Stepping Information 1

Documentation Changes include typos, errors, or omissions from the current published
specifications. These changes will be incorporated in the next release of the specifications.

2 82559 Stepping Information

Identification Information

82559 Component Marking Identification

Device Stepping Top Marking Q-specification MM Number Notes

82559 B1 - 3 GD82559 Q405 MM818501 Engineering samples

82559 B5 GD82559 STD MM821112 No longer in production.

82559 B5 GD82559 Q406 MM821144 Production samples (tray)

82559 B5 GD82559 SL3Q3 MM825117 Production (tape and reel)

82559 B5 GD82559 SL3HD MM822772 Production (tray)

82559C A2 GD82559C STD MM824178 Production (tape and reel)

82559C A2 GD82559C Q408 MM825112 Production (tray)

82559C A2 GD82559C SL3DF MM822048 Production (tray)

GD82559C
FFFFFFFF

M C '99

KOREA

FFFFFFFF FPO numbers

82559 Stepping Information 3