Intel 82555 User Manual

82555 10/100 Mbps LAN Physical Layer Interface

Networking Silicon

Datasheet

Product Features

■

Optimal integration for lower cost solutions

—Integrated 10/100 Mbps single chip

physical layer interface solution

—Complete 10/100 Mbps MII compliance

with MDI support

—Full duplex operation in 10 Mbps and

100 Mbps modes

—IEEE 802.3u Auto-Negotiation support

for 10BASE-T half and full duplex, 100BASE-TX half and full duplex, and 100BASE-T4 configurations

—Parallel detection algorithm for legacy

support of non-Auto-Negot ia ti on enabled link partner

—Integrated 10BASE-T transcei v er with

built in transmit and receive filters

—Glueless interface to T4-PHY for

combination TX/T4 designs with single magnetics

—Glueless support for 4 LEDs: activity,

link, speed, and duplex —LED function mapping support via MDI —Low external component count —Single 25 MHz clock support for 10

Mbps and 100 Mbps (crystal or

oscillator) —Single magnetics for 10 Mbps and 100

Mbps operation —QFP 100-pin package

■

Performance enhancements

—Flow control support for IEEE 802.3x

Auto-Negotiation and Bay Technologies PHY Base* scheme

—Adaptive Channel Equalizer for greater

functionality over varying cable lengths

—High tolerance to extreme noise

conditions —Very lo w emissions —Jabber control circuitry to prevent data

loss in 10 Mbps operation —Auto-polarity correction for 10BASE-T —Software compatible with 82557 drivers

■

Repeater functionality

—Repeater mode operation —Support for forced speed of 10 Mbps

and 100 Mbps —Automatic carrier disconnect for IEEE

802.3u compliance

—Auto-Negotiation enable/disable

capability —Receive port enable function —Support for 32 configurable addresses —Narrow analog side (14 mm) for tight

packing in repeater and switch designs

Notice: Notice:

Document Number: 666252-004

Revision 2.0

March 1998

82555 — Networking Silicon

■

Low power consumption

—Typical total solution power including

all resistors and magnetics:

- 275 mA 100BASE-TX

- 230 mA 10BASE-T

- 250 mA Auto-Negotiation

—300 mA maximum total solution power

in DTE (adapter) mode

—Power-down of 10BASE-T/100BASE-

■

Added modes for design, testing, and manufacturability

—Test Access Port (TAP)

- NAND Tree

- Board Level Functional Test (BIST)

—Programmable bypass for 4B/5B

encoding/decoding and scrambler/

descrambler —Diagnostic loopback mode

TX sections when not in use

Revision Hist ory

Revision

Date

Jan. 1997 1.0 First external release of the preliminary datasheet Apr. 1997 1.1 First release edition Mar. 1998 2.0 General editing

Revision Description

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any f e atures or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation

P.O. Box 7641 Mt. Prospect IL 60056-7641

ii Datasheet

Networking Silicon — 82555

Contents

1.0 INTRODUCTION..........................................................................................................................1

1.1 Functional Overview........................................................................................................1

1.2 Compliance to Industry Standards..................................................................................1

2.0 ARCHITECTURAL OVERVIEW...................................................................................................3

2.1 100 Mbps Mode...............................................................................................................3

2.2 10 Mbps Mode.... ...... ....... ...... ....... ...... ....... ...... ................................................................4

2.3 Media Independent Interface (MII)..................................................................................5

3.0 PIN DEFINITIONS........................................................................................................................7

3.1 Pin Types .......................................................................................................................8

3.2 Clock Pins ......................................................................................................................8

3.3 Twisted Pair Ethernet (TPE) Pins ...................................................................................8

3.4 Media Independent Interface (MII) Pins .........................................................................8

3.5 Media Access Control/Repeater Interface Control Pins .................................................9

3.6 LED Pins ......................................................................................................................10

3.7 External Bias Pins ........................................................................................................10

3.8 Miscellaneous Control Pins .................................. ....... ...... ....... ....................................11

3.9 Power and Ground Pins ...............................................................................................12

4.0 100BASE-TX ADAPTER MODE OPERATION..........................................................................13

4.1 100BASE-TX Transmit Clock Generation .....................................................................13

4.2 100BASE-TX Transmit Blocks ......................................................................................13

4.2.1 100BASE-TX 4B/5B Encoder ....................................................................13

4.2.2 100BASE-TX Scrambler and MLT-3 Encoder ...........................................14

4.2.3 100BASE-TX Transmit Framing ................................................................15

4.2.4 Transmit Driver ..........................................................................................16

4.3 100BASE-TX Receive Blocks .......................................................................................16

4.3.1 Adaptive Equalizer.....................................................................................17

4.3.2 Receive Clock and Data Recovery............................................................17

4.3.3 MLT-3 Decoder, Descrambler, and Receive Digital Section......................17

4.3.4 100BASE-TX Receive Framing .................................................................17

4.3.5 100BASE-TX Receive Error Detection and Repo rt ing. ..............................17

4.4 100BASE-TX Collision Detection..................................................................................17

4.5 100BASE-TX Link Integrity and Auto-Negotiation Solution...........................................18

4.5.1 Link Integrity...............................................................................................18

4.5.2 Auto-Negotiation ........................................................................................18

4.5.3 Combination Tx/T4 Auto-Negotiation Solution...........................................18

4.6 Auto 10/100 Mbps Speed Selection..............................................................................19

4.7 Adapter Mode Addresses.......................... ...... ..............................................................19

5.0 10BASE-T FUNCTIONALITY IN ADAPTER MODE ..................................................................21

5.1 10BASE-T Transmit Clock Generation..........................................................................21

5.2 10BASE-T Transmit Blocks...........................................................................................21

5.2.1 10BASE-T Manchester Encoder................................................................21

5.2.2 10BASE-T Driver and Filter .......................................................................21

5.3 10BASE-T Receive Blocks............................................................................................21

5.3.1 10BASE-T Manchester Decoder................................................................21

5.3.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter............21

Datasheet iii

82555 — Networking Silicon

Contents

5.3.3 10BASE-T Error Detection and Reporting .................................................22

5.4 10BASE-T Collision Detection.......................................................................................22

5.5 10BASE-T Link Integrity................................................................................................22

5.6 10BASE-T Jabber Control Function..............................................................................22

5.7 10BASE-T Full Duplex ..................................................................................................23

6.0 REPEATER MODE....................................................................................................................25

6.1 Special Repeater Features............................................................................................25

6.2 Connectivity...................................................................................................................25

7.0 MANAGEMENT DATA INTERFACE..........................................................................................27

7.1 MDI Frame Structure.....................................................................................................27

7.2 MDI Registers................................................................................................................28

7.2.1 MDI Registers 0 - 7....................................................................................28

7.2.2 MDI Registers 8 - 15..................................................................................31

7.2.3 MDI Registers 16 - 31................................................................................31

8.0 AUTO-NEGOTIATION FUNCTIONALITY..................................................................................35

8.1 Description ....................................................................................................................35

8.2 Parallel Detect and Auto-Negotiation............................................................................36

9.0 LED DESCRIPTIONS ................................................................................................................39

10.0 RESET AND MISCELLANEOUS TEST MODES.......................................................................41

10.1 Reset.............................................................................................................................41

10.2 Loopback.......................................................................................................................41

10.3 Scrambler Bypass .........................................................................................................41

10.4 Test Port........................................................................................................................41

11.0 ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS..............................................43

11.1 Absolute Maximum Ratings ..........................................................................................43

11.2 General Operating Conditions ........................... ...... ....... ...... ....... ...... ....... ...... ....... .......43

11.3 DC Characteristics ............................................. ...... ....... ...... ....... ...... ....... ...... ....... ...... .43

11.3.1 MII DC Characteristics ..............................................................................43

11.3.2 10BASE-T Voltage/Current DC Characteristics ........................................43

11.3.3 100BASE-TX Voltage/Current DC Characteristics .................................. .44

11.4 AC Characteristics.........................................................................................................45

11.4.1 MII Clock Specifications.............................................................................45

11.4.2 MII Timing Parameters ..............................................................................46

11.4.3 Repeater Mode Timing Parameters ..........................................................47

11.4.4 Transmit Packet Timing Parameters .........................................................48

11.4.5 Squelch Test Timing Parameters ..............................................................48

11.4.6 Jabber Timing Parameters ........................................................................49

11.4.7 Receive Packet Timing Parameters ..........................................................49

11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters .........................50

11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ....................50

11.4.10 Reset Timing Parameters .........................................................................51

11.4.11 X1 Clock Specifications ............................................................................51

11.4.12 100BASE-TX Transmitter AC Specification ..............................................52

12.0 82555 PACKAGE INFORMATION.............................................................................................53

Datasheet

1.0 Introduction

The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications . 100B ASE-TX is an IEEE 802.3 physical layer s peci fication for use o v er t wo pairs of Category 5 unshielded twist ed pair or Type 1 shielded twisted pair cable. 100BASE-TX defines a signaling scheme not only for 100 Mbps, but also provides CSMA/CD compatibility with the 10 Mbps IEEE 802.3 10BASE-T signaling stand ard.

1.1 Functional Overview

The 82555 is designed to work in two modes: Data Terminal Equipment (DTE) for adapters and repeater for hubs and switches. When configured to DTE (adapter) mode, the 82555 incorporates all active circuitry required to interface 10/100 Mbps Ethernet controllers and CSMA/CD MAC components to 10 Mbps and 100 Mbps networks. In this and other documents the 82555 may be referred to as the DTE, Physical Medium Device (PMD), or Physical Layer Medium (PLM). It supports a direct glueless interface to Intel components such as the 82557 Fast Ethernet controller. The 82555 also supports the Media Independent Interface (MII) signals as specified in the IEEE

802.3u standard. The figure below shows how the 82555 fits into a 10/100 Mbps Ethernet adapter design.

Networking Silicon — 82555

Controller/MAC

System Bus Interface

Intel 82555

Figure 1. 82555 10/100 Mbps Ethernet Solution

When configured to repeater mo de, the 82555 incorporates sev eral f eatures that allo w it to f unction as a Class I or MII level repeater. Section 6.0, “Repeater Mode” on page 25 describes the 82555 in a repeater type of application.

1.2 Compliance to Industry Standards

When operating in 100 Mbps mode, the 82555 complies with IEEE 802.3u 100BASE-TX specification. The PMD section with the related changes established in 802.3u 100BASE-TX complies with ANSI X3.263:1995 TP-PMD, Revision 2.2.

When operating in the 10 Mbps mode, the 82555 complies with the IEEE 802.3 10BASE-T specification.

Pair 1

Pair 2

netics

Datasheet 1

82555 — Networking Silicon

The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media Independent Interface (MII) standard.

Datasheet

2.0 Architectural Overview

The 82555 is an advanced combin ation of both digital and an alog logic which combine to pro vide a functional stack between the Media Independent Interface (MII) and the wire through the magnetics. Figure 2 shows a general block diagram of the 82555 component.

Networking Silicon — 82555

Figure 2. 82555 Simplified Block Diagram

2.1 100 Mbps Mode

In 100BASE-TX mode the 82555 digital subsection performs all signal processing of digital data obtained from the analog reception and the data to be driven into the analog transmit subsection. This includes 4B/5B encoding/deco ding, scrambling/descrambling, carrier sense, collision detection, link detection, Auto-Negotiation, data validation, and providing MII to the Media Access Controller (MAC). The 82555 supports the IEEE defined MII as its MAC interface and expects the controller to drive the Management Data Input/Output and Management Data Clock signals to perform the management functions.

In 100BASE-TX mode, the analog subsection of the 82555 performs two functions:

Transmit: The 82555 converts a digital 125 Mbps stream into MLT-3 format and drives it

•

through the transmit differential pair onto the physical medium.

Datasheet 3

82555 — Networking Silicon

Receive: The 82555 takes receive analog MLT-3 data from the receive differential pair and

•

converts it into a digital 125 Mbps stream, recovering both clock and data signals.

MII TX Interface

4b/5b

Encoding

Scrambler

Serialization NRZ to NRZI

NRZI to MLT3

Magnetics Module

12345678

MII RX Interface

4b/5b

Decoding

De-scrambler

Serial to 5B NRZI to NRZ

MLT3 to NRZI

RJ-45 Connector

Figure 3. 82555 Analog Logic

2.2 10 Mbps Mode

The 82555 operation in 1 0BASE-T mode is similar to the 82555 operation in 100BASE-TX mode. Manchester encoding and decoding is used instead of 4B/5B encoding/decoding and scrambling/ descrambling. In addition, the Transmit Clock and Receive Clock (MII clock signals) provide 2.5 MHz instead of 25 MHz.

Datasheet

Networking Silicon — 82555

(

)

The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well as any MII compatible device. Figure 4 shows a schematic-level diagram of the 82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface.

Flash

(optional)

82557

EEPROM

optional

RXD[3:0]

RXERR

RXDV

TXD[3:0]

TXEN

MDIO

RESET

PCI Bus Signals

Figure 4. Intel 82557/82555 Solution

2.3 Media Independent Interface (MII)

RXC

CRS COL

TXC

MDC

82555

The 82555 supports the Media Independent Interface (MII) as its primary interface to the MAC. The MII Interface is summarized in Table 1.

Table 1. 82555 MII

Signal Name

TXC Transmit Cloc k

TXD[3:0] Transmit Data From MAC TXC Yes TXEN Transmit Enable From MAC TXC Yes COL Collision Detect From 82555 Asynchronous Yes CRS Carrier Sense From 82555 Asynchronous Yes RXC Receive Clock From 82555 -- Yes RXD[3:0] Receive Data From 82555 RXC Yes RXDV Receive Data Valid From 82555 RXC Yes RXERR Receive Error From 82555 RXC Yes

MDC

MDIO

Description Direction

From 82555 (adapter mode only)

Management Data Clock

Management Data Input/Output

From manager -- Yes

From manager MDC Yes

Clock

Reference

-- Yes

MII Signal Supported

by the 82555?

Datasheet 5

82555 — Networking Silicon

Table 1. 82555 MII

Signal

Name

TXERR

Description Direction

Transmit Err or (repeater mode only)

From RIC TXC Yes

Clock

Reference

MII Signal Supported

by the 82555?

Datasheet

3.0 Pin Definitions

All active digital pins are defined to have transistor-to-transistor logic voltage levels except the X1 and X2 crystal signals. The transmit differential and recei ve d iffer ential pins are specifi ed as analog outputs and inputs, respectively.

The figure below show the pin locations on the 82555 component. The following subsections describe the pin functions .

Networking Silicon — 82555

Figure 5. 82555 Pin Numbers and Labels

Datasheet 7

82555 — Networking Silicon

Pin allocation is based on a 100-lead quad flat package. All pin locations are based on printed circuit board layout and other design constraints.

3.1 Pin Types

Pin Type Description

I This type of pin is an input pin to the 82555. O This type of pin is an output pin from the 82555. I/O This type of pin is both an input and output pin for the 82555. B This pin is used as a bias pin. The bias pin is either pulled up or do wn with a resistor. The bias pin

may also be used as an external voltage reference.

3.2 Clock Pins

Symbol Pin Type Name and Function

X1 56 I

X2 55 O

Crystal Input One.

Otherwise, X1 may be driven by an external MOS level 25 MHz oscillator when X2 is left floating. (The crystal should have a tolerance of 50 PPM or better.)

Crystal Output Two.

crystal. Otherwise, X1 may be driven by an external MOS level 25 MHz oscillator when this pin is left floating.

X1 and X2 can be driven by an external 25 MHz crystal.

X1 and X2 can be driven by an external 25 MHz

3.3 Twisted Pair Ethernet (TPE) Pins

Symbol Pin Type Name and Function

TDP TDN

RDP RDN

47 48

33 34

Transmit Differential Pair.

transmission on an unshielded twisted pair (UTP) cable. The current-driven differential driver can be two-level (10BASE-T or Manchester) or three-level (100BASE-TX or MLT-3) signals depending on the operating mode. These signals interface directly with an isolation transformer.

Receive Differential Pair.

isolation transformer. The bitstream can be two-level (10BASE-T or manchester) or three-level (100BASE-TX or MLT-3) signals depending on the operating mode.

These pins send the serial bitstream for

These pins receive the serial bitstream from the

3.4 Media Independent Interface (MII) Pins

Symbol Pin Type Name and Function

RXD3 RXD2 RXD1 RXD0

97 96 95 92

Receive Data.

these four lines one nibble at a time.

In 100 Mbps and 10 Mbps mode, data is transferred across

Datasheet

Networking Silicon — 82555

Symbol Pin Type Name and Function

RXC 90 O

RXDV 86 O

RXERR 87 O

TXD3 TXD2 TXD1 TXD0

TXC 60 I/O

TXEN 79 I

TXERR 59 I

CRS 82 O

COL 85 O

MDIO 80 I/O

MDC 81 II

71 70 69 68

Receive Clock.

depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps). The Receive Clock is recovered directly from incoming data and is continuous into the Media Access Controller (MAC). Thus, it must be resynchronized in 10 Mbps mode at the start of each incoming packet.

Receive Data Valid.

RSC[3:0] pins are valid.

Receive Error.

occurred during frame reception.

T ransmit Data.

these four lines one nibble at a time.

T ransmit Clock.

depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps). The Transmit Clock outputs a continuous clock into the MAC that is generated directly from the external clock source in DTE (adapter) mode. In repeater mode, the TXC is an input signal operating at either 25 MHz or 2.5 MHz depending on the operating speed, which is typically clocked by a receiver interface de vice .

T ransmit Enabl e.

valid data is present on the TXD[3:0] pins.

T ransmit Error.

occurred during transmissions of a frame.

Carrier Sense.

present on the link. CRS is an asynchronous output signal.

Collision Detect.

and indicates to the 82555 that a collision has occurred on the link. COL i s an asynchronous output signal to the controller.

Management Data Input/Output.

for the Management Data Interface (MDI).

Management Data Clock.

the MDIO signal. MDC should operate at a maximum frequency of 2.5 MHz

The Receive Clock may be either 25 MHz or 2.5 MHz

This signal indicates that the incoming data on the

The RXERR signal indicates to the 82555 that an error has

In 100 Mbps and 10 Mbps mode, data is transferred across

The Transmit Clock may be either 25 MHz or 2.5 MHz

The Transmit Enable signal indicates to the 82555 that

The TXERR signal indicates to the 82555 that an error has

The Carrier Sense signal indicates to the 82555 that traffic is

The Collision Detect signal operates in half duplex mode

The MDIO signal is a bidirectional data pin

The MDC signal functions as a clock reference for

3.5 Media Access Control/Repeater Interface Control Pins

Symbol Pin Type Name and Function

RXCONG 77 I

PORTEN 76 I

Receive Congestion.

active high and indicates an overrun on the controller receive side:

• Full duplex PHY Base (Bay Technologies) flow control DTE (adapter) mode

• Full duplex signal (FDX_N) is high

• Full duplex technology is active through Auto-Negotiation

Port Enable.

signals will be tri-stated: RXD[3:0], RXC, RXDV, and RXERR.

In repeater mode when the PORTEN signal is low, the follo wing

Datasheet 9

If the following conditions exist, the RXCONG is an

82555 — Networking Silicon

Symbol Pin Type Name and Function

TXRDY (TOUT)

FDX_N 5 I/O

4 O This pin is multiplexed and can be used for one of the following:

3.6 LED Pins

Symbol Pin Type Name and Function

ACTLED 12 O

LILED 11 O

SPEEDLED

13 O Speed LED

T ransmit Ready.

modes are enabled, the TXRDY signal enables transmission while it is asserted.

When the Test Enable signal is activated, this signal functions as the

TOUT .

Test Output port.

Full Duplex.

result of the duplex configuration to the MAC. This pin can also operate as the LED driver and will be an active low for all technologies.

In repeater mode, this signal is used for Auto-Negotiation advertisement to the 82555’s link partner and activates the PHY Base (Bay Technologies) flow control if 100BASE-TX full duplex is the highest common technology between the 82555 and its link partner.

Activity LED.

activity is present, the ACTLED is on. When no activity is present, the ACTLED is off.

Link Integrity LED.

present in either 10 Mbps or 100 Mbps, the LILED is on; and if an invalid link is preset, LILED is off.

For a combination design board, the LILED should be connected to the TX technology LED.

This signal is used to indicate the speed of operation. For 100 Mbps, the SPEEDLED will be on; and for 10 Mbps, the SPEEDLED will be off.

If full duplex and PHY Base (Bay T echnologies) flow control

In DTE (adapter) mode, this active lo w output signal reports the

This signal indicates either transmit or receive activity. When

This signal indicates the link integrity. If a valid link is

3.7 External Bias Pins

Symbol Pin Type Name and Function

RBIAS100 44 B

RBIAS10 43 B

PD1 42 I

PD2 100 I

Note: The resistor values described for the external bias pins are only recommended values and may

require to be fine tuned for various designs.

Bias Reference Resistor 100.

this pin to ground.

Bias Reference Resistor 10.

this pin to ground.

Pull Down One.

ground.

Pull Down One.

ground.

A 10 KΩ resistor should be connected from this pin to

A 1 KΩ resistor should be connected from this pin to

Datasheet

A 634 Ω resistor should be connected from

A 768 Ω resistor should be connected from

3.8 Miscellaneous Control Pins

Symbol Pin Type Name and Function

RESET 1 I

FRC100

(MACTYP)

PHYA4 (TIN)

PHYA3

(SLVTRI)

PHYA2

(LISTAT)

PHYA1

(TEXEC)

PHYA0

(TCK)

ANDIS

(T4ADV)

SCRMBY 23 I

LPBK 2 I

RPT 50 I

TESTEN 21 I

51 I This pin is multiplexed and can be used for one of the following:

22 I This pin is multiplexed and can be used for one of the following:

52 I/O This pin is multiplexed and can be used for one of the following:

6 I This pin is multiplexed and can be used for one of the following:

25 I This pin is multiplexed and can be used for one of the following:

24 I This pin is multiplexed and can be used for one of the following:

54 I This pin is multiplexed and can be used for one of the following:

The Reset signal is active high and resets the 82555. A reset pulse

Reset.

width of at least 1 µs should be used.

Force 100/10 Mbps.

either 100 Mbps (active high) or to 10 Mbps (active low).

MAC Type.

82555 drives 82557 mode. If this input signal is low, the 82555 drives a generic MII MAC mode.

PHY Address 4.

address port configuration.

TIN.

data.

PHY Address 3.

address port configuration.

Slave T ri - state.

with the T4 Advanced signal. When both are active, the slave PHY is inactive and tri-states all its outputs.

PHY Address 2.

address port configuration.

Link Status.

signal is active low and the slave PHY link is valid.

PHY Address 1.

address port configuration.

Test Execute.

execution command indicating that the pin 22 is being used as the Test Input pin.

PHY Address 0.

address port configuration.

Test Clock.

signal.

Auto-Negotiation Disable.

for management reasons. If this input signal is high, the Auto-Negotiation operation will be disabled.

T4ADV.

allows the LISTAT and SLVTRI pins to be used as interface to the slave PHY.

Scrambler/Descrambler Bypass.

descrambler of TP-PMD will be bypassed.

Loopback.

diagnostic loopback function.

Repeater.

mode. When this signal is low, the 82555 runs in DTE (adapter) mode.

Test.

In DTE (adapter) full duplex mode, if this input signal is high, the

If the Test Enable signal is active, this signal is used as the Test Input

In DTE (adapter) mode, this output operates in conjunction

In DTE (adapter) mode, if T4 Advance is active, the LISTAT _N

If Test Enable is asserted, this signal acts as the test

If Test Enable is asserted, this signal acts as the Test Clock

In DTE (adapter) mode, this pin enables the combo mode. This

When the LPBK signal is high, the 82555 will perform a

When the RPT signal is high, the 82555 functions in repeater

If the TESTEN signal is high, the 82555 enables the test ports.

Networking Silicon — 82555

In repeater mode, this pin configures the repeater to

In repeater mode, this signal represents the fifth bit for

In repeater mode, this signal represents the fourth bit for

In repeater mode, this signal represents the third bit for

In repeater mode, this signal represents the second bit for

In repeater mode, this signal represents the first bit for

In repeater mode, the Auto-Negotiation operates

If SCRMBY is high, the scrambler/

Datasheet 11

82555 — Networking Silicon

3.9 Power and Gr ound Pins

Symbol Pin Type Name and Function

VCC 7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58, 62,

64, 66, 73, 75, 83, 88, 93, 98

VSS 3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39,

41, 46, 49, 53, 57, 61, 63, 65, 67, 72, 74, 78, 84, 89, 91, 94, 99

I Power: +5 V ± 5%

I Ground: 0 V

Datasheet

Networking Silicon — 82555

4.0 100BASE-TX Adapter Mode Operation

4.1 100BASE-TX Transmit Clock Generation

A 25 MHz crystal or a 25 MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555 derives its internal transmit digital clocks from this crystal or oscillator input. The Transmit Clock signal is a derivativ e of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± 0.0005% (50 PPM).

4.2 100BASE-TX Transmit Blocks

The transmit subsection of the 82555 accepts nibble-wide data on the TXD[3:0] lines when TXEN is asserted (high). The transmit subsection passes data unconditionally to the 4B/5B encoder as long as TXEN is active.

The 4B/5B encoder accepts nibble-wide data (4 bits) from the MA C and compiles it into 5-bit-wide parallel symbols. These symbols are scrambled and serialized into a 125 Mbps bit stream, converted by the analog transmit driver into a MLT-3 waveform format, and transmitted onto the Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire.

4.2.1 100BASE-TX 4B/5B Encoder

The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard . Fo ur bits are encoded according to the transmit 4B/5B lookup table. The lookup table matches a 5-bit code to each 4-bit code.

The table below illustrates the 4B/5B encoding scheme associated with the given symbol.

Symbol 5B Symbol Code 4B Nibble Code

0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101

Table 2. 4B/5B Encoder

Datasheet 13

82555 — Networking Silicon

Table 2. 4B/5B Encoder

Symbol 5B Symbol Code 4B Nibble Code

E 11100 1110 F 11101 1111

I 11111

J 11000

K 10001 T 01101 1st End of Packet Symbol

R 00111 V 00000 INVALID

V 00001 INVALID V 00010 INVALID V 00011 INVALID H 00100 INVALID V 00101 INVALID V 00110 INVALID V 01000 INVALID V 01100 INVALID V 10000 Flow Control S V 11001 INVALID

Inter Pack et Idle Symbol (No 4B)

1st Start of Packet Symbol 0101

2nd Start of Packet Symbol 0101

2nd End of Packet Symbol and Flow Control

4.2.2 100BASE-TX Scrambler and MLT-3 Encoder

Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82555 implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. The cipher equation used is:

X[n] = X[n-11] + X[n-9] (mod 2)

The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZI coding, but three levels are output instead of two. There are three output levels: positive, negative and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is

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