for 10BASE-T half and full duplex,
100BASE-TX half and full duplex, and
100BASE-T4 configurations
—Parallel detection algorithm for legacy
support of non-Auto-Negot ia ti on
enabled link partner
—Integrated 10BASE-T transcei v er with
built in transmit and receive filters
—Glueless interface to T4-PHY for
combination TX/T4 designs with single
magnetics
—Glueless support for 4 LEDs: activity,
link, speed, and duplex
—LED function mapping support via MDI
—Low external component count
—Single 25 MHz clock support for 10
Mbps and 100 Mbps (crystal or
oscillator)
—Single magnetics for 10 Mbps and 100
Mbps operation
—QFP 100-pin package
■
Performance enhancements
—Flow control support for IEEE 802.3x
Auto-Negotiation and Bay Technologies
PHY Base* scheme
—Adaptive Channel Equalizer for greater
functionality over varying cable lengths
—High tolerance to extreme noise
conditions
—Very lo w emissions
—Jabber control circuitry to prevent data
loss in 10 Mbps operation
—Auto-polarity correction for 10BASE-T
—Software compatible with 82557 drivers
■
Repeater functionality
—Repeater mode operation
—Support for forced speed of 10 Mbps
and 100 Mbps
—Automatic carrier disconnect for IEEE
802.3u compliance
—Auto-Negotiation enable/disable
capability
—Receive port enable function
—Support for 32 configurable addresses
—Narrow analog side (14 mm) for tight
packing in repeater and switch designs
Notice:
Notice:
Document Number: 666252-004
Revision 2.0
March 1998
82555 — Networking Silicon
■
Low power consumption
—Typical total solution power including
all resistors and magnetics:
- 275 mA 100BASE-TX
- 230 mA 10BASE-T
- 250 mA Auto-Negotiation
—300 mA maximum total solution power
in DTE (adapter) mode
—Power-down of 10BASE-T/100BASE-
■
Added modes for design, testing, and
manufacturability
—Test Access Port (TAP)
- NAND Tree
- Board Level Functional Test (BIST)
—Programmable bypass for 4B/5B
encoding/decoding and scrambler/
descrambler
—Diagnostic loopback mode
TX sections when not in use
Revision Hist ory
Revision
Date
Jan. 19971.0First external release of the preliminary datasheet
Apr. 19971.1First release edition
Mar. 19982.0General editing
RevisionDescription
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any f e atures or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps
Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications . 100B ASE-TX is
an IEEE 802.3 physical layer s peci fication for use o v er t wo pairs of Category 5 unshielded twist ed
pair or Type 1 shielded twisted pair cable. 100BASE-TX defines a signaling scheme not only for
100 Mbps, but also provides CSMA/CD compatibility with the 10 Mbps IEEE 802.3 10BASE-T
signaling stand ard.
1.1Functional Overview
The 82555 is designed to work in two modes: Data Terminal Equipment (DTE) for adapters and
repeater for hubs and switches. When configured to DTE (adapter) mode, the 82555 incorporates
all active circuitry required to interface 10/100 Mbps Ethernet controllers and CSMA/CD MAC
components to 10 Mbps and 100 Mbps networks. In this and other documents the 82555 may be
referred to as the DTE, Physical Medium Device (PMD), or Physical Layer Medium (PLM). It
supports a direct glueless interface to Intel components such as the 82557 Fast Ethernet controller.
The 82555 also supports the Media Independent Interface (MII) signals as specified in the IEEE
802.3u standard. The figure below shows how the 82555 fits into a 10/100 Mbps Ethernet adapter
design.
Networking Silicon — 82555
Controller/MAC
System Bus Interface
Intel 82555
Figure 1. 82555 10/100 Mbps Ethernet Solution
When configured to repeater mo de, the 82555 incorporates sev eral f eatures that allo w it to f unction
as a Class I or MII level repeater. Section 6.0, “Repeater Mode” on page 25 describes the 82555 in
a repeater type of application.
1.2Compliance to Industry Standards
When operating in 100 Mbps mode, the 82555 complies with IEEE 802.3u 100BASE-TX
specification. The PMD section with the related changes established in 802.3u 100BASE-TX
complies with ANSI X3.263:1995 TP-PMD, Revision 2.2.
When operating in the 10 Mbps mode, the 82555 complies with the IEEE 802.3 10BASE-T
specification.
Ma
Pair 1
Pair 2
netics
Datasheet1
82555 — Networking Silicon
The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex
Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media
Independent Interface (MII) standard.
2
Datasheet
2.0Architectural Overview
The 82555 is an advanced combin ation of both digital and an alog logic which combine to pro vide a
functional stack between the Media Independent Interface (MII) and the wire through the
magnetics. Figure 2 shows a general block diagram of the 82555 component.
Networking Silicon — 82555
Figure 2. 82555 Simplified Block Diagram
2.1100 Mbps Mode
In 100BASE-TX mode the 82555 digital subsection performs all signal processing of digital data
obtained from the analog reception and the data to be driven into the analog transmit subsection.
This includes 4B/5B encoding/deco ding, scrambling/descrambling, carrier sense, collision
detection, link detection, Auto-Negotiation, data validation, and providing MII to the Media
Access Controller (MAC). The 82555 supports the IEEE defined MII as its MAC interface and
expects the controller to drive the Management Data Input/Output and Management Data Clock
signals to perform the management functions.
In 100BASE-TX mode, the analog subsection of the 82555 performs two functions:
Transmit: The 82555 converts a digital 125 Mbps stream into MLT-3 format and drives it
•
through the transmit differential pair onto the physical medium.
Datasheet3
82555 — Networking Silicon
Receive: The 82555 takes receive analog MLT-3 data from the receive differential pair and
•
converts it into a digital 125 Mbps stream, recovering both clock and data signals.
MII TX Interface
4b/5b
Encoding
Scrambler
Serialization
NRZ to NRZI
NRZI to MLT3
Magnetics Module
12345678
MII RX Interface
4b/5b
Decoding
De-scrambler
Serial to 5B
NRZI to NRZ
MLT3 to NRZI
RJ-45 Connector
Figure 3. 82555 Analog Logic
2.210 Mbps Mode
The 82555 operation in 1 0BASE-T mode is similar to the 82555 operation in 100BASE-TX mode.
Manchester encoding and decoding is used instead of 4B/5B encoding/decoding and scrambling/
descrambling. In addition, the Transmit Clock and Receive Clock (MII clock signals) provide 2.5
MHz instead of 25 MHz.
4
Datasheet
Networking Silicon — 82555
(
)
The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet
Controller, as well as any MII compatible device. Figure 4 shows a schematic-level diagram of the
82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface.
Flash
(optional)
82557
EEPROM
optional
RXD[3:0]
RXERR
RXDV
TXD[3:0]
TXEN
MDIO
RESET
PCI Bus Signals
Figure 4. Intel 82557/82555 Solution
2.3Media Independent Interface (MII)
RXC
CRS
COL
TXC
MDC
82555
The 82555 supports the Media Independent Interface (MII) as its primary interface to the MAC.
The MII Interface is summarized in Table 1.
All active digital pins are defined to have transistor-to-transistor logic voltage levels except the X1
and X2 crystal signals. The transmit differential and recei ve d iffer ential pins are specifi ed as analog
outputs and inputs, respectively.
The figure below show the pin locations on the 82555 component. The following subsections
describe the pin functions .
Networking Silicon — 82555
Figure 5. 82555 Pin Numbers and Labels
Datasheet7
82555 — Networking Silicon
Pin allocation is based on a 100-lead quad flat package. All pin locations are based on printed
circuit board layout and other design constraints.
3.1Pin Types
Pin TypeDescription
IThis type of pin is an input pin to the 82555.
OThis type of pin is an output pin from the 82555.
I/OThis type of pin is both an input and output pin for the 82555.
BThis pin is used as a bias pin. The bias pin is either pulled up or do wn with a resistor. The bias pin
may also be used as an external voltage reference.
3.2Clock Pins
SymbolPinTypeName and Function
X156I
X255O
Crystal Input One.
Otherwise, X1 may be driven by an external MOS level 25 MHz oscillator
when X2 is left floating. (The crystal should have a tolerance of 50 PPM or
better.)
Crystal Output Two.
crystal. Otherwise, X1 may be driven by an external MOS level 25 MHz
oscillator when this pin is left floating.
X1 and X2 can be driven by an external 25 MHz crystal.
X1 and X2 can be driven by an external 25 MHz
3.3Twisted Pair Ethernet (TPE) Pins
SymbolPinTypeName and Function
TDP
TDN
RDP
RDN
47
48
33
34
O
I
Transmit Differential Pair.
transmission on an unshielded twisted pair (UTP) cable. The current-driven
differential driver can be two-level (10BASE-T or Manchester) or three-level
(100BASE-TX or MLT-3) signals depending on the operating mode. These
signals interface directly with an isolation transformer.
Receive Differential Pair.
isolation transformer. The bitstream can be two-level (10BASE-T or
manchester) or three-level (100BASE-TX or MLT-3) signals depending on the
operating mode.
These pins send the serial bitstream for
These pins receive the serial bitstream from the
3.4Media Independent Interface (MII) Pins
SymbolPinTypeName and Function
RXD3
RXD2
RXD1
RXD0
97
96
95
92
O
Receive Data.
these four lines one nibble at a time.
In 100 Mbps and 10 Mbps mode, data is transferred across
8
Datasheet
Networking Silicon — 82555
SymbolPinTypeName and Function
RXC90O
RXDV86O
RXERR87O
TXD3
TXD2
TXD1
TXD0
TXC60I/O
TXEN79I
TXERR59I
CRS82O
COL85O
MDIO80I/O
MDC81II
71
70
69
68
I
Receive Clock.
depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5
MHz for 10 Mbps). The Receive Clock is recovered directly from incoming
data and is continuous into the Media Access Controller (MAC). Thus, it must
be resynchronized in 10 Mbps mode at the start of each incoming packet.
Receive Data Valid.
RSC[3:0] pins are valid.
Receive Error.
occurred during frame reception.
T ransmit Data.
these four lines one nibble at a time.
T ransmit Clock.
depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5
MHz for 10 Mbps). The Transmit Clock outputs a continuous clock into the
MAC that is generated directly from the external clock source in DTE
(adapter) mode. In repeater mode, the TXC is an input signal operating at
either 25 MHz or 2.5 MHz depending on the operating speed, which is
typically clocked by a receiver interface de vice .
T ransmit Enabl e.
valid data is present on the TXD[3:0] pins.
T ransmit Error.
occurred during transmissions of a frame.
Carrier Sense.
present on the link. CRS is an asynchronous output signal.
Collision Detect.
and indicates to the 82555 that a collision has occurred on the link. COL i s an
asynchronous output signal to the controller.
Management Data Input/Output.
for the Management Data Interface (MDI).
Management Data Clock.
the MDIO signal. MDC should operate at a maximum frequency of 2.5 MHz
The Receive Clock may be either 25 MHz or 2.5 MHz
This signal indicates that the incoming data on the
The RXERR signal indicates to the 82555 that an error has
In 100 Mbps and 10 Mbps mode, data is transferred across
The Transmit Clock may be either 25 MHz or 2.5 MHz
The Transmit Enable signal indicates to the 82555 that
The TXERR signal indicates to the 82555 that an error has
The Carrier Sense signal indicates to the 82555 that traffic is
The Collision Detect signal operates in half duplex mode
The MDIO signal is a bidirectional data pin
The MDC signal functions as a clock reference for
3.5Media Access Control/Repeater Interface Control Pins
SymbolPinTypeName and Function
RXCONG77I
PORTEN76I
Receive Congestion.
active high and indicates an overrun on the controller receive side:
• Full duplex PHY Base (Bay Technologies) flow control DTE (adapter)
mode
• Full duplex signal (FDX_N) is high
• Full duplex technology is active through Auto-Negotiation
Port Enable.
signals will be tri-stated: RXD[3:0], RXC, RXDV, and RXERR.
In repeater mode when the PORTEN signal is low, the follo wing
Datasheet9
If the following conditions exist, the RXCONG is an
82555 — Networking Silicon
SymbolPinTypeName and Function
TXRDY
(TOUT)
FDX_N5I/O
4OThis pin is multiplexed and can be used for one of the following:
3.6LED Pins
SymbolPinTypeName and Function
ACTLED12O
LILED11O
SPEEDLED
13OSpeed LED
T ransmit Ready.
modes are enabled, the TXRDY signal enables transmission while it is
asserted.
When the Test Enable signal is activated, this signal functions as the
TOUT .
Test Output port.
Full Duplex.
result of the duplex configuration to the MAC. This pin can also operate as
the LED driver and will be an active low for all technologies.
In repeater mode, this signal is used for Auto-Negotiation advertisement to
the 82555’s link partner and activates the PHY Base (Bay Technologies) flow
control if 100BASE-TX full duplex is the highest common technology between
the 82555 and its link partner.
Activity LED.
activity is present, the ACTLED is on. When no activity is present, the
ACTLED is off.
Link Integrity LED.
present in either 10 Mbps or 100 Mbps, the LILED is on; and if an invalid link
is preset, LILED is off.
For a combination design board, the LILED should be connected to the TX
technology LED.
This signal is used to indicate the speed of operation. For 100 Mbps, the
SPEEDLED will be on; and for 10 Mbps, the SPEEDLED will be off.
If full duplex and PHY Base (Bay T echnologies) flow control
In DTE (adapter) mode, this active lo w output signal reports the
This signal indicates either transmit or receive activity. When
This signal indicates the link integrity. If a valid link is
3.7External Bias Pins
SymbolPinTypeName and Function
RBIAS100 44B
RBIAS1043B
PD142I
PD2100I
Note:The resistor values described for the external bias pins are only recommended values and may
require to be fine tuned for various designs.
10
Bias Reference Resistor 100.
this pin to ground.
Bias Reference Resistor 10.
this pin to ground.
Pull Down One.
ground.
Pull Down One.
ground.
A 10 KΩ resistor should be connected from this pin to
A 1 KΩ resistor should be connected from this pin to
Datasheet
A 634 Ω resistor should be connected from
A 768 Ω resistor should be connected from
3.8Miscellaneous Control Pins
SymbolPinTypeName and Function
RESET1I
FRC100
(MACTYP)
PHYA4
(TIN)
PHYA3
(SLVTRI)
PHYA2
(LISTAT)
PHYA1
(TEXEC)
PHYA0
(TCK)
ANDIS
(T4ADV)
SCRMBY23I
LPBK2I
RPT50I
TESTEN21I
51IThis pin is multiplexed and can be used for one of the following:
22IThis pin is multiplexed and can be used for one of the following:
52I/OThis pin is multiplexed and can be used for one of the following:
6IThis pin is multiplexed and can be used for one of the following:
25IThis pin is multiplexed and can be used for one of the following:
24IThis pin is multiplexed and can be used for one of the following:
54IThis pin is multiplexed and can be used for one of the following:
The Reset signal is active high and resets the 82555. A reset pulse
Reset.
width of at least 1 µs should be used.
Force 100/10 Mbps.
either 100 Mbps (active high) or to 10 Mbps (active low).
MAC Type.
82555 drives 82557 mode. If this input signal is low, the 82555 drives a
generic MII MAC mode.
PHY Address 4.
address port configuration.
TIN.
data.
PHY Address 3.
address port configuration.
Slave T ri - state.
with the T4 Advanced signal. When both are active, the slave PHY is inactive
and tri-states all its outputs.
PHY Address 2.
address port configuration.
Link Status.
signal is active low and the slave PHY link is valid.
PHY Address 1.
address port configuration.
Test Execute.
execution command indicating that the pin 22 is being used as the Test Input
pin.
PHY Address 0.
address port configuration.
Test Clock.
signal.
Auto-Negotiation Disable.
for management reasons. If this input signal is high, the Auto-Negotiation
operation will be disabled.
T4ADV.
allows the LISTAT and SLVTRI pins to be used as interface to the slave PHY.
Scrambler/Descrambler Bypass.
descrambler of TP-PMD will be bypassed.
Loopback.
diagnostic loopback function.
Repeater.
mode. When this signal is low, the 82555 runs in DTE (adapter) mode.
Test.
In DTE (adapter) full duplex mode, if this input signal is high, the
If the Test Enable signal is active, this signal is used as the Test Input
In DTE (adapter) mode, this output operates in conjunction
In DTE (adapter) mode, if T4 Advance is active, the LISTAT _N
If Test Enable is asserted, this signal acts as the test
If Test Enable is asserted, this signal acts as the Test Clock
In DTE (adapter) mode, this pin enables the combo mode. This
When the LPBK signal is high, the 82555 will perform a
When the RPT signal is high, the 82555 functions in repeater
If the TESTEN signal is high, the 82555 enables the test ports.
Networking Silicon — 82555
In repeater mode, this pin configures the repeater to
In repeater mode, this signal represents the fifth bit for
In repeater mode, this signal represents the fourth bit for
In repeater mode, this signal represents the third bit for
In repeater mode, this signal represents the second bit for
In repeater mode, this signal represents the first bit for
A 25 MHz crystal or a 25 MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555
derives its internal transmit digital clocks from this crystal or oscillator input. The Transmit Clock
signal is a derivativ e of the 25 MHz internal clock. The accuracy of the external crystal or oscillator
must be ± 0.0005% (50 PPM).
4.2100BASE-TX Transmit Blocks
The transmit subsection of the 82555 accepts nibble-wide data on the TXD[3:0] lines when TXEN
is asserted (high). The transmit subsection passes data unconditionally to the 4B/5B encoder as
long as TXEN is active.
The 4B/5B encoder accepts nibble-wide data (4 bits) from the MA C and compiles it into 5-bit-wide
parallel symbols. These symbols are scrambled and serialized into a 125 Mbps bit stream,
converted by the analog transmit driver into a MLT-3 waveform format, and transmitted onto the
Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire.
4.2.1100BASE-TX 4B/5B Encoder
The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard . Fo ur bits are encoded
according to the transmit 4B/5B lookup table. The lookup table matches a 5-bit code to each 4-bit
code.
The table below illustrates the 4B/5B encoding scheme associated with the given symbol.
V00001INVALID
V00010INVALID
V00011INVALID
H00100INVALID
V00101INVALID
V00110INVALID
V01000INVALID
V01100INVALID
V10000Flow Control S
V11001INVALID
Inter Pack et Idle Symbol
(No 4B)
1st Start of Packet Symbol
0101
2nd Start of Packet Symbol
0101
2nd End of Packet Symbol
and Flow Control
4.2.2100BASE-TX Scrambler and MLT-3 Encoder
Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long
transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B
encoder block and presents the scrambled data to the MLT-3 encoder. The 82555 implements the
11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation.
The cipher equation used is:
X[n] = X[n-11] + X[n-9] (mod 2)
The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the
scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to
NRZI coding, but three levels are output instead of two. There are three output levels: positive,
negative and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is
14
Datasheet
Networking Silicon — 82555
maintained (either positive, n eg ativ e o r zero). When an NR Z “1” arri v es at th e input of the encoder,
the output steps to the next level. The order of steps is negative-zero-positive-zero which continues
periodically. The figure below illustrates this process.
Clock
NRZ
NRZ1
MLT-3
11000110
11000110
11000110
Figure 6. NRZ to MLT-3 Encoding Diagram
4.2.3100BASE-TX T ransmit Framing
The 82555 does not differentiate between the fields of the MAC frame containing preamble, start
of frame delimiter, data and Cyclic Redund anc y Check (CRC). When TXE N is asserted, the 82555
accepts data on the MII TXD[3:0] lines, encodes it, and sends it out onto the wire. The 82555
encodes the first byte of the preamble as the “JK” symbol, encodes all other pieces of data
according to the 4B/5B lookup table, and adds the “TR” code after the end of the packet (deassertion of TXEN). The 82555 scrambles and serializes the data into a 125 Mbps stream, encodes
it as ML T-3, and drives it onto the wire. If TXERR is asserted dur ing trans mission of v alid data, th e
82555 transmits an invalid “H” symbol.
Datasheet15
82555 — Networking Silicon
(V
TDP-VTDN
)
+1V
0V
-1V
40mA
I
TDP
20mA
0
40mA
20mA
0
I
TDN
t
t
t
4.2.4Transmit Driver
The transmit differential lines are implemented with a digital slope controlled current driver that
meets the TP-PMD specifications. Current is sunk from the isolation transformer by the transmit
differential pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the
following figure.
The magnetics module that is external to the 82555 converts I
by the TP-PMD specification. The same magnetics used for 100BASE-TX mod e should also work
in 10BASE-T mode. The following is a list of current magnetics modules available from several
vendors:
The receive subsection of the 82555 accepts 100BASE-TX MLT-3 data on the receive differential
pair. Due to the advanced digital signal processing design techniques employed, the 82555 will
accurately receive valid data from Category 5 (C AT5) UTP and Type 1 STP cable of length well in
excess of 100 meters.
16
TDP
and I
to 2.0 Vpp, as required
TDN
Table 3. Magnetics Modules
Datasheet
Networking Silicon — 82555
4.3.1Adaptive Equalizer
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer
performs adaptation based on the shape of the received signal, equalizing the signal to meet
superior Data Dependent Jitter performance.
4.3.2Receive Clock and Data Recovery
The clock recovery circuit uses advanced digital signal processing technology to compensate for
various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data
to the MLT-3 decoder.
4.3.3MLT-3 Decoder, Descrambler, and Receive Digital Section
The 82555 first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B symbols
originated in the transmitter. The descrambling is based on synchronization to the transmit 11-bit
Linear Feedback Shift Register (LFSR) during idle. The data is decoded at the 4B/5B decoder.
Once the 4B symbols are obtained, the 82555 outputs the receive data to the CSMA unit.
4.3.4100BASE-TX Receive Framing
The 82555 does not differentiate between the fields of the MAC frame containing preamble, start
of frame delimiter, data and CRC. During 100 Mbps reception, the 82555 differentiates between
the idle condition ("L" symbols on the wire) and the preamble or start of frame delimiter. When
two non-consecutive bits are 0b within 10 bits (125 Mbps 5B data coding) the 82555 immediately
asserts the CRS signal. When the “JK” symbols (“11000, 10001”) are fully recognized, the 82555
asserts the RXDV signal and provides the data recei v ed on the MII RXD[3:0] to the Receiv e Clock.
If the “JK” symbol is not recognized (“false carrier sense”), the CRS signal is immediately deasserted and RXERR is asserted. Otherwise, the valid data is passed through th e MII until the
82555 finds the “TR” (“01101, 00111”) and idle symbols in order to de-assert TXDV and CRS.
4.3.5100BASE-TX Receive Error Detect ion and Reporting
In 100BASE-TX mod e, the 825 55 can detect errors in recei v e d ata in a nu mber of ways. An y o f the
following conditions is considered an error:
Link integrity fails in the middle of frame reception.
•
The start of stream delimiter “JK” symbol is not fully detected after idle.
•
An invalid symbol is detected at the 4B/5B decoder.
•
Idle is detected in the middle of a frame (before “TR” is detected).
•
When any of the above error conditions occurs, the 82555 immediately asserts the Receive Error
signal to the MAC. The R XERR signal is asserted as lon g as the receive error condition persists on
the receive pair.
4.4100BASE-TX Collision Detection
100BASE-TX collisions in half duplex mode only are detected similarly to 10BASE-T collision
detection, via simultaneous transmission and reception.
Datasheet17
82555 — Networking Silicon
4.5100BASE-TX Link Integrity and Auto-Negotiation Solution
The 82555’s Auto-Negotiation function automatically configures the device to the technology,
media, and speed to operate with its link partner. Auto-Negotiation is widely described in IEEE
specification 802.3u, Clause 28. The 82555 supports 10BASE-T half duplex, 10BASE-T full
duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex.
The 82555 has two Physical Medium Attachment (PMA) technologies with its link integrity
function, 10BASE-T and 100BASE-TX. The 82555 also has a special interface defined between
itself and a PHY-T4 in order to implement an Auto-Negotiation combination card.
4.5.1Link Integrity
In 100BASE-TX, the link integrity function is determined by a stable signal status coming from the
TP-PMD block. Signal status is asserted when the PMD detects breaking squelch energy and the
right bit error rate according to the ANSI specification.
4.5.2Auto-Negotiation
The 82555 fully supports IEEE 802.3u, Clause 28. In DTE (adapter) mode, the technology,
10BASE-T or 100BASE-TX, is determined by the Auto-Negotiation result . In repeat er mod e onl y,
this function can be disabled by pin configuration. If the T4ADV pin is active, the AutoNegotiation function will advertise and negotiate T4 technology.
Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may
be manually configured via the MII management interface (MDI registers).
4.5.3Combination Tx/T4 Auto-Negotiation Solution
The Auto-Negotiation function is available in both the 82555 and a PHY-T4. For these PHYs to
operate together, some arbitration at the PMA level is required and the Auto-Negotiation function
of one of the PHYs must be disabled. For this purpose, the 82555 is defined as the master; and the
PHY-T4, the slave. In combination mode, only the 82555’s Auto-Negotiation function is enabled
(the PHY-T4’s Auto-Negotiation is disabled).
In a combination boar d, a PHY-T4 is used on ly to supp ort 1 00BASE-T4 operation and the 82555 is
sued to support 100BASE-TX full or half duplex and 10BASE-T full or half duplex as determined
by the Auto-Negotiation or Parallel Detection function.
Combination mode is available only in DTE (adapter) mode with the following pin interface:
T4ADV (pin 54): Enables T4 technology in a PHY-TX Auto-Negotiation system.
•
SLVTRI (pin 52): Disables the PHY -T4.The PHY-T4 is enabled only if the T4 technology has
•
been detected by Auto-Negotiation or Parallel Detection.
LISTAT (pin 6): Indicates valid link on the PHY-T4. When SLVTRI is de-asserted, the PHY-
•
T4 should be active.
18
Datasheet
Networking Silicon — 82555
3669
The figure below illustrates an 82557/82555/PHY-T4 s olution in a block diagram.
T4
adv
82555
PCI BUS
82557
fdx_n
MII
PHY-T4
Figure 8. Combination Card Example
4.6Auto 10/100 Mbps Speed Selection
The MAC may either allow the 82555 to automatically select its operating speed or force the 82555
into 10 Mbps or 100 Mbps mode. The Management Data Interface (MDI) can control the 82555
speed mode.
The 82555 autoselect function determines the operation speed of the media based on the link
integrity pulses it receives. If no Fast Link Pulses (FLPs) are detected and Normal Link Pulses
(NLPs) are detected, the 82555 defaults to 10 Mbps operation. If the 8255 5 detects a speed chang e,
it dynamically changes its transmit clock and receive clock frequencies to the appropriate value.
This change takes a maximum of five milliseconds.
listat_n
slave_tri
Common
Magnetics
4.7Adapter Mode Addresses
In DTE (adapter) mode, the 82555 supports addresses 0, 1, 2, and 3 through the pins PHYA1 and
PHYA0. Four addresses are sufficient in the case of a combination adapter having three PHYs. For
switch applications, the T4ADV signal should be de-asserted to allow all 32 addresses to be
available in repeater mode.
Datasheet19
82555 — Networking Silicon
20
Datasheet
Networking Silicon — 82555
5.010BASE-T Functionality in Adapter Mode
5.110BASE-T Transmit Clock Generation
The 20 MHz and 10 MHz clocks needed for 10B A SE-T are synthesized fr om th e external 25 MHz
crystal or oscillator. The 82555 provides the transmit clock and receive clock to the MAC at 2.5
MHz.
5.210BASE-T Transmit Blocks
5.2.110BASE-T Manchester Encoder
After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock
performs the Manchester encoding. The Manchester code always has a mid-bi t trans ition. If the
value is 1b then the transition is from low to high. If the value is 0b then the transition is from high
to low. The boundary transition occurs only when the data changes from bit to bit. For example, if
the value is 10b, then the change is from high to low; if 01b, then the change is from low to high.
5.2.210BASE-T Driver and Filter
Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented
inside the chip. This allows the two technologies to share the same magnetics. The 82555 suppo rts
both technologies through one pair of transmit differential pins and by externally sharing the same
magnetics.
In 10 Mbps mode, the 82555 begins transmitting the serial Manchester bit stream within 3 bit times
(300 nanoseconds) after the MAC asserts TXEN. In 10 Mbps mode the line drivers use a predistortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the
second half of “wide” (100 ns) Manchester pulses and maintain a full drive level during all narrow
(50 ns) pulses and the first half of the wide pulses. This reduces line overcharging during wide
pulses, a major source of jitter.
5.310BASE-T Receive Blocks
5.3.110BASE-T Manchester Decoder
The 82555 performs Manchester decoding and timing recovery when in 10 Mbps mode. The
Manchester encoded data stream is decoded from the receive differential pair to separate Receive
Clock and Receive Data lines from the differential signal. This data is transferred to the controller
at 2.5 MHz/nibble through the MII. The hig h-performance circuitry of the 82555 e xceeds the I EEE
802.3 jitter requirements.
5.3.210BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter
In 10 Mbps mode, data is expected to be received on the receive differential pair after passing
through isolation transformers. The filter is implemented inside the 82555 for supporting single
magnetics that are shared with the 100BASE-TX side. The input differential voltage range for the
Datasheet21
82555 — Networking Silicon
Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive
buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the
requirements of the 10BASE-T standard.
The following line activity is determined to be inactive and is rejected:
Differential pulses of peak magnitude less than 300 mV.
•
Continuous sinusoids with a differential amplitude less than 6.2 Vpp and frequency less than 2
•
MHz.
Sine waves of a single cycle duration starting with 0° or 180° phase that have a differential
•
amplitude less than 6.2 V
These single-cycle sine waves are discarded only if they are preceded by 4 bit times (400
nanoseconds) of silence.
All other activity is determined to be either data, link test pulses, Auto-Negotiation fast link pulses,
or the idle condition. When activity is detected, the carrier sense signal is asserted to the MAC.
and a frequency of at least 2 MHz and not more than 16 MHz.
pp
5.3.310BASE-T Error Detection and Reporting
In 10 Mbps mode, the 82555 can detect errors in the receive data. The following condition is
considered an error:
The receive pair’s voltage level drops to the idle state during reception bef ore the end-of-f rame
bit is detected (250 nanoseconds without mid-bit transitions).
5.410BASE-T Collision Detection
Collision detection in 10 Mbps mode is indicated by simultaneous transmission and reception. If
the 82555 detects this condition, it asserts a collision indication to the controller.
5.510BASE-T Link Integrity
The link integrity in 10 Mbps works with link pulses. The 82555 senses and differentiates those
link pulses from fast link pulses and from 100BASE-TX idles. In the first and last case, the 82555
activates parallel detection of the respecti ve technology; and in the second case, Auto-Negotiation.
The 10 Mbps link pulses or normal link pulses are driven in the transmit differential pair line but
are 100 ns wide and ha ve l e v els fr om 0 V to 5 V. The link beat pulse i s also used t o det ermine if the
receive pair polarity is reversed. If it is, the polarity is corrected internally.
5.610BASE-T Jabber Control Function
The 82555 contains a jabber control function that inhibits transmission after a specified time
window when enabled. In 10 Mbps mod e, the jabber timer is set to a v alue between 26 .2 ms and 39
ms. If the 82555 detects continuous transmissi on that is greater than this time period, it prevents
further transmissions from onto the wire until it detects that the MAC transmit enable signal has
been inactive for at least 314 ms.
22
Datasheet
5.710BASE-T Full Duplex
The 82555 supports 10 Mbps full duplex by disabling the collision function, the squelch test, and
the carrier sense transmit function. This allows the 82555 to transmit and receive simultaneously,
achieving up to 20 Mbps of network bandwidth. The configuration can be achieved through AutoNegotiation. Full duplex should only be used in point-to-point connections (no shared media).
Flow control is always disabled.
Networking Silicon — 82555
Datasheet23
82555 — Networking Silicon
24
Datasheet
6.0Repeater Mode
The 82555 has a compete set of repeater features making it the ideal PHY for Class 1 (MII)
repeater designs. The 82555 works in repeater mode when the RPT signal (pin 50) is high. The
FRC100 signal (pin 51) determines which type of repeater is supported, either 100BASE-TX or
10BASE-T.
6.1Special Repeater Features
Special features of the 82555 repeater mode operation include:
Fully IEEE compliant with automatic carrier disconnect.
•
The 82555 will disconnect when it receives false carrier detects. Either a long series of valid
idle symbols or a valid “JK” pair will cause it to reconnect.
Narrow 14 mm analog side that enables tight packing of multiple PHYs, which is ideal for 8,
•
12, 18, 24, or even 32 port repeater designs.
Very low emissions and high noise immunity.
•
32 configurable addresses through five address lines.
•
Auto-Negotiation di sab l e functi on.
•
In repeater mode, the Auto-Negotiation fu ncti on is n ot us ed f or configuration purposes. When
Auto-Negotiation is enabled in repeater mode, the MII management will be able to obtain data
from the MDI Auto-Negotiation register about the remote partner. This is a feature for hub
management allowing a 10/100 Mbps r epeater d esign to autom atically detect wheth er o r n ot it
can operate at 100 Mbps. If the ANDIS signal is de-asserted, the Auto-Negotiation feature will
be disabled.
Networking Silicon — 82555
Forced 10 Mbps or 100 Mbps operation (allows for a 10/100 repeater design).
•
Receive port enable function.
•
The PORTEN signal is a glueless interface to the Repeater Interface Controller (RIC). When
the PORTEN signal is low, all receive signals are tri-stated, except CRS and COL.
26-bit PHY budget for round trip.
•
The total PHY bit budget is 8 bits from the MII to the wire and 18 bits from the wire to the
MII.
Static 2.5 MHz (10BASE-T) or 25 MHz (100BA SE-TX) clock input for repeater designs
•
(issued by RIC).
The 82555 clock source is fixed between Resets. There is one input, either 2.5 MHz or 25
MHz, as indicated by the level at the FRC100 pin. All clocks have a common source
generation so the that PPM is 0 between them (X1, 2.5 MHz and 25 MHz).
DTE (adapter) features not available in repeater mode: full duplex, flow control, and the
•
combination Auto-Negotiation interface for T4.
6.2Connectivity
A 25 MHz buffered oscillator can provide the clock to all of the 82555 devices. A 2.5 MHz (10
Mbps) or a 25 MHz (100 Mbps) signal is required to clock the RIC and the TXC signal in the
PHYs. TXD[3:0], TXERR, RXC, RXD[3: 0], RXD V, and RXERR are single -bus (s hortened) fo r all
Datasheet25
82555 — Networking Silicon
PHYs connected to the RIC. Signals TXEN, CRS, and PORTEN are connected from each of the
82555 devices to the specified RIC pin. The figure below illustrates an example of multiple 82555s
connected to a 25 MHz (or 2.5 MHz) oscillator.
2.5/25 MHz (10/100)
RIC
CLK
2.5/25 MHz (10/100)
TXCLK
PHY1
X1
TXCLKTXCLK
PHY2
X1X1
PHY3
PC-3691
Figure 9. Clock Signal Example
26
Datasheet
7.0Management Data Interface
The 82555 provides status and accepts management information through the Management Data
Interface (MDI). This is accomplished through read and write operations to various registers in
accordance with the IEEE 802.3u MII specification.
7.1MDI Frame Structure
Data read from or written to a particular register is called a management frame and is sent serially
over the MDIO pin synchronously to the MDC signal. Read and write cycles are viewed from the
perspective of the controller. Thus, the controller always drives the start, opcode, PHY address, and
register address onto the MDIO pin. For read cycles, the controller drives the transition bits and
data onto the MDIO pin; for write cycles, to the 82555. The controller dri v es addresses and data on
the falling edge of the MDC signal, and the 82555 latches the data on the rising edge of the MDC
signal. The following list defines protocol terms:
Networking Silicon — 82555
PREAMBLE
ST
OP
PHYAD
REGAD
TA
DATA
At the beginning of each transaction, the controller send a sequence of 32
contiguous logic one bits on the MDIO pi n with corres pon di ng cycles on the MDC
pin for synchronization by the 82555.
This field contains the value of 01b indicating the start of a frame.
This is a 2-bit field containing one of the follo wing two operation codes: 10 b (read)
or 01b (write).
This field is a 5-bit address of th e 8 2555 device that provides su ppo rt for 32 unique
PHY addresses. The controller drives the value written into the PHYAD portion of
the MDI register in this field.
This field is a 5-bit address of a specific register within the 82555. This provides
support for 32 unique registers. The desired register address is specified by the
value written to the MDI register.
This field contains a 2-bit value specifying the period during a read cycle that no
device may actively drive the MDIO signal. During a read transaction, the 82555
should not drive the MDIO signal in the first bit time; however, it will drive a 0b in
the second bit time. During a write transaction, the controller drives the pattern of
10b to fill this time.
This field contains 16 bits of data driven by the 82555 on a read transaction or by
the controller on a write transactions. This data is either control or status parameters
passed between the controller and the 82555.
IDLE
During the idle state, the MDIO signal is in a high impedance state. The MDIO
driver is disabled, and the 82555 will pull the MDIO signal high to a logic 1.
Datasheet27
82555 — Networking Silicon
The 82555 address can be configu red t o fou r 0 th rough 3 in DTE (adapter) mode and 0 through 31
in repeater mode. A special functions for switches allows 32 addresses to exist in repeater mode.
The management frame structure is as follows:
7.2.1.1Register 0: Control Register Bit De finitions
Bit(s)NameDescriptionDefaultR/W
15ResetThis bit sets the status and control register of the 82555
14LoopbackThis bit enables loopback of transmit data nibbles from
13Speed SelectionThis bit controls speed when Auto-Negotiation is disabled
12Auto-Negotiation
Enable
to their default states and is self-clearing. The PHY
returns a value of 1b until the reset process has
completed and accepts a read or write transaction.
1 = PHY Reset
0 = Normal operation
the TXD[3:0] signals to the receive data path. The
82555’s receive circuitry is isolated from the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of “dead
time.”
Note also that the loopback configuration bit takes priority
over the Loopback MDI bit.
10IsolateThis bit allows the 82555 to electrically isolate the Media
9Restart Auto-
Negotiation
8Duplex ModeThis bit controls the duplex mode when Auto-Negotiation
7Collision TestThis bit will force a collision in response to the assertion
6:0ReservedT hese bits are reser ved and should be set to 0000000b.0RW
Independent Interface. When the MII is isolated, the
82555 does not respond to TXD[3:0], TXEN, and TXERR
input signals. Also, the 82555 presents high impedance
on its TXC, RXC, RXDV, RXERR, RXD[3:0], COL, and
CRS output signals. In the TX mode, the 82555 responds
to management transactions.
1 = Electrically isolate MII
0 = Normal operation
This bit restarts the Auto-Negotiation process and is selfclearing.
1 = Restart Auto-Negotiation process
0 = Normal operation
is disabled. If the 82555 reports that it is only able to
operate in one duplex mode, the value of this bit shall
correspond to the mode which the 82555 can operate.
When the 82555 is placed in Loopback mode, the
behavior of the PHY shall not be affected by the status of
this bit, bit 8.
1 = Full Duplex
0 = Half Duplex
of the transmit enable signal.
1 = Force COL
0 = Do not force COL
0RW
0RW
0RW
SC
0RW
0RW
7.2.1.2Register 1: Status Register Bit Definitions
Bit(s)NameDescriptionDefaultR/W
15100BASE-T41 = 82555 able to perf orm 100BASE-T4
0 = 82555 not able to perform 100BASE-T4
14100BASE-TX Full
Duplex
13100 Mbps Half
Duplex
1210 Mbps Full
Duplex
1110 Mbps Half
Duplex
10:7ReservedThese bits are reserved and should be set to 0000b.0RO
1 = 82555 able to perform full duplex 100BASE-TX
0 = 82555 not able to perform full duplex in repeater
mode
1 = 82555 able to perform half duplex 100BASE-TX
0 = 82555 not able to perform 100BASE-TX
1 = 82555 able to operate at 10 Mbps in full duplex
mode
0 = 82555 not able to operate in full duplex mode in
10BASE-T
1 = 82555 able to operate at 10 Mbps in half duplex
mode
0 = 82555 not able to operate in 10BASE-T
Datasheet29
--RO
P
--RO
P
--RO
P
--RO
P
--RO
P
82555 — Networking Silicon
Bit(s)NameDescriptionDefaultR/W
6Management
Frames Preamble
Suppression
5Auto-Negotiation
Complete
4Remote Fault1 = Remote fault condition detected
3Auto-Negotiation
Ability
2Link Status1 = Valid link has been established
1Jabber Detect1 = Jabber condition detected
0Extended
Capability
1 = 82555 will accept management frames with
preamble suppressed
0 = 82555 will not accept management frames with
preamble suppressed
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process has not completed
0 = No remote fault condition detected
1 = 82555 is able to perform Auto-Negotiation
0 = 82555 is in repeater mode and Auto-Negotiation
Disable pin is high
1 = Auto-Negotiation loopback
0 = Auto-Negotiation normal mode
0 = Normal operation
0 = Normal filter operation
1 = Auto Polarity disabled
0 = Normal polarity operation
0 = Normal squelch operation
1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled
1 = Link disabled
0 = Normal Link Integrity operation
1 = Jabber disabled
0 = Normal Jabber operation
0RW
0RW
0RW
0RW
0RW
0RW
0RW
0RW
0RW
0RW
--RW
0RW
0RW
7.2.3.3Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
Bit(s)NameDescriptionDefaultR/W
15:0Disconnect EventThis field contains a 16-bit counter that increments for
each disconnect event. The counter stops when full
(and does not roll over) and self-clears on read
In repeater mode, a frame that starts without “JK” is a
disconnect event.
--RO
SC
7.2.3.4Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions
Bit(s)NameDescriptionDefaultR/W
15:0Receive Error
Frame
Datasheet33
This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter stops when full (and does not roll
over) and self-clears on read.
--RO
SC
82555 — Networking Silicon
7.2.3.5Register 22: Receive Symbol Error Counter Bit Definitions
Bit(s)NameDescriptionDefaultR/W
15:0Symbol Error
Counter
This field contains a 16-bit counter that increments f or
each symbol error. The counter stops when full (and
does not roll over) and self-clears on read.
In a frame with a bad symbol, each sequential six bad
symbols count as one.
--RO
SC
7.2.3.6Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Bit Definitions
Bit(s)NameDescriptionDefaultR/W
15:0Premature End of
Frame
This field contains a 16-bit counter that increments f or
each premature end of frame event. The counter
stops when full (and does not roll over) and self -clears
on read.
A frame without a “TR” at the end is considered a
premature end of frame event.
--RO
SC
7.2.3.7Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions
Bit(s)NameDescriptionDefaultR/W
15:0End of Frame
Counter
This is a 16-bit counter that increments for each end
of frame error event. The counter stops when full (and
does not roll over) and self-clears on read.
--RO
7.2.3.8Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions
Bit(s)NameDescriptionDefaultR/W
15:0Jabber Detect
Counter
This is a 16-bit counter that increments for each
jabber detection event. The counter stops when full
(and does not roll over) and self-clears on read.
--RO
7.2.3.9Register 27: 82555 Special Control Bit Defini tions
Bit(s)NameDescriptionDefaultR/W
15:3ReservedThese bits are reserved and should be set to 0b.0RW
2:0LED Switch
Control
Value
000
001
010
011
100
101
110
111
ACTLED
Activity
Speed
Speed
Activity
Off
Off
On
On
LILED
Link
Collision
Link
Collision
Off
On
Off
On
000RW
SC
SC
34
Datasheet
8.0Auto-Negotiation Functionality
The 82555 supports Auto-Negotiation. Auto-Negotiation is a scheme of auto-configuration
designed to manage interoperability in multifu nctional LAN environments. It allows two stations
with “N” different modes of communication to establish a common mode of operation. At powerup, Auto-Negotiation automatically establishes a link that takes advantage of an Auto-Negotiation
capable device. An Auto-Negotiation capable device can detect and automatically configure its
port to take maximum adv antage of comm on mod es of operati on with out user inter v entio n or prior
knowledge by either station. The possible common modes of operation are: 100BASE-TX,
100BASE-TX Full Duplex, 100BASE-T4, 10BASE-T, and 10BASE-T Full Duplex.
8.1Description
Auto-Negotiation selects the fastest operating mode (in other words, the highest common
denominator) available to hardware at both ends of the cable. A PHY’s capability is encoded by
bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange
and handshake during link initialization time. Once the link is established by this handshake, the
native link pulse scheme resumes (that is, 10BASE-T or 100BASE-TX link pulses). A reset or
management renegotiate command (through the MDI interface) will restart the process. To enable
Auto-Negotiation, bit 12 of the MDI Control Register must be set. If the 82555 cannot perform
Auto-Negotiation, it will set this bit to 0b and determin e the speed using Parallel Detection.
Networking Silicon — 82555
The 82555 supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full
and Half Duplex. Since only one technology can be used at a time (after every renegotiate
command), a prioritization scheme must be used to ensure that the highest common denominator
ability is chosen.
Table 4 lists the technology ability field bit assignments. Each bit in this table is
set according to what the PHY is capable of supporting. In the case of the 82555, bits 0, 1, 2, and 3
are set. Table 5 lists the priority of each of the technologies.
Table 4. Technology Ability Field Bit Assignments
Bit SettingTechnology
010BASE-T Half Duplex
110BASE-T Full Duplex
2100BASE-T Half Duplex
3100BASE-T Full Duplex
4100BASE-T4
5Pause (Flow Control)
6Reserved
7Reserved
Table 5. Technology Priority
PriorityTechnology
1100BASE-TX Full Duplex
2100BASE-T4
3100BASE-TX Half Duplex
Datasheet35
82555 — Networking Silicon
To detect the correct technology, the two register fields should be ANDed together to obtain the
highest common denominator. This value should then be used to map into a priority resolution
table used by the MAC driver to use the appropriate technology.
The following is an outline of the Auto-Negotiation process:
1. Receive 3 consecutive, matching code words
2. Set Acknowledge bit in transmit code word
3. Receive 3 consecutive, matching code words with Acknowledge bit set
4. Transmit 6 to 8 more code words with Acknowledge bit set
5. Determine operating mode via the priority table
6. Receive FLP from the link partner and record FLP in the MII register
Table 5. Technology Priority
PriorityTechnology
410BASE- T Full Duplex
510BASE- T Half Duplex
8.2Parallel Detect and A uto-Negotiati on
The 82555 automatically determines the speed of the link either by using Parallel Detect or AutoNegotiation. Upon a reset, a link status fail, or a negotiate/renegotiate command, the 82555 inserts
a long delay during which no link pulses are transmitted. This period, known as Force _Fail, insures
that the 82555’s link partner has gone into a Link Fail state before Auto-Negotiation or Parallel
Detection begins. Thus, both sides (the 82555 and the 82555’s link partner) will perform Auto-
36
Datasheet
Networking Silicon — 82555
Negotiation or Parallel Detection with no data packets being transmitted. Connection is then
established either by FLP exchange or Parallel Detection. The 82555 will look for both FLPs and
link integrity pulses. The following diagram illustrates this process.
Force_Fail
Ability detect either by
parallel detect or auto-
negotiation.
Parallel Detection
Auto-Negotiation
10Base-T or
100Base-TX Link
Ready
Look at Link Pulse;
Auto-Negotiation capable = 0
Figure 10. Auto-Negotiation and Parallel Detect
FLP capable
LINK PASS
Auto-Negotiation Complete bit set
Auto-Negotiation capable = 1
Ability Match
Datasheet37
82555 — Networking Silicon
38
Datasheet
9.0LED Descriptions
The 82555 supports four LED pins to indicate link status, network activity and network speed.
Link: This LED is off (logic high) until a valid link has been detected. After a valid link has
•
been detected, the LED will remain on (active-low).
Activity: This LED is on (active-low ) when activity is detected on the wire. In DTE (adapter)
•
mode, this LED is on during transmit and receive when the 82555 is not in loopback mode. In
repeater mode, this LED is on only during receive when the 82555 is not in loopback mode.
Speed: This LED will be on if a 100BASE-TX link is detected and off if a 10BASE-T link is
•
detected. If the link fails while in Auto-Negotiation, this LED will keep the last v alid link state.
If 100BASE-TX link is forced this LED will be on, regardless of the link status. This LED will
be of if the 10BASE-T link is forced, regardless of the link status.
Full Duplex: The FDX_N signal can operate as a LED if it is enabled. It indicates full duplex
•
link for either 100BASE-TX or 10 BASE-T technology.
MDI register 27 in Section 7.2.3.9, “Register 27: 82555 Special Control Bit Definitions” on
page 34 details the information for LED function mapping and support enhancements.
Networking Silicon — 82555
Datasheet39
82555 — Networking Silicon
40
Datasheet
Networking Silicon — 82555
10.0Reset and Miscellaneous Test Modes
10.1Reset
When the 82555 RESET signal is asserted (high), all internal circuits are reset. TXC and RXC
should run continuously even though RESET is active. The 82555 may also be reset through the
MDI reset bit.
10.2Lo opback
When the loopback pin is being driven high, the 82555 executes a loopback diagnostics operation.
This mode can also be accessed through the MDI registers.
10.3Scrambler Bypass
When the Scrambler Bypass pin is active, the 82555 bypasses the scrambler/descrambler. This
mode can also be accessed through the MDI registers.
10.4Test Port
When the TESTEN pin is high, the test pins provide a test access port for the 82555. In test mode,
the 82555 will default to address 1. The 82555 has a simple Test Access Port (TAP) from which all
the test modes are selected and test instructions are operated. The TAP is controlled by a simple
mechanism and handshake. Activ ation of all test modes requires simple hardware. The TAP signals
connected to the 825 55 blocks and periphery control the 8 2555’s mode of operation to allo w simp le
testing and internal built-in self testing.
The test instruction are shifted into the Test Instruction Shift Register (TISR) through the TIN pin.
The TIN pin is sampled on the rising edge of the TCK input signal. The instruction is transferred
from the TISR to the Test Instruction Register (TIR) when TESTEN is sampled high on the rising
edge of TCK. As a general rule, all t he TAP input and output pins are acti v ated b y the risi ng edge of
TCK. If TCK is a constant clock signal, then TESTEN must be 1 clock pulse width.
When the TIR receives a new instruction, the instruction is decoded into control signals and
synchronized to the 10 MHz clock. These control signals set the 82555 blocks into various test
modes. In order to achieve stable synchronization between the clock signal (X1) and the TCK
signal, the TCK input signal fr equenc y shou ld be les s than or equ al to h alf of t he clock inpu t sign al
frequency.
Datasheet41
82555 — Networking Silicon
The TOUT pin is controlled by different sources according to the acti ve test instruction. The T OUT
signal is activated b y the falling edge of TCK. The TAP must be reset during power-up. Otherwise,
the 82555 can wake-up during high-Z mode or NAND Test, which can be harmful to the board.
The TA P should be reset only with a hardware reset input pin and not with software reset. The
TOUT control logic selects the TISR output in all tests, except burn-in test modes.
11.0Electrical Specifications and Timing Parameters
11.1Absolute Maximum Ratings
SymbolParameter DescriptionMinTypMaxUnits
T
C
T
S
V
SUP
a
V
OA
V
OTD
V
IA
a. Stresses above the listed under absolute maximum ratings may cause permanent damage to the
device. This is a stress rating only and fu nctional operations o f the device at th ese or any ot her
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Case temperature under bias085C
Storage temperature-65140C
Supply voltage-0.57.0V
All output voltages-0.57.0V
Transmit Data Output Voltage-0.58.0V
All input voltages-1.06.0V
a. This val ue is measured across the receive differential pins, RDP and RDN.
b. RL is the resistive load across the receive differential pins, RDP and RDN.
c. Transmitter current is measured with a 1:1 transformer on the center tap.
d. Current is measured on all V
e. The analog pins are: TDP, TDN, RDP, RDN, RBIAS10, and RBIAS100.
Input differential accept voltage
Input differential reject voltage
Input common mode voltageVCC/2V
Output differential voltage
c
Line driver supplyRBIAS10 = 768
d
Current on all VCC pins120mA
Total supply current230mA
e
Leakage on analog pins20mA
pins at VCC = 5.25 V.
CC
Rbias10
Ω
805
5 MHz ≤ f ≤ 10 MHz
5 MHz ≤ f ≤ 10 MHz
b
RL = 100
Ω
RBIAS10 = 768
±585±3100mV
±2.2±2.8V
Ω
Ω
110mA
±300mV
P
P
768
Ω
735
Ω
105mA110mA
115mA
Figure 11. RBIAS10 Resistance versus I
11.3.3100BASE-TX Voltage/Current DC Characteristics
a. Transmitter current is measured with a 1:1 transformer on the center tap.
b. Transmitter current is measured with a 1:1 transformer on the center tap.
c. Current is measured on all V
Current on all VCC pins235mA
Total supply current275mA
Jabber turn-on delay (TXEN
asserted to end of transmit
frame)
Jabber turn-off delay (TXEN deasserted to falling edge of COL)
Networking Silicon — 82555
T20
10 Mbps26ms
10 Mbps410ms
T21
TXEN
COL
T22
TDP/TDN
Figure 21. Jabber Timing Parameters
11.4.7Receive Packet Timing Parameters
SymbolParameterConditionsMinTypMaxUnits
T24T
T24a
T25T
T25a
T26T
R_CRSH
T
R_CRSH
R_RXDVH
T
R_RXDVH
R_CRSL
Start of receive frame to rising
edge of CRS
Start of receive frame to rising
edge of CRS
Start of receive frame to rising
edge of RXDV
Start of receive frame to rising
edge of RXDV
End of receive frame to falling
edge of CRS
T23
100 Mbps1113bits
10 Mbps35bits
100 Mbps15bits
10 Mbps22bits
100 Mbps1416bits
Datasheet49
82555 — Networking Silicon
Normal Link Pulse
SymbolParameterConditionsMinTypMaxUnits
T26a
T
R_CRSL
T27T
T27a
R_RXDVL
T
R_RXDVL
End of receive frame to falling
edge of CRS
End of receive frame to falling
edge of RXDV
End of receive frame to falling
edge of RXDV
RXCLK
10 Mbps4.5bits
100 Mbps12bits
10 Mbps4bits
RXDV
CRS
Frame On link
T25,T25a
T24,T24a
T27,T27a
T26,T26a
Valid Frame Data
Figure 22. Receive Packet Timing Parameters
11.4.810BASE-T Normal Link Pulse (NLP) Timing Parameters
SymbolParameterConditionsMinTypMaxUnits
T28T
T29T
NLP_WID
NLP_PER
NLP width10 Mbps100ns
NLP period10 Mbps824ms
T29
T28
Figure 23. Normal Link Pulse Timing Parameters
11.4.9Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
SymbolParameterConditionsMinTypMaxUnits
50
T30T
T31T
T32T
FLP_WID
FLP_CLK_CLK
FLP_CLK_DAT
FLP width (clock/data)100ns
Clock pulse to clock pulse period111125139
Clock pulse to data pulse period55.562.569.5
Datasheet
µ
s
µ
s
T33T
)
T34T
T35T
Networking Silicon — 82555
SymbolParameterConditionsMinTypMaxUnits
FLP_BUR_NUM
FLP_BUR_WID
FLP_BUR_PER
Number of pulses in one burst1733
FLP Burst width2ms
FLP burst period824ms
T30
T31
T30
Fast Link Pulse
Clock Pulse
FLP Bursts
Figure 24. Fast Link Pulse Timing Parameters
11.4.10Reset Timing Parameters
SymbolParameterConditionsMinTypMaxUnits
T36T
T37T
RST_WID
PUP_RST
Reset pulse width500ns
Power-up to falling edge of reset500
Power Up (VCC
RESET
T34
T35
Data Pulse
T37
T36
Clock Pulse
Figure 25. Reset Timing Parameters
µ
s
11.4.11X1 Clock Specifications
SymbolParameterConditionsMinTypMaxUnits
T38T
T39T
X1_DC
X1_PR
Datasheet51
X1 duty cycle4060%
X1 period±50 PPM40ns
82555 — Networking Silicon
4.0V
2.5V
0.4V
T39
T38
Figure 26. X1 Clock Specifications
11.4.12100BASE-TX Transmitter AC Specification
SymbolParameterConditionsMinTypMaxUnits
T40T
JIT
TDP/TDN differential output peak
jitter
HLS data300700ps
T39
52
Datasheet
12.082555 Package Information
This section provides the physical packaging information for the 82555. The 82555 is an 100-pin
plastic Quad Flat Pack (QFP) device. Package attrib utes are provided in Table 7 and the dimensions
are shown in Figure 27.