Intel 307017-001 User Manual

Intel® I/O Controller Hub 7 (ICH7)/ Intel® High Definition Audio/ AC’97

Programmer’s Reference Manual (PRM)

For the Intel® 82801GB ICH7 and 82801GR ICH7R I/O Controller Hubs

April 2005

Document Number: 307017-001

Contents

2 Programmer’s Reference Manual

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “un defined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel to deviate from published specifications. Current characteri zed errata are available on request.

I/O Controller Hub 7 (ICH7) Family chipset component may contain design defect s or errors known as er rat a which may cause t he product

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I Corporation.

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

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Intel, Intel SpeedStep, and the Intel logo are trademarks or registered tr ademarks of Intel Corpor ation o r its sub sidiari es in the United States and other countries.

3 Programmer’s Reference Manual

Contents

1Intel® High Definition Audio Controller Registers (D27:F0) ....................................................13

1.1 Intel

High Definition Audio PCI Configuration Space

(Intel

High Definition Audio— D27:F0) .............................................................................13

1.1.1 VID—Vendor Identification Register

1.1.2 DID—Device Identification Register

1.1.3 PCICMD—PCI Command Register

1.1.4 PCISTS—PCI Status Register

1.1.5 RID—Revision Identification Register

1.1.6 PI—Programming Interface Register

1.1.7 SCC—Sub Class Code Register

1.1.8 BCC—Base Class Code Register

1.1.9 CLS—Cache Line Size Register

1.1.10 LT—Latency Timer Register

1.1.11 HEADTYP—Header Type Register

1.1.12 HDBARL—Intel

1.1.13 HDBARU—Intel

1.1.14 SVID—Subsystem Vendor Identification Register

1.1.15 SID—Subsystem Identification Register

(Intel

High Definition Audio Controller—D27:F0).................................................15

(Intel

High Definition Audio Controller—D27:F0).................................................15

(Intel

High Definition Audio Controller—D27:F0).................................................16

(Intel

High Definition Audio Controller—D27:F0).................................................17

(Intel

High Definition Audio Controller—D27:F0).................................................17

(Intel

High Definition Audio Controller—D27:F0).................................................18

(Intel

High Definition Audio Controller—D27:F0).................................................18

(Intel

High Definition Audio Controller—D27:F0).................................................18

(Intel

High Definition Audio Controller—D27:F0).................................................18

(Intel

High Definition Audio Controller—D27:F0).................................................19

(Intel

High Definition Audio Controller—D27:F0).................................................19

(Intel

High Definition Audio—D27:F0) .................................................................19

(Intel

High Definition Audio Controller—D27:F0).................................................19

(Intel

High Definition Audio Controller—D27:F0).................................................20

(Intel

High Definition Audio Controller—D27:F0).................................................20

High Definition Audio Lower Base Address Register

High Definition Audio Upper Base Address Register

1.1.16 CAPPTR—Capabilities Pointer Register (Audio—D30:F2) ...................................21

1.1.17 INTLN—Interrupt Line Register

1.1.18 INTPN—Interrupt Pin Register

1.1.19 HDCTL—Intel

1.1.20 TCSEL—Traffic Class Select Register

1.1.21 DCKSTS—Docking Status Register

1.1.22 PID—PCI Power Management Capability ID Register

1.1.23 PC—Power Management Capabilities Register

(Intel

High Definition Audio Controller—D27:F0).................................................21

(Intel

High Definition Audio Controller—D27:F0).................................................21

High Definition Audio Controller—D27:F0).................................................22

(Intel

High Definition Audio Controller—D27:F0).................................................23

(Intel

High Definition Audio Controller—D27:F0).................................................24

(Intel

High Definition Audio Controller—D27:F0).................................................24

(Intel

High Definition Audio Controller—D27:F0).................................................25

High Definition Audio Control Register

4 Programmer’s Reference Manual

Contents

1.1.24 PCS—Power Management Control and Status Register

1.1.25 MID—MSI Capability ID Register

1.1.26 MMC—MSI Message Control Register

1.1.27 MMLA—MSI Message Lower Address Register

1.1.28 MMUA—MSI Message Upper Address Register

1.1.29 MMD—MSI Message Data Register

1.1.30 PXID—PCI Express* Capability ID Register

1.1.31 PXC—PCI Express* Capabilities Register

1.1.32 DEVCAP—Device Capabilities Register

1.1.33 DEVC—Device Control Re gis te r

1.1.34 DEVS—Device Status Register

1.1.35 VCCAP—Virtual Channel Enhanced Capability Header

1.1.36 PVCCAP1—Port VC Capability Register 1

1.1.37 PVCCAP2 — Port VC Capability Register 2

1.1.38 PVCCTL — Port VC Control Register

1.1.39 PVCSTS—Port VC Status Register

1.1.40 VC0CAP—VC0 Resource Capability Register

1.1.41 VC0CTL—VC0 Resource Contr ol Re gis ter

1.1.42 VC0STS—VC0 Resource Status Register

1.1.43 VCiCAP—VCi Resource Capability Register

1.1.44 VCiCTL—VCi Resource Control Register

1.1.45 VCiSTS—VCi Resource Status Register

1.1.46 RCCAP—Root Complex Link Declaration Enhanced

1.1.47 ESD—Element Self Description Register

1.1.48 L1DESC—Link 1 Description Register

1.1.49 L1ADDL—Link 1 Lower Addre ss Regis te r

(Intel

High Definition Audio Controller—D27:F0).................................................25

(Intel

High Definition Audio Controller—D27:F0).................................................26

(Intel

High Definition Audio Controller—D27:F0).................................................26

(Intel

High Definition Audio Controller—D27:F0).................................................27

(Intel

High Definition Audio Controller—D27:F0).................................................27

(Intel

High Definition Audio Controller—D27:F0).................................................27

(Intel

High Definition Audio Controller—D27:F0).................................................27

(Intel

High Definition Audio Controller—D27:F0).................................................28

(Intel

High Definition Audio Controller—D27:F0).................................................28

(Intel

High Definition Audio Controller—D27:F0).................................................29

(Intel

High Definition Audio Controller—D27:F0).................................................29

(Intel

High Definition Audio Controller—D27:F0).................................................30

(Intel

High Definition Audio Controller—D27:F0).................................................30

(Intel

High Definition Audio Controller—D27:F0).................................................31

(Intel

High Definition Audio Controller—D27:F0).................................................31

(Intel

High Definition Audio Controller—D27:F0).................................................31

(Intel

High Definition Audio Controller—D27:F0).................................................32

(Intel

High Definition Audio Controller—D27:F0).................................................32

(Intel

High Definition Audio Controller—D27:F0).................................................32

(Intel

High Definition Audio Controller—D27:F0).................................................33

(Intel

High Definition Audio Controller—D27:F0).................................................33

(Intel

High Definition Audio Controller—D27:F0).................................................34

Capability Header Register (Intel

(Intel

High Definition Audio Controller—D27:F0).................................................34

(Intel

High Definition Audio Controller—D27:F0).................................................35

(Intel

High Definition Audio Controller—D27:F0).................................................35

High Definition Audio Controller—D27:F0).....34

Programmer’s Reference Manual 5

Contents

1.1.50 L1ADDU—Link 1 Upper Address Register

1.2 Intel

High Definition Audio Memory Mapped Configuration Registers

(Intel

High Definition Audio— D27:F0) .............................................................................36

1.2.1 GCAP—Global Capabilities Register

1.2.2 VMIN—Minor Version Register

1.2.3 VMAJ—Major Version Register

1.2.4 OUTPAY—Output Payload Capability Register

1.2.5 INPAY—Input Payload Capability Register

1.2.6 GCTL—Global Control Register

1.2.7 WAKEEN—Wake Enable Register

1.2.8 STATESTS—State Change Status Register

1.2.9 GSTS—Global Status Register

1.2.10 OUTSTRMPAY—Output Stream Payload Capability

1.2.11 INSTRMPAY—Input Stream Payload Capability

1.2.12 INTCTL—Interrupt Control Register

1.2.13 INTSTS—Interrupt Status Register

1.2.14 WALCLK—Wall Clock Counter Register

1.2.15 SSYNC—Stream Synchronization Register

1.2.16 CORBLBASE—CORB Lower Base Address Register

1.2.17 CORBUBASE—CORB Upper Base Address Register

1.2.18 CORBWP—CORB Write Pointer Register

1.2.19 CORBRP—CORB Read Pointer Register

1.2.20 CORBCTL—CORB Control Register

1.2.21 CORBST—CORB Status Register

1.2.22 CORBSIZE—CORB Size Register

1.2.23 RIRBLBASE—RIRB Lower Base Address Register

1.2.24 RIRBUBASE—RIRB Upper Base Address Register

(Intel

High Definition Audio Controller—D27:F0).................................................35

(Intel

High Definition Audio Controller—D27:F0).................................................40

(Intel

High Definition Audio Controller—D27:F0).................................................40

(Intel

High Definition Audio Controller—D27:F0).................................................40

(Intel

High Definition Audio Controller—D27:F0).................................................41

(Intel

High Definition Audio Controller—D27:F0).................................................41

(Intel

High Definition Audio Controller—D27:F0).................................................42

(Intel

High Definition Audio Controller—D27:F0).................................................43

(Intel

High Definition Audio Controller—D27:F0).................................................43

(Intel

High Definition Audio Controller—D27:F0).................................................44

(Intel

High Definition Audio Controller—D27:F0).................................................44

(Intel

High Definition Audio Controller—D27:F0).................................................45

(Intel

High Definition Audio Controller—D27:F0).................................................46

(Intel

High Definition Audio Controller—D27:F0).................................................47

(Intel

High Definition Audio Controller—D27:F0).................................................47

(Intel

High Definition Audio Controller—D27:F0).................................................48

(Intel

High Definition Audio Controller—D27:F0).................................................48

(Intel

High Definition Audio Controller—D27:F0).................................................49

(Intel

High Definition Audio Controller—D27:F0).................................................49

(Intel

High Definition Audio Controller—D27:F0).................................................49

(Intel

High Definition Audio Controller—D27:F0).................................................50

(Intel

High Definition Audio Controller—D27:F0).................................................50

Intel

High Definition Audio Controller—D27:F0)..................................................50

(Intel

High Definition Audio Controller—D27:F0).................................................51

(Intel

High Definition Audio Controller—D27:F0).................................................51

6 Programmer’s Reference Manual

Contents

1.2.25 RIRBWP—RIRB Write Pointer Register

1.2.26 RINTCNT—Response Interrupt Count Register

1.2.27 RIRBCTL—RIRB Control Register

1.2.28 RIRBSTS—RIRB Status Register

1.2.29 RIRBSIZE—RIRB Size Register

1.2.30 IC—Immediate Command Register

1.2.31 IR—Immediate Response Register

1.2.32 IRS—Immediate Command Status Register

1.2.33 DPLBASE—DMA Position Lower Base Address Register

1.2.34 DPUBASE—DMA Position Upper Base Address Register

1.2.35 SDCTL—Stream Descriptor Control Register

1.2.36 SDSTS—Stream Descriptor Status Register

1.2.37 SDLPIB—Stream Descriptor Link Position in Buffer

1.2.38 SDCBL—Stream Descriptor Cyclic Buffer Length Register

1.2.39 SDLVI—Stream Descriptor Last Valid Index Register

1.2.40 SDFIFOW—Stream Descript or FIF O Wa term ar k Reg ist er

1.2.41 SDFIFOS—Stream Descriptor FIFO Size Register

1.2.42 SDFMT—Stream Descriptor Format Register

(Intel

High Definition Audio Controller—D27:F0).................................................51

(Intel

High Definition Audio Controller—D27:F0).................................................52

(Intel

High Definition Audio Controller—D27:F0).................................................52

(Intel

High Definition Audio Controller—D27:F0).................................................53

(Intel

High Definition Audio Controller—D27:F0).................................................53

(Intel

High Definition Audio Controller—D27:F0).................................................53

(Intel

High Definition Audio Controller—D27:F0).................................................54

(Intel

High Definition Audio Controller—D27:F0).................................................54

(Intel

High Definition Audio Controller—D27:F0).................................................55

(Intel

High Definition Audio Controller—D27:F0).................................................55

(Intel

High Definition Audio Controller—D27:F0).................................................55

(Intel

High Definition Audio Controller—D27:F0).................................................57

(Intel

High Definition Audio Controller—D27:F0).................................................58

(Intel

High Definition Audio Controller—D27:F0).................................................59

(Intel

High Definition Audio Controller—D27:F0).................................................59

(Intel

High Definition Audio Controller—D27:F0).................................................60

(Intel

High Definition Audio Controller—D27:F0).................................................61

High Definition Audio Controller—D27:F0)...................................58

1.2.43 SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register

(Intel

High Definition Audio Controller—D27:F0).................................................62

1.2.44 SDBDPU—Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (Intel

High Definition Audio Controller—D27:F0) 62

2 AC ’97 Audio Controller Registers (D30:F2) .............................................................................63

2.1 AC ’97 Audio PCI Configuration Space

(Audio—D30:F2).................................................................................................................63

2.1.1 VID—Vendor Identification Register (Audio—D30:F2)................ .... ... ... ...... .... ... ...64

2.1.2 DID—Device Identification Register (Audio—D30:F2)...........................................64

2.1.3 PCICMD—PCI Command Register (Audio—D30:F2) ...........................................65

2.1.4 PCISTS—PCI Status Register (Audio—D30:F2)...................................................66

2.1.5 RID—Revision Identification Register (Audio—D30:F2)........................................67

2.1.6 PI—Programming Interface Register (Audio—D30:F2).........................................67

2.1.7 SCC—Sub Class Code Register (Audio—D30:F2) ...............................................67

Programmer’s Reference Manual 7

Contents

2.1.8 BCC—Base Class Code Register (Audio—D30:F2) .............................................67

2.1.9 HEADTYP—Header Type Register (Audio—D30:F2)...........................................68

2.1.10 NAMBAR—Native Audio Mixer Base Address Register

(Audio—D30:F2)....................................................................................................68

2.1.11 NABMBAR—Native Audio Bus Mastering Base Address

2.1.12 MMBAR—Mixer Base Address Register (Audio—D30:F2) ...................................69

2.1.13 MBBAR—Bus Master Base Address Register

(Audio—D30:F2)....................................................................................................70

2.1.14 SVID—Subsystem Vendor Identification Register

(Audio—D30:F2)....................................................................................................70

2.1.15 SID—Subsystem Identification Register (Audio—D30:F2)....................................71

2.1.16 CAP_PTR—Capabilities Pointer Register (Audio—D30:F2) .................................71

2.1.17 INT_LN—Interrupt Line Register (Audio—D30:F2) ...............................................71

2.1.18 INT_PN—Interrupt Pin Register (Audio—D30:F2) ................................................72

2.1.19 PCID—Programmable Codec Identification Register

(Audio—D30:F2)....................................................................................................72

2.1.20 CFG—Configuration Register (Audio—D30:F2)....................................................72

2.1.21 PID—PCI Power Management Capability Identification

2.1.22 PC—Power Management Capabilities Register

(Audio—D30:F2)....................................................................................................73

2.1.23 PCS—Power Management Control and Status Register

(Audio—D30:F2)....................................................................................................74

2.2 AC ’97 Audio I/O Space (D30:F2).......................................................................................75

2.2.1 x_BDBAR—Buffer Descriptor Base Address Register

(Audio—D30:F2)....................................................................................................78

2.2.2 x_CIV—Current Index Value Register (Audio—D30:F2).......................................79

2.2.3 x_LVI—Last Valid Index Register (Audio—D30:F2)..............................................79

2.2.4 x_SR—Status Register (Audio—D30:F2)..............................................................80

2.2.5 x_PICB—Position In Current Buffer Register

(Audio—D30:F2)....................................................................................................81

2.2.6 x_PIV—Prefetched Index Value Register (Audio—D30:F2)..................................81

2.2.7 x_CR—Control Register (Audio—D30:F2) ............................................................82

2.2.8 GLOB_CNT—Global Control Register (Audio—D30:F2) ......................................83

2.2.9 GLOB_STA—Global Status Register (Audio—D30:F2) ........................................85

2.2.10 CAS—Codec Access Semaphore Register (Audio—D30:F2)...............................87

2.2.11 SDM—SDATA_IN Map Register (Audio—D30:F2) ...............................................87

3 AC ’97 Modem Controller Registers (D30:F3)...........................................................................89

3.1 AC ’97 Modem PCI Configuration Space (D30:F3)............................................................89

3.1.1 VID—Vendor Identification Register (Modem—D30:F3) .......................................90

3.1.2 DID—Device Identification Register (Modem—D30:F3)........................................90

3.1.3 PCICMD—PCI Command Register (Modem—D30:F3) ........................................90

3.1.4 PCISTS—PCI Status Register (Modem—D30:F3)................................................91

3.1.5 RID—Revision Identification Register (Modem—D30:F3).....................................92

3.1.6 PI—Programming Interface Register (Modem—D30:F3)......................................92

3.1.7 SCC—Sub Class Code Register (Modem—D30:F3) ............................................92

3.1.8 BCC—Base Class Code Register (Modem—D30:F3)...........................................92

3.1.9 HEADTYP—Header Type Register (Modem—D30:F3) ........................................93

3.1.10 MMBAR—Modem Mixer Base Address Register

8 Programmer’s Reference Manual

Contents

(Modem—D30:F3).................................................................................................93

3.1.11 MBAR—Modem Base Address Register (Modem—D30:F3) ................................94

3.1.12 SVID—Subsystem Vendor Identification Register

(Modem—D30:F3).................................................................................................94

3.1.13 SID—Subsystem Identification Register (Modem—D30:F3) .................................95

3.1.14 CAP_PTR—Capabilities Pointer Register (Modem—D30:F3)...............................95

3.1.15 INT_LN—Interrupt Line Register (Modem—D30:F3).............................................95

3.1.16 INT_PIN—Interrupt Pin Register (Modem—D30:F3).............................................96

3.1.17 PID—PCI Power Management Capability Identification

3.1.18 PC—Power Management Capabilities Register

(Modem—D30:F3).................................................................................................96

3.1.19 PCS—Power Management Control and Status Register

(Modem—D30:F3).................................................................................................97

3.2 AC ’97 Modem I/O Space (D30:F3)....................................................................................98

3.2.1 x_BDBAR—Buffer Descriptor List Base Address Register

(Modem—D30:F3)...............................................................................................100

3.2.2 x_CIV—Current Index Value Register (Modem—D30:F3) ..................................100

3.2.3 x_LVI—Last Valid Index Register (Modem—D30:F3) .........................................100

3.2.4 x_SR—Status Register (Modem—D30:F3) .........................................................101

3.2.5 x_PICB—Position in Current Buffer Register

(Modem—D30:F3)...............................................................................................102

3.2.6 x_PIV—Prefetch Index Value Reg i st er

(Modem—D30:F3)...............................................................................................102

3.2.7 x_CR—Control Register (Modem—D30:F3)........................................................103

3.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3)..................................104

3.2.9 GLOB_STA—Global Status Register (Modem—D30:F3)....................................105

3.2.10 CAS—Codec Access Semaphore Register

(Modem—D30:F3)...............................................................................................107

4 Intel® High Definition Audio BIOS Considerations................................................................109

4.1 Intel

High Definition Audio/AC’ 97 Signal Mode Selection .............................................109

4.1.1 Intel

4.1.2 Intel

High Definition Audio/AC’ 97 Codec Detection..........................................110

High Definition Audio Codec Initialization ..................................................112

4.1.2.1 Intel

High Definition Audio Codec Architecture Introduction ..............112

4.1.2.2 Codec Verb Table................................................................................113

4.1.2.3 Codec Initialization Programming Sequence.......................................116

4.1.2.4 Codec Initialization Sample Code........................................................117

4.1.3 Intel

4.2 Intel

4.3 Intel

Programmer’s Reference Manual 9

High Definition Audio Controller Configuration .......................................................125

High Definition Audio PME Event ...........................................................................126

High Definition Audio Codec Initialization on S3 Resume .........................125

Contents

Figures

4-1 Intel® ICH7 High Definition Audio/AC’ 97 Share Signals to Codecs ..............................109

4-2 Intel

High Definition Audio Codec Node Structure and Addressing..............................113

Tables

1-1 Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) ........................................................................................13

1-2 Intel

2-1 AC ‘97 Audio PCI Register Address Map (Audio—D30:F2).......................................................63

2-2 Intel

2-3 Native Audio Bus Master Control Registers ...............................................................................77

3-1 AC ‘97 Modem PCI Register Address Map (Modem—D30:F3) .................................................89

3-2 Intel

3-3 Modem Registers ...................................... .................................................................................99

High Definition Audio PCI Register Address Map

(Intel

High Definition Audio D27:F0).........................................................................................36

ICH7 Audio Mixer Register Configuration........................................................................75

ICH7 Modem Mixer Register Configuration......................................................................98

10 Programmer’s Reference Manual

Revision History

Revision Description Date

-001 • Initial release April 2005

Contents

Programmer’s Reference Manual 11

Contents

12 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1 Intel

Controller Registers (D27:F0)

The Intel® HD Audio controller resides in PCI Device 27, Function 0 on bus 0. This function contains a set of DMA engines that are used to move samples of digitally encoded data between system memory and external codecs.

Note: All registers in this function (including memory-mapped registers) must be addressable in byte,

word, and DWord quantities. The software must always make register accesses on natural boundaries (i.e. DWord accesses must be on DWord boundaries; word accesses on word boundaries, etc.) In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the Intel® HD Audio memory-mapped space, the results are undefined.

Note: Users interested in providing feedback on the Intel

implement the Intel execute the Intel information, contact nextgenaudio@intel.com.

1.1 Intel

High Definition Audio

High Definition Audio specification into a future product will need to

High Definition Audio Specification Developer’s Agreement. For more

High Definition Audio PCI Configuration

HD Audio specification or planning to

Space

(Intel

Note: Address locations that are not shown should be treated as Reserved.

Table 1-1. Intel

(Intel

Offset Mnemonic Register Name Default Access

00h–01h VID Vendor Identification 8086h RO 02h–03h DID Device Identification 04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0010h R/WC, RO

10h–13h HDBARL

High Definition Audio— D27:F0)

High Definition Audio PCI Register Address Map

High Definition Audio D27:F0)

08h RID Revision Identification

09h PI Programming Interface 00h RO 0Ah SCC Sub Class Code 03h RO 0Bh BCC Base Class Code 04h RO 0Ch CLS Cache Line Size 00h R/W 0Dh LT Latency Timer 00h RO 0Eh HEADTYP Header Type 00h RO

High Definition Audio Lower Base Address

Intel (Memory)

See register

description.

See register

description.

00000004h R/W, RO

Programmer’s Reference Manual 13

Intel® High Definition Audio Controller Registers (D27:F0)

Table 1-1. Intel® High Definition Audio PCI Register Address Map

(Intel

High Definition Audio D27:F0)

14h–17h HDBARU

2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAPPTR Capability List Pointer 50h RO

3Ch INTLN Interrupt Line 00h R/W 3Dh INTPN Interrupt Pin

40h HDCTL Intel High Definition Audio Control 00h R/W, RO 44h TCSEL Traffic Class Select 00h R/W

4Dh DCKSTS Docking Status 80h R/WO, RO 50h–51h PID PCI Power Management Capability ID 6001h RO 52h–53h PC Power Management Capabilities C842 RO

54h–57h PCS Power Management Control and Status 00000000h 60h–61h MID MSI Capability ID 7005h RO

62h–63h MMC MSI Message Control 0080h R/W, RO 64h–67h MMLA MSI Message Lower Address 00000000h R/W, RO 68h–6Bh MMUA SMI Message Upper Address 00000000h R/W

6Ch–6Dh MMD MSI Message Data 0000h R/W

70h–71h PXID PCI Express* Capability Identifiers 0010h RO 72h–73h PXC PCI Express Capabilities 0091h RO 74h–77h DEVCAP Device Capabilities 00000000h RO, R/WO 78h–79h DEVC Device Control 0800h R/W, RO

7Ah–7Bh DEVS Device Status 0010h RO 100h–103h VCCAP Virtual Channel Enhanced Capability Header 13010002h RO 104h–107h PVCCAP1 Port VC Capability Register 1 00000001h RO 108h–10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO

10Ch–10D PVCCTL Port VC Control 0000h RO 10Eh–10Fh PVCSTS Port VC Status 0000h RO 110h–103h VC0CAP VC0 Resource Capability 00000000h RO 114h–117h VC0CTL VC0 Resource Control 800000FFh R/W, RO 11Ah–11Bh VC0STS VC0 Resource Status 0000h RO 11Ch–11Fh VCiCAP VCi Resource Capability 00000000h RO 120h–123h VCiCTL VCi Resource Control 00000000h R/W, RO 126h–127h VCiSTS VCi Resource Status 0000h RO

130h–133h RCCAP 134h–137h ESD Element Self Description 0F000100h RO

140h–143h L1DESC Link 1 Description 00000001h RO 148h–14Bh L1ADDL Link 1 Lower Address

14Ch–14Fh L1ADDU Link 1 Upper Address 00000000h RO

Intel® High Definition Audio Upper Base Address (Memory)

Root Complex Link Declaration Enhanced Capability Header

00000000h R/W

See Register

Description

R/W, RO,

R/WC

00010005h RO

See Register

Description

14 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.1 VID—Vendor Identification Register

(Intel

Offset: 00h-01h Attribute: RO

Default Value: 8086h Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

High Definition Audio Controller—D27:F0)

1.1.2 DID—Device Identification Register

(Intel

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

High Definition Audio Controller—D27:F0)

Bit Description

15:0

Device ID — RO. This is a 16-bit value assigned to the Intel controller. Refer to the Intel value of the Device ID Register.

I/O Controller Hub 7 (ICH7) Family Specification Update for the

ICH7 Intel

High Definition Audio

Programmer’s Reference Manual 15

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.3 PCICMD—PCI Command Register

(Intel

Offset Address: 04h–05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits

High Definition Audio Controller—D27:F0)

Bit Description

15:11 Reserved

Interrupt Disable (ID) — R/W.

0= The INTx# signals may be asserted. 1= The Intel

NOTE: This bit does not affect the generation of MSIs.

9 Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.

SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the ICH7 Intel High Definition

Audio Controller. 7 Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0. 6 Parity Error Response (PER) — RO. Not implemented. Hardwired to 0. 5 VGA Palette Snoop (VPS). Not implemented. Hardwired to 0. 4 Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0. 3 Special Cycle Enable (SCE). Not implemented. Hardwired to 0.

Bus Master Enable (BME) — R/W. Controls standard PCI Express* bus mastering capabilities

for Memory and I/O, reads and writes. Note that this bit also controls MSI generation since MSIs

are essentially Memory writes.

0 = Disable

1 = Enable

Memory Space Enable (MSE) — R/W. Enables memory space addresses to the Intel High

Definition Audio controller. 1

0 = Disable

1 = Enable

I/O Space Enable (IOSE)—RO. Hardwired to 0 since the Intel High Definition Audio controller

does not implement I/O space.

High Definition Audio controller’s INTx# signal will be de-asserted

16 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.4 PCISTS—PCI Status Register

(Intel

Offset Address: 06h–07h Attribute: RO, R/WC Default Value: 0010h Size: 16 bits

High Definition Audio Controller—D27:F0)

Bit Description

15 Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0. 14 SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.

Received Master Abort (RMA) — R/WC. Software clears this bit by writing a 1 to it. 0 = No master abort received.

1 = The Intel

master abort. When set, the Intel High Definition Audio controller clears the run bit for the

channel that received the abort. 12 Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0. 11 Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. Does not apply. Hardwired to 0.

8 Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0. 7 Fast Back to Back Capable (FB2BC) — RO. Does not apply. Hardwired to 0. 6 Reserved. 5 66 MHz Capable (66MHZ_CAP) — RO. Does not apply. Hardwired to 0.

Capabilities List (CAP_LIST) — RO. Hardwired to 1. Indicates that the controller contains a

capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. Interrupt Status (IS) — RO.

0 = This bit is 0 after the interrupt is cleared.

1 = This bit is 1 when the INTx# is asserted. Note that this bit is not set by an MSI.

2:0 Reserved.

High Definition Audio controller sets this bit when, as a bus master, it receives a

1.1.5 RID—Revision Identification Register

(Intel

Offset: 08h Attribute: RO Default Value: See bit description Size: 8 Bits

Bit Description

7:0

Programmer’s Reference Manual 17

High Definition Audio Controller—D27:F0)

Revision ID — RO. Refer to the Intel the value of the Revision ID Register.

I/O Controller Hub 7 (ICH7) Family Specification Update for

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.6 PI—Programming Interface Register

(Intel

Offset: 09h Attribute: RO Default Value: 00h Size: 8 bits

High Definition Audio Controller—D27:F0)

Bit Description

7:0 Programming Interface — RO.

1.1.7 SCC—Sub Class Code Register

(Intel

Address Offset: 0Ah Attribute: RO Default Value: 03h Size: 8 bits

High Definition Audio Controller—D27:F0)

Bit Description

Sub Class Code (SCC) — RO.

7:0

03h = Audio Device

1.1.8 BCC—Base Class Code Register

(Intel

High Definition Audio Controller—D27:F0)

Address Offset: 0Bh Attribute: RO Default Value: 04h Size: 8 bits

Bit Description

Base Class Code (BCC) — RO.

7:0

04h = Multimedia device

1.1.9 CLS—Cache Line Size Register

(Intel

Address Offset: 0Ch Attribute: R/W Default Value: 00h Size: 8 bits

7:0 Cache Line Size — R/W. Implemented as R/W register, but has no functional impact to the ICH7.

High Definition Audio Controller—D27:F0)

Bit Description

18 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.10 LT—Latency Timer Register

(Intel

Address Offset: 0Dh Attribute: RO Default Value: 00h Size: 8 bits

Bit Description

7:0 Latency Timer — RO. Hardwired to 00

High Definition Audio Controller—D27:F0)

1.1.11 HEADTYP—Header Type Register

(Intel

Address Offset: 0Eh Attribute: RO Default Value: 00h Size: 8 bits

Bit Description

7:0 Header Type — RO. Hardwired to 00.

1.1.12 HDBARL—Intel

High Definition Audio Controller—D27:F0)

High Definition Audio Lower Base

Address Register

(Intel

High Definition Audio—D27:F0)

Address Offset: 10h-13h Attribute: R/W, RO Default Value: 00000004h Size: 32 bits

Bit Description

31:14

Lower Base Address (LBA) — R/W. This field contains the base address for the Intel Definition Audio controller’s memory mapped configuration registers; 16 KB are requested by hardwiring bits 13:4 to 0s.

13:4 RO. Hardwired to 0’s

3 Prefetchable (PREF) — RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable.

Address Range (ADDRNG) — RO. Hardwired to 10b, indicating that this BAR can be located

2:1

anywhere in 64-bit address space.

0 Space Type (SPTYP) — RO. Hardwired to 0. Indicates this BAR is located in memory space.

1.1.13 HDBARU—Intel Address Register

(Intel

Address Offset: 14h-17h Attribute: R/W Default Value: 00000000h Size: 32 bits

Bit Description

31:0

High Definition Audio Controller—D27:F0)

Upper Base Address (UBA) — R/W. This field provides the upper 32 bits of the Base address for

the Intel

High Definition Audio controller’s memory mapped configuration registers.

High Definition Audio Upper Base

High

Programmer’s Reference Manual 19

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.14 SVID—Subsystem Vendor Identification Register

(Intel

Address Offset: 2Ch–2Dh Attribute: R/WO Default Value: 0000h Size: 16 bits

High Definition Audio Controller—D27:F0)

The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh), enable the operating environment to distinguish one audio subsystem from the other(s).

This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3

Bit Description

15:0 Subsystem Vendor ID — R/WO.

to D0 transition.

HOT

1.1.15 SID—Subsystem Identification Register

(Intel

Address Offset: 2Eh–2Fh Attribute: R/WO Default Value: 0000h Size: 16 bits

The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s).

High Definition Audio Controller—D27:F0)

This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3

Bit Description

15:0 Subsystem ID — R/WO.

to D0 transition.

HOT

20 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.16 CAPPTR—Capabilities Pointer Register (Audio—D30:F2)

Address Offset: 34h Attribute: RO Default Value: 50h Size: 8 bits

This register indicates the offset for the capability pointer.

Bit Description

Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer offset is

7:0

offset 50h (Power Management Capability).

1.1.17 INTLN—Interrupt Line Register

(Intel

Address Offset: 3Ch Attribute: R/W Default Value: 00h Size: 8 bits

Bit Description

7:0

High Definition Audio Controller—D27:F0)

Interrupt Line (INT_LN) — R/W. This data is not used by the Intel to software the interrupt line that is connected to the interrupt pin.

1.1.18 INTPN—Interrupt Pin Register

(Intel

Address Offset: 3Dh Attribute: RO Default Value: See Description Size: 8 bits

Bit Description

7:4 Reserved. 3:0

High Definition Audio Controller—D27:F0)

Interrupt Pin — RO. This reflects the value of D27IP.ZIP (Chipset Config Registers:Offset 3110h: bits 3:0).

ICH7. It is used to communicate

Programmer’s Reference Manual 21

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.19 HDCTL—Intel

(Intel

Address Offset: 40h Attribute: R/W, RO Default Value: 00h Size: 8 bits

7:4 Reserved.

High Definition Audio Controller—D27:F0)

Bit Description

BITCLK Detect Clear (CLKDETCLR) — R/W.

0 = Clock detect circuit is operational and maybe enabled. 1 = Writing a 1 to this bit clears bit 1 (CLKDET#) in this register. CLKDET# bit remains clear when

this bit is set to 1.

NOTE: This bit is not affected by the D3 BITCLK Detect Enable (CLKDETEN) — R/W.

0 = Latches the current state of bit 1 (CLKDET#) in this register 1 = Enables the clock detection circuit

NOTE: This bit is not affected by the D3 BITCLK Detected Inverted (CLKDET#) — RO. This bit is modified by hardware.

It is set to 0 when the Intel AC’97 codec on the link

NOTES:

1. Bit 2 (CLKDETEN) and bit 3 (CLKDETCLR) in this register control the operation of this bit and must be manipulated correctly in order to get a valid CLKDET# indicator.

2. This bit is not affected by the D3

High Definition Audio/AC ‘97 Signal Mode — R/W. This bit selects the shared Intel High

Intel

Definition Audio/AC ‘97 signals. 0 = AC ’97 mode is selected (Default) 1 = Intel High Definition Audio mode is selected

NOTES:

1. This bit has no effect on the visibility of the Intel High Definition Audio and AC ’97 function configuration space.

2. This bit is in the resume well and only clear on a power-on reset. Software must not makes assumptions about the reset state of this bit and must set it appropriately.

High Definition Audio Control Register

to D0 transition.

HOT

to D0 transition.

HOT

ICH7 detects that the BITCLK is toggling, indicating the presence of an

to D0 transition.

HOT

22 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.20 TCSEL—Traffic Class Select Register

(Intel

Address Offset: 44h Attribute: R/W Default Value: 00h Size: 8 bits

This register assigned the value to be placed in the TC field. CORB and RIRB data will always be assigned TC0.

Bit Description

7:3 Reserved.

2:0

High Definition Audio Controller—D27:F0)

Intel

HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W. This register assigns the

value to be placed in the Traffic Class field for input data, output data, and buffer descriptor transactions.

000 = TC0 001 = TC1 010 = TC2 011 = TC3 100 = TC4 101 = TC5 110 = TC6 111 = TC7

NOTE: These bits are not reset on D3

to D0 transition; however, they are reset by PLTRST#.

HOT

Programmer’s Reference Manual 23

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.21 DCKSTS—Docking Status Register

(Intel

Address Offset: 4Dh Attribute: R/WO, RO Default Value: 80h Size: 8 bits

High Definition Audio Controller—D27:F0)

Bit Description

7 BIOS is required to clear this bit.

6:1 Reserved.

0 Reserved.

1.1.22 PID—PCI Power Management Capability ID Register

(Intel

Address Offset: 50h–51h Attribute: RO Default Value: 6001h Size: 16 bits

15:8 Next Capability (Next) — RO. Hardwired to 60h. Points to the next capability structure (MSI).

7:0

High Definition Audio Controller—D27:F0)

Bit Description

Cap ID (CAP) — RO. Hardwired to 01h. Indicates that this pointer is a PCI power management capability.

24 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.23 PC—Power Management Capabilities Register

(Intel

High Definition Audio Controller—D27:F0)

Address Offset: 52h–53h Attribute: RO Default Value: C842h Size: 16 bits

Bit Description

15:11

PME Support — RO. Hardwired to 11001b. Indicates PME# can be generated from D3 and D0 states.

10 D2 Support — RO. Hardwired to 0. Indicates that D2 state is not supported.

9 D1 Support —RO. Hardwired to 0. Indicates that D1 state is not supported.

Aux Current — RO. Hardwired to 001b. Reports 55 mA maximum suspend well current required

8:6

when in the D3 Device Specific Initialization (DSI) — RO. Hardwired to 0. Indicates that no device specific

initialization is required. 4 Reserved 3 PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.

Version — RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power Management

2:0

Specification.

COLD

state.

1.1.24 PCS—Power Management Control and Status Register

(Intel

High Definition Audio Controller—D27:F0)

Address Offset: 54h–57h Attribute: RO, R/W, R/WC Default Value: 00000000h Size: 32 bits

Bit Description

31:24 Data — RO. Does not apply. Hardwired to 0.

23 Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0. 22 B2/B3 Support — RO. Does not apply. Hardwired to 0.

21:16 Reserved.

PME Status (PMES) — R/WC.

0 = Software clears the bit by writing a 1 to it.

1 = This bit is set when the Intel

14:9 Reserved

7:2 Reserved

signal independent of the state of the PME_EN bit (bit 8 in this register)

This bit is in the resume well and only cleared on a power-on reset. Software must not make

assumptions about the reset state of this bit and must set it appropriately.

PME Enable (PMEE) — R/W.

0 = Disable

1 = when set and if corresponding PMES also set, the Intel High Definition Audio controller sets the

AC97_STS bit in the GPE0_STS register (PMBASE +28h). The AC97_STS bit is shared by AC ’97 and Intel High Definition Audio functions since they are mutually exclusive.

This bit is in the resume well and only cleared on a power-on reset. Software must not make

assumptions about the reset state of this bit and must set it appropriately.

High Definition Audio controller would normally assert the PME#

Programmer’s Reference Manual 25

Intel® High Definition Audio Controller Registers (D27:F0)

Bit Description

Power State (PS) — R/W. This field is used both to determine the current power state of the Intel

High Definition Audio controller and to set a new power state. 00 = D0 state 11 = D3 Others = reserved

1:0

NOTES:

1. If software attempts to write a value of 01b or 10b in to this field, the write operation must

2. When in the D3

3. When software changes this value from D3

state

HOT

complete normally; however, the data is discarded and no state change occurs. available, but the I/O and memory space are not. Additionally, interrupts are blocked. is generated, and software must re-initialize the function.

states, the Intel High Definition Audio controller’s configuration space is

HOT

state to the D0 state, an internal warm (soft) reset

HOT

1.1.25 MID—MSI Capability ID Register

(Intel

High Definition Audio Controller—D27:F0)

Address Offset: 60h–61h Attribute: RO Default Value: 7005h Size: 16 bits

Bit Description

15:8 Next Capability (Next) — RO. Hardwired to 70h. Points to the PCI Express* capability structure.

7:0 Cap ID (CAP) — RO. Hardwired to 05h. Indicates that this pointer is a MSI capability

1.1.26 MMC—MSI Message Control Register

(Intel

Address Offset: 62h–63h Attribute: RO, R/W Default Value: 0080h Size: 16 bits

15:8 Reserved

6:4 3:1 Multiple Message Capable (MMC) — RO. Hardwired to 0 indicating request for 1 message.

High Definition Audio Controller—D27:F0)

Bit Description

64b Address Capability (64ADD) — RO. Hardwired to 1 indicating the ability to generate a 64-bit

message address Multiple Message Enable (MME) — RO. Normally this is a R/W register. However, since only 1

message is supported, these bits are hardwired to 000 = 1 message.

MSI Enable (ME) — R/W.

0 = an MSI may not be generated 1 = an MSI will be generated instead of an INTx signal.

26 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.27 MMLA—MSI Message Lower Address Register

(Intel

Address Offset: 64h–67h Attribute: RO, R/W Default Value: 00000000h Size: 32 bits

Bit Description

31:2 Message Lower Address (MLA) — R/W. Lower address used for MSI message.

1:0 Reserved.

High Definition Audio Controller—D27:F0)

1.1.28 MMUA—MSI Message Upper Address Register

(Intel

Address Offset: 68h–6Bh Attribute: R/W Default Value: 00000000h Size: 32 bits

Bit Description

31:0 Message Upper Address (MUA) — R/W. Upper 32-bits of address used for MSI message.

High Definition Audio Controller—D27:F0)

1.1.29 MMD—MSI Message Data Register

(Intel

High Definition Audio Controller—D27:F0)

Address Offset: 6Ch–6Dh Attribute: R/W Default Value: 0000h Size: 16 bits

Bit Description

15:0 Message Data (MD) — R/W. Data used for MSI message.

1.1.30 PXID—PCI Express* Capability ID Register

(Intel

Address Offset: 70h-71h Attribute: RO Default Value: 0010h Size: 16 bits

Bit Description

15:8

7:0

High Definition Audio Controller—D27:F0)

Next Capability (Next) — RO. Hardwired to 0. Indicates that this is the last capability structure in the

list.

Cap ID (CAP) — RO. Hardwired to 10h. Indicates that this pointer is a PCI Express* capability

structure.

Programmer’s Reference Manual 27

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.31 PXC—PCI Express* Capabilities Register

(Intel

Address Offset: 72h–73h Attribute: RO Default Value: 0091h Size: 16 bits

15:14 Reserved

13:9 Interrupt Message Number (IMN) — RO. Hardwired to 0.

7:4 3:0 Capability Version (CV) — RO. Hardwired to 0001b. Indicates version #1 PCI Express capability.

High Definition Audio Controller—D27:F0)

Bit Description

8 Slot Implemented (SI) — RO. Hardwired to 0.

Device/Port Type (DPT) — RO. Hardwired to 1001b. Indicates that this is a Root Complex Integrated endpoint device.

1.1.32 DEVCAP—Device Capabilities Register

(Intel

Address Offset: 74h–77h Attribute: R/WO, RO Default Value: 00000000h Size: 32 bits

31:28 Reserved 27:26 Captured Slot Power Limit Scale (SPLS) — RO. Hardwired to 0. 25:18 Captured Slot Power Limit Value (SPLV) — RO. Hardwired to 0. 17:15 Reserved

11:9 Endpoint L1 Acceptable Latency — R/WO.

8:6 Endpoint L0s Acceptable Latency — R/WO.

4:3

2:0

High Definition Audio Controller—D27:F0)

Bit Description

14 Power Indicator Present — RO. Hardwired to 0. 13 Attention Indicator Present — RO. Hardwired to 0. 12 Attention Button Present — RO. Hardwired to 0.

5 Extended Tag Field Support — RO. Hardwired to 0. Indicates 5-bit tag field support

Phantom Functions Supported — RO. Hardwired to 0. Indicates that phantom functions are not supported.

Max Payload Size Supported — RO. Hardwired to 0. Indicates 128-B maximum payload size capability.

28 Programmer’s Reference Manual

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.33 DEVC—Device Control Register

(Intel

Address Offset: 78h–79h Attribute: R/W, RO Default Value: 0800h Size: 16 bits

Bit Description

15 Reserved

14:12 Max Read Request Size — RO. Hardwired to 0 enabling 128B maximum read request size.

7:5 Max Payload Size — RO. Hardwired to 0 indicating 128B.

High Definition Audio Controller—D27:F0)

No Snoop Enable (NSNPEN) — R/W.

0 = The Intel

isochronous transfers will not use VC1 (VCi) even if it is enabled since VC1 is never snooped.

9 Phantom Function Enable — RO. Hardwired to 0 disabling phantom functions. 8 Extended Tag Field Enable — RO. Hardwired to 0 enabling 5-bit tag.

4 Enable Relaxed Ordering — RO. Hardwired to 0 disabling relaxed ordering. 3 Unsupported Request Reporting Enable — RO. Not implemented. Hardwired to 0. 2 Fatal Error Reporting Enable — RO. Not implemented. Hardwired to 0. 1 Non-Fatal Error Reporting Enable — RO. Not implemented. Hardwired to 0. 0 Correctable Error Reporting Enable — RO. Not implemented. Hardwired to 0.

Isochronous transfers will use VC0.

1 = The Intel High Definition Audio controller is permitted to set the No Snoop bit in the Requester

Attributes of a bus master transaction. In this case, VC0 or VC1 may be used for isochronous transfers.

NOTE: This bit is not reset on D3

Auxiliary Power Enable — RO. Hardwired to 0, indicating that Intel High Definition Audio device

does not draw AUX power.

High Definition Audio controller will not set the No Snoop bit. In this case,

to D0 transition; however, it is reset by PLTRST#.

HOT

1.1.34 DEVS—Device Status Register

(Intel

Address Offset: 7Ah–7Bh Attribute: RO Default Value: 0010h Size: 16 bits

Bit Description

15:6 Reserved

Programmer’s Reference Manual 29

High Definition Audio Controller—D27:F0)

Transactions Pending — RO.

0 = Indicates that completions for all non-posted requests have been received.

1 = Indicates that Intel

not been completed. 4 AUX Power Detected — RO. Hardwired to 1 indicating the device is connected to resume power. 3 Unsupported Request Detected — RO. Not implemented. Hardwired to 0. 2 Fatal Error Detected — RO. Not implemented. Hardwired to 0. 1 Non-Fatal Error Detected — RO. Not implemented. Hardwired to 0. 0 Correctable Error Detected — RO. Not implemented. Hardwired to 0.

High Definition Audio controller has issued non-posted requests that have

Intel® High Definition Audio Controller Registers (D27:F0)

1.1.35 VCCAP—Virtual Channel Enhanced Capability Header

(Intel

Address Offset: 100h–103h Attribute: RO Default Value: 13010002h Size: 32 bits

31:20 19:16 Capability Version — RO. Hardwired to 1h.

15:0 PCI Express* Extended Capability — RO. Hardwired to 0002h.

High Definition Audio Controller—D27:F0)

Bit Description

Next Capability Offset — RO. Hardwired to 130h. Points to the next capability header that is the Root Complex Link Declaration Enhanced Capability Header.

1.1.36 PVCCAP1—Port VC Capability Register 1

(Intel

Address Offset: 104h–107h Attribute: RO Default Value: 00000001h Size: 32 bits

31:12 Reserved.

11:10 Port Arbitration Table Entry Size — RO. Hardwired to 0 since this is an endpoint device.

9:8 Reference Clock — RO. Hardwired to 0 since this is an endpoint device.

6:4

2:0

High Definition Audio Controller—D27:F0)

Bit Description

7 Reserved.

Low Priority Extended VC Count — RO. Hardwired to 0. Indicates that only VC0 belongs to the low priority VC group.

3 Reserved.

Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in addition to VC0) is supported by the Intel

High Definition Audio controller.

30 Programmer’s Reference Manual

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Intel 307017-001 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® I/O Controller Hub 7 (ICH7)/ Intel® High Definition Audio/ AC’97

Contents

Figures

Tables

Revision History

Intel® High Definition Audio Controller Registers (D27:F0)