INTEL 28F800C3, 28F160C3, 28F320C3, 28F640C3 User Manual

Intel£ Advanced+ Boot Block Flash

Memory (C3)

28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16)

Datasheet

Product Features

■Flexible SmartVoltage Technology

—2.7 V– 3.6 V Read/Program/Erase

—12 V for Fast Production Programming

■1.65 V–2.5 V or 2.7 V–3.6 V I/O Option

—Reduces Overall System Power

■High Performance

—2.7 V– 3.6 V: 70 ns Max Access Time

■Optimized Architecture for Code Plus Data Storage

—Eight 4 Kword Blocks, Top or Bottom Parameter Boot

—Up to One Hundred-Twenty-Seven 32 Kword Blocks

—Fast Program Suspend Capability

—Fast Erase Suspend Capability

■Flexible Block Locking

—Lock/Unlock Any Block

—Full Protection on Power-Up

—WP# Pin for Hardware Block Protection

■Low Power Consumption

—9 mA Typical Read

—7 A Typical Standby with Automatic Power Savings Feature (APS)

■Extended Temperature Operation

—–40 °C to +85 °C

■128-bit Protection Register

—64 bit Unique Device Identifier

—64 bit User Programmable OTP Cells

■Extended Cycling Capability

—Minimum 100,000 Block Erase Cycles

■Software

—Intel® Flash Data Integrator (FDI)

—Supports Top or Bottom Boot Storage, Streaming Data (e.g., voice)

—Intel Basic Command Set

—Common Flash Interface (CFI)

■Standard Surface Mount Packaging

—48-Ball BGA*/VFBGA

—64-Ball Easy BGA Packages

—48-Lead TSOP Package

■ETOX™ VIII (0.13 m) Flash

Technology

—16, 32 Mbit

■ETOX™ VII (0.18 m) Flash Technology

—16, 32, 64 Mbit

■ETOX™ VI (0.25 m) Flash Technology

—8, 16 and 32 Mbit

The Intel® Advanced+ Book Block Flash Memory (C3) device, manufactured on Intel’s latest 0.13 m and 0.18 m technologies, represents a feature-rich solution for low-power applications. The C3 device incorporates low-voltage capability (3 V read, program, and erase) with highspeed, low-power operation. Flexible block locking allows any block to be independently locked or unlocked. Add to this the Intel® Flash Data Integrator (FDI) software and you have a costeffective, flexible, monolithic code plus data storage solution. Intel® Advanced+ Boot Block Flash Memory (C3) products will be available in 48-lead TSOP, 48-ball CSP, and 64-ball Easy BGA packages. Additional information on this product family can be obtained by accessing the Intel® Flash website: http://www.intel.com/design/flash.

Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number: 290645-017

October 2003

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright © Intel Corporation, 2003

*Third-party brands and names are the property of their respective owners.

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Datasheet

					Contents
Contents
1.0	Introduction		....................................................................................................................................		7
	1.1	Document ...............................................................................................................Purpose			7
	1.2	Nomenclature .......................................................................................................................			7
	1.3	Conventions ..........................................................................................................................			7
2.0	Device Description ........................................................................................................................				8
	2.1	Product .................................................................................................................Overview			8
	2.2	Ballout ....................................................................................................................Diagram			8
	2.3	Signal .............................................................................................................Descriptions			13
	2.4	Block Diagram ....................................................................................................................			14
	2.5	Memory .......................................................................................................................Map			15
3.0	Device Operations .......................................................................................................................				17
	3.1	Bus Operations ...................................................................................................................			17
		3.1.1 ......................................................................................................................	Read		17
		3.1.2 ......................................................................................................................	Write		17
		3.1.3 .......................................................................................................	Output Disable		17
		3.1.4 ..................................................................................................................	Standby		18
		3.1.5 .....................................................................................................................	Reset		18
4.0	Modes of Operation .....................................................................................................................				19
	4.1	Read Mode .........................................................................................................................			19
		4.1.1 .............................................................................................................	Read Array		19
		4.1.2 .......................................................................................................	Read Identifier		19
		4.1.3 ..............................................................................................................	CFI Query		20
		4.1.4 .............................................................................................	Read Status Register		20
		.............................................................................	4.1.4.1	Clear Status Register	21
	4.2	Program ....................................................................................................................Mode			21
		4.2.1 ...........................................................................	12 - Volt Production Programming		21
		4.2.2 .....................................................................Suspending and Resuming Program			22
	4.3	Erase ........................................................................................................................Mode			22
		4.3.1 .........................................................................Suspending and Resuming Erase			23
5.0	Security Modes ............................................................................................................................				27
	5.1	Flexible ........................................................................................................Block Locking			27
		5.1.1 ..................................................................................................	Locking Operation		28
		..........................................................................................	5.1.1.1	Locked State	28
		.......................................................................................	5.1.1.2	Unlocked State	28
		....................................................................................	5.1.1.3	Lock-Down State	28
	5.2	Reading .................................................................................................Block-Lock Status			28
	5.3	Locking ........................................................................Operations during Erase Suspend			29
	5.4	Status ..........................................................................................Register Error Checking			29
	5.5	128-Bit .................................................................................................Protection Register			29
		5.5.1 ............................................................................Reading the Protection Register			30
		5.5.2 ....................................................................Programming the Protection Register			30
		5.5.3 .............................................................................Locking the Protection Register			30
	5.6	VPP Program ......................................................................................and Erase Voltages			30

Datasheet

3

Contents
		5.6.1	Program Protection................................................................................................	31
6.0	Power Consumption....................................................................................................................			32
	6.1	Active Power (Program/Erase/Read)..................................................................................		32
	6.2	Automatic Power Savings (APS) ........................................................................................		32
	6.3	Standby Power ...................................................................................................................		32
	6.4	Deep Power-Down Mode....................................................................................................		32
	6.5	Power and Reset Considerations .......................................................................................		33
		6.5.1	Power-Up/Down Characteristics ............................................................................	33
		6.5.2 RP# Connected to System Reset ..........................................................................		33
		6.5.3 VCC, VPP and RP# Transitions ............................................................................		33
	6.6	Power Supply Decoupling...................................................................................................		34
7.0 Thermal and DC Characteristics ................................................................................................				34
	7.1	Absolute Maximum Ratings ................................................................................................		34
	7.2	Operating Conditions ..........................................................................................................		35
	7.3	DC Current Characteristics.................................................................................................		35
	7.4	DC Voltage Characteristics.................................................................................................		38
8.0	AC Characteristics ......................................................................................................................			39
	8.1	AC Read Characteristics ....................................................................................................		39
	8.2	AC Write Characteristics.....................................................................................................		43
	8.3	Erase and Program Timings ...............................................................................................		47
	8.4	Reset Specifications ...........................................................................................................		48
	8.5	AC I/O Test Conditions .......................................................................................................		49
	8.6	Device Capacitance............................................................................................................		49
Appendix A Write State Machine States.............................................................................................				50
Appendix B Flow Charts ......................................................................................................................				52
Appendix C Common Flash Interface.................................................................................................				58
Appendix D Mechanical Specifications ..............................................................................................				64
Appendix E Additional Information ....................................................................................................				67
Appendix F Ordering Information .......................................................................................................				68

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Datasheet

Contents

Revision History

	Date of	Version	Description
	Revision
	05/12/98	-001	Original version
			48-Lead TSOP package diagram change
			BGA package diagrams change
			32-Mbit ordering information change (Section 6)
	07/21/98	-002	CFI Query Structure Output Table Change (Table C2)
			CFI Primary-Vendor Specific Extended Query Table Change for Optional
			Features and Command Support change (Table C8)
			Protection Register Address Change
			IPPD test conditions clarification (Section 4.3)
			BGA package top side mark information clarification (Section 6)
			Byte-Wide Protection Register Address change
			VIH Specification change (Section 4.3)
			VIL Maximum Specification change (Section 4.3)
	10/03/98	-003	ICCS test conditions clarification (Section 4.3)
			Added Command Sequence Error Note (Table 7)
			Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash
			Memory Family.
	12/04/98	-004	Added tBHWH/tBHEH and tQVBL (Section 4.6)
			Programming the Protection Register clarification (Section 3.4.2)
	12/31/98	-005	Removed all references to x8 configurations
	02/24/99	-006	Removed reference to 40-Lead TSOP from front page
			Added Easy BGA package (Section 1.2)
			Removed 1.8 V I/O references
	06/10/99	-007	Locking Operations Flowchart changed (Appendix B)
			Added tWHGL (Section 4.6)
			CFI Primary Vendor-Specific Extended Query changed (Appendix C)
	03/20/00	-008	Max ICCD changed to 25 µA
			Table 10, added note indicating VCCMax = 3.3 V for 32-Mbit device
	04/24/00	-009	Added specifications for 0.18 micron product offerings throughout document
			Added 64-Mbit density
			Changed references of 32Mbit 80ns devices to 70ns devices to reflect the
			faster product offering.
	10/12/00	-010	Changed VccMax=3.3V reference to indicate that the affected product is the
			0.25 m 32Mbit device.
			Minor text edits throughout document.
			Added 1.8v I/O operation documentation where applicable
			Added TSOP PCN ‘Pin-1’ indicator information
			Changed references in 8 x 8 BGA pinout diagrams from ‘GND’ to ‘Vssq’
	7/20/01	-011	Added ‘Vssq’ to Pin Descriptions Information
			Removed 0.4 µm references in DC characteristics table
			Corrected 64Mb package Ordering Information from 48-uBGA to 48-VFBGA
			Corrected ‘bottom’ parameter block sizes to on 8Mb device to 8 x 4KWords
			Minor text edits throughout document
	10/02/01	-012	Added specifications for 0.13 micron product offerings throughout document
			Corrected Iccw / Ippw / Icces /Ippes values.
	2/05/02	-013	Added mechanicals for 16Mb and 64Mb
			Minor text edits throughout document.

Datasheet

5

Contents

	Date of	Version	Description
	Revision
			Updated 64Mb product offerings.
			Updated 16Mb product offerings.
	4/05/02	-014	Revised and corrected DC Characteristics Table.
			Added mechanicals for Easy BGA.
			Minor text edits throughout document.
	3/06/03	-016	Complete technical update.
	10/03	-017	Corrected information in the Device Geometry Details table, address 0x34.

6

Datasheet

Intel£ Advanced+ Boot Block Flash Memory (C3)

1.0Introduction

1.1Document Purpose

This datasheet contains the specifications for the Intel® Advanced+ Boot Block Flash Memory (C3) device family. These flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems.

1.2Nomenclature

0x	Hexadecimal prefix
0b	Binary prefix
Byte	8 bits
Word	16 bits
Kword	1024 words
Mword	1,048,576 words
Kb	1024 bits
KB	1024 bytes
Mb	1,048,576 bits
MB	1,048,576 bytes
APS	Automatic Power Savings
CUI	Command User Interface
OTP	One Time Programmable
PR	Protection Register
PRD	Protection Register Data
PLR	Protection Lock Register
RFU	Reserved for Future Use
SR	Status Register
SRD	Status Register Data
WSM	Write State Machine

1.3Conventions

The terms pin and signal are often used interchangeably to refer to the external signal connections on the package. (ball is the term used for CSP).

Group Membership Brackets: Square brackets will be used to designate group membership or to define a group of signals with similar function (i.e. A[21:1], SR[4:1])

Set: When referring to registers, the term set means the bit is a logical 1.

Clear: When referring to registers, the term clear means the bit is a logical 0.

Block: A group of bits (or words) that erase simultaneously with one block erase instruction.

Main Block: A block that contains 32 Kwords.

Parameter Block: A block that contains 4 Kwords.

Datasheet

7

Intel£ Advanced+ Boot Block Flash Memory (C3)

2.0Device Description

This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device features, packaging, signal naming, and device architecture.

2.1Product Overview

The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks.

The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC and VPP can be tied together for a simple, ultra-low-power design. In addition to I/O voltage flexibility, the dedicated VPP input provides complete data protection when VPP ≤ VPPLK.

The device features a 128-bit protection register enabling security techniques and data protection schemes through a combination of factory-programmed and user-programmable OTP data registers. Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. Additional block lock-down capability provides hardware protection where software commands alone cannot change the block’s protection status.

A command User Interface(CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence issued to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.

The device offers three low-power saving features: Automatic Power Savings (APS), standby mode, and deep power-down mode. The device automatically enters APS mode following read cycle completion. Standby mode begins when the system deselects the flash memory by deasserting CE#. The deep power-down mode begins when RP# is asserted, which deselects the memory and places the outputs in a high-impedance state, producing ultra-low power savings. Combined, these three power-savings features significantly enhanced power consumption flexibility.

2.2Ballout Diagram

The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball BGA, and Easy BGA packages. (Refer to Figure 1 on page 9, Figure 3 on page 11, and Figure 4 on page 12, respectively.)

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Datasheet

Intel£ Advanced+ Boot Block Flash Memory (C3)

Figure 1. 48-Lead TSOP Package

		A15	1		48	A16
		A14	2		47	VCCQ
		A13	3		46	GND
		A12	4		45	DQ15
		A11	5		44	DQ7
		A10	6		43	DQ14
		A9	7		42	DQ6
	64 M	A8	8		41	DQ13
		A21	9		40	DQ5
	32 M	A20	10	Advanced+ Boot Block	39	DQ12
		WE#	11	48-Lead TSOP	38	DQ4
		RP#	12	12 mm x 20 mm	37	VCC
		VPP	13		36	DQ11
	16 M	WP#	14	TOP VIEW	35	DQ3
		A19	15		34	DQ10
		A18	16		33	DQ2
		A17	17		32	DQ9
		A7	18		31	DQ1
		A6	19		30	DQ8
		A5	20		29	DQ0
		A4	21		28	OE#
		A3	22		27	GND
		A2	23		26	CE#
		A1	24		25	A0
	NOTES:

1.For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on Pins 9 and 10.

Datasheet

9

Intel£ Advanced+ Boot Block Flash Memory (C3)

Figure 2. Mark for Pin-1 indicator on 48-Lead 8Mb, 16Mb and 32Mb TSOP

C urrent M ark:

N ew M ark:

Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel£ Advanced and Advanced + Boot Block 48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in package size, materials, functionality, customer handling, or manufacturability. Product will continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes shown in Table 1.

Table 1. 48-Lead TSOP

Extended 64 Mbit	Extended 32 Mbit	Extended 16 Mbit	Extended 8 Mbit
TE28F640C3TC80	TE28F320C3TD70	TE28F160C3TD70	TE28F800C3TA90
TE28F640C3BC80	TE28F320C3BD70	TE28F160C3BD70	TE28F800C3BA90
	TE28F320C3TC70	TE28F160C3TC80	TE28F800C3TA110
	TE28F320C3BC70	TE28F160C3BC80	TE28F800C3BA110
	TE28F320C3TC90	TE28F160C3TA90
	TE28F320C3BC90	TE28F160C3BA90
	TE28F320C3TA100	TE28F160C3TA110
	TE28F320C3BA100	TE28F160C3BA110
	TE28F320C3TA110
	TE28F320C3BA110

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Datasheet

Intel£ Advanced+ Boot Block Flash Memory (C3)

Figure 3. 48-Ball µBGA* and 48-Ball Very Fine Pitch BGA (VF BGA) Chip Size Package (Top View, Ball Down)1,2,3

	1	2	3	4	5	6	7	8
						16M
A	A13	A11	A8	VPP	WP#	A19	A7	A4
B	A14	A10	WE#	RP#	A18	A17	A5	A2
			64M		32M
C	A15	A12	A9	A21	A20	A6	A3	A1
D	A16	D14	D5	D11	D2	D8	CE#	A0
E	VCCQ	D15	D6	D12	D3	D9	D0	GND
F	GND	D7	D13	D4	VCC	D10	D1	OE#
	NOTES:

1.Shaded connections indicate the upgrade address connections. Routing is not recommended in this area.

2.A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.

3.Unused address balls are not populated.

Datasheet

11

Intel£ Advanced+ Boot Block Flash Memory (C3)

Figure 4. 64-Ball Easy BGA Package1,2

1			2	3	4	5	6	7	8
	A
		A1	A6	A18	VPP	VCC	GND A10		A15
	B
		A2	A17	A19(1)	RP#	DU	A20(1)	A11	A14
	C
		A3	A7	WP# WE# DU A21(1)				A12	A13
	D
		A4	A5	DU	DU	DU	DU	A8	A9
	E	DQ8	DQ1	DQ9	DQ3	DQ12	DQ6	DU	DU
	F
		CE# DQ0		DQ10	DQ11	DQ5	DQ14	DU	DU
	G
		A0	VSSQ	DQ2	DQ4	DQ13	DQ15	VSSQ	A16
	H
		A22(2) OE# VCCQ			VCC	VSSQ	DQ7	VCCQ	DU

8	7	6	5	4	3	2	1
A
A15	A10	GND VCC		VPP	A18	A6	A1
B
A14	A11	A20(1)	DU	RP# A19(1)		A17	A2
C
A13	A12	A21(1)	DU WE# WP# A7				A3
D
A9	A8	DU	DU	DU	DU	A5	A4
E
DU	DU	DQ6	DQ12	DQ3	DQ9	DQ1	DQ8
F
DU	DU DQ		DQ	DQ	DQ	DQ	CE#
		14	5	11	10	0
G	V	D15	D13	DQ4	DQ2	VSSQ	A0
A16
	SSQ
H
DU	VCCQ	D7	VSSQ	VCC	VCCQ	OE# A22(2)

Top ViewBall Side

Bottom View - Ball Side

NOTES:

1.A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.

2.Unused address balls are not populated.

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Datasheet

Intel£ Advanced+ Boot Block Flash Memory (C3)

2.3Signal Descriptions

Table 2 lists the active signals used and provides a brief description of each.

Table 2. Signal Descriptions

	Symbol	Type	Name and Function
			ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
			cycle.
	A[MAX:0]	INPUT	8 Mbit: AMAX= A18
			16 Mbit: AMAX = A19
			32 Mbit: AMAX = A20
			64 Mbit: AMAX = A21
		INPUT/	DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
	DQ[15:0]		cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
		OUTPUT	internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are
			disabled.
	CE#	INPUT	CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense
			amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption
			to standby levels.
	OE#	INPUT	OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a
			Read operation.
			RESET/DEEP POWER-DOWN: Active-low input.
	RP#	INPUT	When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to
			High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
			When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
			logic-high, the device resets all blocks to locked and defaults to the read array mode.
	WE#	INPUT	WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
			the rising edge of the WE# pulse.
			WRITE PROTECT: Active-low input.
			When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot
			be unlocked through software.
	WP#	INPUT	When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are
			now locked and can be unlocked and locked through software. After WP# goes low, any blocks
			previously marked lock-down revert to the lock-down state.
			See Section 5.0, “Security Modes” on page 27 for details on block locking.
			PROGRAM/ERASE POWER SUPPLY: Operates as an input at logic levels to control complete device
			protection. Supplies power for accelerated Program and Erase operations in 12 V ± 5% range. This pin
			cannot be left floating.
			Lower VPP ≤ VPPLK to protect all contents against Program and Erase commands.
	VPP	INPUT/	Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can
		POWER	drop as low as 1.65 V to allow for resistor or diode drop from the system supply.
			Apply VPP to 12 V ± 5% for faster program and erase in a production environment. Applying 12 V ± 5%
			to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the
			boot blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 5.6 for
			details on VPP voltage configurations.
	VCC	POWER	DEVICE CORE POWER SUPPLY: Supplies power for device operations.
	VCCQ	POWER	OUTPUT POWER SUPPLY: Output-driven source voltage. This ball can be tied directly to VCC if
			operating within VCC range.
	GND	POWER	GROUND: For all internal circuitry. All ground inputs must be connected.
	DU	-	DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or
			other balls, and must be left floating.
	NC	-	NO CONNECT: Pin must be left floating.

Datasheet

13

Intel£ Advanced+ Boot Block Flash Memory (C3)

2.4Block Diagram

					DQ 0-DQ15
	VCCQ
			Output Buffer				Input Buffer
				M ulti ple xer	Identifier
			Outp ut		Register		Re gi ster
					Status	Da ta		I/O Logic
					Register
							Command		CE#
		Power							WE#
							User
					Data				OE#
		Reduction					Interface
		Control			Comparator				RP#
									WP#
A[MAX:MIN]	Input Buffer	Y-Decoder		Y-Gating/Sensing			Write State	Program/Erase	VPP
			k	k			Machine	Voltage Switch
	Address		Para mete r B loc	4 -KWor d Para mete r B loc	32KWord M ain Blo ck	32KWord M ain Blo ck
	Latch	X-Decoder							VCC
	Address	KW4ord-							GND
	Counter

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Datasheet

Intel£ Advanced+ Boot Block Flash Memory (C3)

2.5Memory Map

The C3 device is asymmetrically blocked, which enables system code and data integration within a single flash device. The bulk of the array is divided into 32 Kword main blocks that can store code or data, and 4 Kword boot blocks to facilitate storage of boot code or for frequently changing small parameters. See Table 3, “Top Boot Memory Map” on page 15 and Table 4, “Bottom Boot Memory Map” on page 16 for details.

Table 3. Top Boot Memory Map

			8-Mbit
	Size	Blk	Memory
	(KW)		Addressing
			(HEX)
	4	22	7F000-
			7FFFF
	4	21	7E000-
			7EFFF
	4	20	7D000-
			7DFFF
	4	19	7C000-
			7CFFF
	4	18	7B000-
			7BFFF
	4	17	7A000-
			7AFFF
	4	16	79000-79FFF
	4	15	78000-78FFF
	32	14	70000-77FFF
	32	13	68000-6FFFF
	32	12	60000-67FFF
	32	11	58000-5FFFF
	...	...	...
	32	2	10000-17FFF
	32	1	8000-0FFFF
	32	0	0000-07FFF

			16-Mbit
	Size	Blk	Memory
	(KW)		Addressing
			(HEX)
	4	38	FF000-FFFFF
	4	37	FE000-FEFFF
	4	36	FD000-FDFFF
	4	35	FC000-FCFFF
	4	34	FB000-FBFFF
	4	33	FA000-FAFFF
	4	32	F9000-F9FFF
	4	31	F8000-F8FFF
	32	30	F0000-F7FFF
	32	29	E8000-EFFFF
	32	28	E0000-E7FFF
	32	27	D8000-DFFFF
	...	...	...
	32	2	10000-17FFF
	32	1	08000-0FFFF
	32	0	00000-07FFF

			32-Mbit
	Size	Blk	Memory
	(KW)		Addressing
			(HEX)
	4	70	1FF000-
			1FFFFF
	4	69	1FE000-
			1FEFFF
	4	68	1FD000-
			1FDFFF
	4	67	1FC000-
			1FCFFF
	4	66	1FB000-
			1FBFFF
	4	65	1FA000-
			1FAFFF
	4	64	1F9000-
			1F9FFF
	4	63	1F8000-
			1F8FFF
	32	62	1F0000-
			1F7FFF
	32	61	1E8000-
			1EFFFF
	32	60	1E0000-
			1E7FFF
	32	59	1D8000-
			1DFFFF
	...	...	...
	32	2	10000-17FFF
	32	1	08000-0FFFF
	32	0	00000-07FFF

	Size		64-Mbit Memory
		Blk	Addressing
	(KW)
			(HEX)
	4	134	3FF000-3FFFFF
	4	133	3FE000-3FEFFF
	4	132	3FD000-3FDFFF
	4	131	3FC000-3FCFFF
	4	130	3FB000-3FBFFF
	4	129	3FA000-3FAFFF
	4	128	3F9000-3F9FFF
	4	127	3F8000-3F8FFF
	32	126	3F0000-3F7FFF
	32	125	3E8000-3EFFFF
	32	124	3E0000-3E7FFF
	32	123	3D8000-3DFFFF
	...	...	...
	32	2	10000-17FFF
	32	1	08000-0FFFF
	32	0	00000-07FFF

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Intel£ Advanced+ Boot Block Flash Memory (C3)

Table 4. Bottom Boot Memory Map

		8-Mbit				16-Mbit				32-Mbit				64-Mbit Memory
Size		Memory		Size		Memory		Size		Memory		Size
	Blk				Blk				Blk				Blk	Addressing
(KW)		Addressing		(KW)		Addressing		(KW)		Addressing		(KW)
														(HEX)
		(HEX)				(HEX)				(HEX)
32	22	78000-7FFFF		32	38	F8000-FFFFF		32	70	1F8000-1FFFFF		32	134	3F8000-3FFFFF
32	21	70000-77FFF		32	37	F0000-F7FFF		32	69	1F0000-1F7FFF		32	133	3F0000-3F7FFF
32	20	68000-6FFFF		32	36	E8000-EFFFF		32	68	1E8000-1EFFFF		32	132	3E8000-3EFFFF
32	19	60000-67FFF		32	35	E0000-E7FFF		32	67	1E0000-1E7FFF		32	131	3E0000-3E7FFF
...	...	...		...	...	...		...	...	...		.	...	...
32	10	18000-1FFFF		32	10	18000-1FFFF		32	10	18000-1FFFF		32	10	18000-1FFFF
32	9	10000-17FFF		32	9	10000-17FFF		32	9	10000-17FFF		32	9	10000-17FFF
32	8	08000-0FFFF		32	8	08000-0FFFF		32	8	08000-0FFFF		32	8	08000-0FFFF
4	7	07000-07FFF		4	7	07000-07FFF		4	7	07000-07FFF		4	7	07000-07FFF
4	6	06000-06FFF		4	6	06000-06FFF		4	6	06000-06FFF		4	6	06000-06FFF
4	5	05000-05FFF		4	5	05000-05FFF		4	5	05000-05FFF		4	5	05000-05FFF
4	4	04000-04FFF		4	4	04000-04FFF		4	4	04000-04FFF		4	4	04000-04FFF
4	3	03000-03FFF		4	3	03000-03FFF		4	3	03000-03FFF		4	3	03000-03FFF
4	2	02000-02FFF		4	2	02000-02FFF		4	2	02000-02FFF		4	2	02000-02FFF
4	1	01000-01FFF		4	1	01000-01FFF		4	1	01000-01FFF		4	1	01000-01FFF
4	0	00000-00FFF		4	0	00000-00FFF		4	0	00000-00FFF		4	0	00000-00FFF

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Datasheet

Intel£ Advanced+ Boot Block Flash Memory (C3)

3.0Device Operations

The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and programming.

The internal WSM completely automates Program and Erase operations while the CUI signals the start of an operation and the status register reports device status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.

3.1Bus Operations

The C3 device performs read, program, and erase operations in-system via the local CPU or microcontroller. Four control pins (CE#, OE#, WE#, and RP#) manage the data flow in and out of the flash device. Table 5 on page 17 summarizes these bus operations.

Table 5. Bus Operations

Mode	RP#	CE#	OE#	WE#	DQ[15:0]
Read	VIH	VIL	VIL	VIH	DOUT
Write	VIH	VIL	VIH	VIL	DIN
Output Disable	VIH	VIL	VIH	VIH	High-Z
Standby	VIH	VIH	X	X	High-Z
Reset	VIL	X	X	X	High-Z

NOTE: X = Don’t Care (VIL or VIH)

3.1.1Read

When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted. CE# is the device selection control; when active low, it enables the flash memory device. OE# is the data output control; when low, data is output on DQ[15:0]. See Figure 8, “Read Operation Waveform” on page 42.

3.1.2Write

A write cycle occurs when both CE# and WE# are low; RP# and OE# are high. Commands are issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever occurs first. See Figure 9, “Write Operations Waveform” on page 47.

3.1.3Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. DQ[15:0] are placed in a high-impedance state.

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Intel£ Advanced+ Boot Block Flash Memory (C3)

3.1.4Standby

Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during a Program or Erase operation, the device continues to consume active power until the Program or Erase operation is complete.

3.1.5Reset

From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high- impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required

until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored.

The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See Figure 10, “Reset Operations Waveforms” on page 48.

If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are

no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence:

1.When RP# goes low, the device shuts down the operation in progress, a process which takes time tPLRH to complete.

2.After time tPLRH, the part will either reset to read-array mode (if RP# is asserted during tPLRH) or enter reset mode (if RP# is deasserted after tPLRH). See Figure 10, “Reset Operations Waveforms”

on page 48.

In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL must be observed before a Read or Write operation is initiated, as discussed in the previous

paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high.

As with any automated device, it is important to assert RP# during a system reset. When the system comes out of reset, the processor expects to read from the flash memory. Automated flash memories provide status information when read during program or Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel® Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

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Intel£ Advanced+ Boot Block Flash Memory (C3)

4.0Modes of Operation

4.1Read Mode

The flash memory has four read modes (read array, read identifier, read status, and CFI query), and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. Table 7, “Command Bus Operations” on page 24 and Table 8, “Command Codes and Descriptions” on page 25 summarize the commands used to reach these modes. Appendix A, “Write State Machine States” on page 50 is a comprehensive chart showing the state transitions.

4.1.1Read Array

When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI commands.

When the device is in read array mode, four control signals control data output.

•WE# must be logic high (VIH)

•CE# must be logic low (VIL)

•OE# must be logic low (VIL)

•RP# must be logic high (VIH)

In addition, the address of the desired location must be applied to the address pins. If the device is not in read-array mode, as would be the case after a Program or Erase operation, the Read Array command (0xFF) must be issued to the CUI before array reads can occur.

4.1.2Read Identifier

The read-identifier mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 6 retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF).

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Intel£ Advanced+ Boot Block Flash Memory (C3)

Table 6. Device Identification Codes

			Address1
	Item					Data	Description
			Base	Offset
	Manufacturer ID		Block	0x00		0x0089
						0x88C0	8-Mbit Top Boot Device
						0x88C1	8-Mbit Bottom Boot Device
						0x88C2	16-Mbit Top Boot Device
	Device ID		Block	0x01		0x88C3	16-Mbit Bottom Boot Device
						0x88C4	32-Mbit Top Boot Device
						0x88C5	32-Mbit Bottom Boot Device
						0x88CC	64-Mbit Top Boot Device
						0x88CD	64-Mbit Bottom Boot Device
	Block Lock Status2		Block	0x02		DQ0 = 0b0	Block is unlocked
						DQ0 = 0b1	Block is locked
	Block Lock-Down Status2		Block	0x02		DQ1 = 0b0	Block is not locked-down
						DQ1 = 0b1	Block is locked down
	Protection Register Lock Status		Block	0x80		Lock Data
				0x81 -			Multiple reads required to read
	Protection Register		Block			Register Data	the entire 128-bit Protection
				0x88
							Register.

NOTES:

1.The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number 38 in a bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i.e. 0x0F8002. Then examine DQ0 of the data to determine if the block is locked.

2.See Section 5.2, “Reading Block-Lock Status” on page 28 for valid lock status.

4.1.3CFI Query

The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read Query Command (0x98). The CFI data structure contains information such as block size, density, command set, and electrical specifications. Once in this mode, read cycles from addresses shown in Appendix C, “Common Flash Interface,” retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF).

4.1.4Read Status Register

The status register indicates the status of device operations, and the success/failure of that operation. The Read Status Register (0x70) command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the array, issue a Read Array (0xFF) command.

The status-register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 0x00 when a Read Status Register command is issued.

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Intel£ Advanced+ Boot Block Flash Memory (C3)

The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs last) which prevents possible bus errors that might occur if Status Register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register will not indicate completion of a Program or Erase operation.

When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 9, “Status Register Bit Definition” on page 26).

4.1.4.1Clear Status Register

The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7; but, the WSM cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. The Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the Status Register.

4.2Program Mode

Programming is executed using a two-write cycle sequence. The Program Setup command (0x40) is issued to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program preferred bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a “0.” If users attempt to program “1”s, the memory cell contents do not change and no error occurs.

The Status Register indicates programming status. While the program sequence executes, status bit 7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the program-status bits should be checked. If the programming operation was unsuccessful, bit SR[4] of the Status Register is set to indicate a program failure. If SR[3] is set, then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR[1] is set, a program operation was attempted on a locked block and the operation was aborted.

The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status-register reads, be sure to reset the CUI to read-array mode.

4.2.112-Volt Production Programming

When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC pin. Note that if VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above 1.65 V to perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device draws program and erase current directly from the VPP pin. This eliminates the need for an external switching transistor to control VPP. Figure 7 on page 31 shows examples of how the flash power supplies can be configured for various usage models.

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