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3 Volt Advanced Boot Block Flash Memory

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Product Features

Preliminary Datasheet

■ Flexible Smar tVoltage Technology

—2.7 V–3.6 V Read/Program/Erase —12 V V

■ 2.7 V or 1.65 V I/O Option

Fast Production Programming

—Reduces Overall System Power

■ High Performance

—2.7 V–3.6 V: 70 ns Max Access Time

■ Optimized Block Sizes

—Eight 8-KB Blocks for Data,Top or

Bottom Locations

—Up to One Hundred Twenty-Seven 64-

KB Blocks for Code

■ Block Locking

—V

-Level Control through WP#

■ Low Power Consumption

—9 mA Typical Read Current

■ Absolute Hardware-Protection

—V

= GND Option

—V

Lockout Voltage

■ Extended Temperature Operation

—–40 °C to +85 °C

■ Automated Program and Block Erase

—Status Reg isters

■ Intel

Flash Data Integrator Software

—Flash Memory Manager —System Interrupt Manager —Supports Parameter Storage, Streaming

Data (e.g., Voice)

■ Extended Cycling Capabilit y

—Minimum 100,000 Block Erase Cycles

Guaranteed

■ Automatic Power Savings Feature

—Typical I

■ Standard Surface Mount Packaging

after Bus Inactivity

CCS

—48-Ball CSP Packages —40- and 48-Lead TSOP Packages

■ Density and Footprint Upgradeable for

common package

—4-, 8-, 16-, 32- and 64-Mbit Densities

■ ETOX™ VII (0.18 µ) Flash Technology

—28F160/320/640B3xC —4-, 8-, 16-, and 32-Mbit also exist on

ETOX™ V (0.4µ) and/or ETOX ™ VI (0.25µ) Flash Technology

■ x8 not recommended for new designs

■ 4-Mbit density not recommended for new

designs

The 3 Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.18 µm technology, represents a feature-rich solution at overall lower system cost. The 3Volt Advanced Boot Block flash memory products in x16 will be available in 48-lead TSOP and 48-ball CSP packages. The x8 option of this product family will o nly be available in 40-lead TSOP and 48ball µBGA* packages. Additional information on this product family can be obtained by accessing Intel’s website at: http://www.intel.com/design/flash.

Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number: 290580-012

October 2000

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause

the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

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Contents

1.0 Introduction..................................................................................................................1

1.1 Product Overview..................................................................................................2

2.0 Product Description..................................................................................................3

2.1 Package Pinouts ...................................................................................................3

2.2 Block Organization ................................................................................................7

2.2.1 Parameter Blocks.....................................................................................7

2.2.2 Main Blocks..............................................................................................7

3.0 Principles of Operation............................................................................................7

3.1 Bus Operation .......................................................................................................7

3.1.1 Read.........................................................................................................8

3.1.2 Output Disable..........................................................................................8

3.1.3 Standby ....................................................................................................8

3.1.4 Deep Power-Down / Reset.......................................................................8

3.1.5 Write.........................................................................................................9

3.2 Modes of Operation...............................................................................................9

3.2.1 Read Array ...............................................................................................9

3.2.2 Read Identifier........................................................................................11

3.2.3 Read Status Register .............................................................................11

3.2.4 Program Mode....... ...... ....... ...... ...... ....... ...... ....................................... ....12

3.2.5 Erase Mode............................................................................................12

3.3 Block Locking ......................................................................................................14

3.3.1 WP# = V

3.3.2 WP# = V

3.4 V

3.5 Power Consumption............................................................................................15

3.6 Power-Up/Down Operation ............. ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... ....16

3.7 Power Supply Decoupling ...................................................................................17

Program and Erase Voltages.......................................................................15

3.4.1 V

3.5.1 Active Power ..........................................................................................16

3.5.2 Automatic Power Savings (APS)............................................................16

3.5.3 Standby Power.......................................................................................16

3.5.4 Deep Power-Down Mode .......................................................................16

3.6.1 RP# Connected to System Reset...........................................................17

3.6.2 V

for Block Locking ..................................................................14

for Block Unlocking ..............................................................15

= VIL for Complete Protection .........................................................15

, VPP and RP# Transitions...............................................................17

4.0 Electrical Specifications........................................................................................18

4.1 Absolute Maximum Ratings.................................................................................18

4.2 Operating Conditions...........................................................................................19

4.3 Capacitance ........................................................................................................19

4.4 DC Characteristics ................... ....... ...................................... ....... ...... ....... ...... ....20

4.5 AC Characteristics —Read Operations...............................................................23

4.6 AC Characteristics —Write Operations...............................................................27

4.7 Program and Erase Timings................................................................................31

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5.0 Reset Operations .....................................................................................................33

6.0 Ordering Information..............................................................................................34

7.0 Additional Information............. ...................................... ....................................... .36

Appendix A Write State Machine Current/Next States.................................................37

Appendix B Architecture Block Diagram... ........................................................................38

Appendix C Word-Wide Memory Map Diagrams.............................................................39

Appendix D Byte-Wide Memory Map Diagrams................................... ...........................45

Appendix E Program and Erase Flowcharts....................................................................48

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Revision History

Number Description

-001 Original version

VPP Program and Erase Voltages

maximum specification change from ±25 µA to ±50 µA

Ordering Information Additional Information

Program Flowchart

Program Suspend/Resume Flowchart

= 0 when in read identifier mode (Section 3.2.2)

absolute maximum specification = 3.7 V (Section 4.1)

CCQ

PPW PPE

test conditions corrected (Section 4.4)

and VILSpecification change (Section 4.4) test conditions clarification (Section 4.4)

-002

-003

-004

-005

-006

-007

Section 3.4, Updated Figure 9: Updated Figure 10: Updated Figure 16: I

PPR

Program and Erase Suspend Latency specification change Updated Appendix A: Updated Figure, Appendix D: Minor wording changes

Combined byte-wide specification (previously 290605) with this document Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V) Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4) Improved several DC characteristics (Section 4.4) Improved several AC characteristics (Sections 4.5 and 4.6) Combined 2.7 V and 1.8 V DC characteristics (Section 4.4) Added 5 V V Removed 120 ns and 150 ns speed offerings Moved Moved Updated figure Appendix B, Updated figure Appendix C, Moved Program and Erase Flowcharts to Appendix E Updated Updated Minor text edits throughout

Added 32-Mbit density Added 98H as a reserved command (Table 4) A

1–A20

Status register clarification for SR3 (Table 7)

and V

Combined I Combined I Max Parameter Block Erase Time (t Max Main Block Erase Time (t Erase suspend time @ 12 V (t (Section 4.7)

Ordering Information

Write State Machine Current/Next States Table updated (Appendix A) Program Suspend/Resume Flowchart updated (Appendix F) Erase Suspend/Resume Flowchart updated (Appendix F) Text clarifications throughout

µBGA package diagrams corrected (Figures 3 and 4) I

PPD

32-Mbit ordering information corrected (Section 6) µBGA package top side mark information added (Section 6)

CCS

Added Command Sequence Error Note (Table 7) Datasheet renamed from

Memory Family.

Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes

Corrected RP# pin description in Table 2, Corrected typographical error fixed in

Automated Block Erase Flowchart

, added

Erase Suspend/Resume Flowchart AC Waveform: Program and Erase Operations

Ordering Information

(included 8 M and 4 M information)

Architecture Block Diagram

read specification (Section 3.4)

from Appendix to Section 6.0; updated information

from Appendix to Section 7.0

Access Time vs. Capacitive Load

Architecture Block Diagram

and I

into one specification (Section 4.4)

CCW

into one specification (Section 4.4)

CCE

updated (Section 6.0)

WHQV2/tEHQV2 WHQV3/tEHQV3 WHRH2/tEHRH2

) reduced to 5 sec (Section 4.7) ) changed to 5 µs typical and 20 µs maximum

) reduced to 4 sec (Section 4.7)

Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash

3 Volt Advanced Boot Block Pin Descriptions

Ordering Information

(added program to table)

(updated notes)

(Block info. in words not bytes)

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Number Description

-008 4-Mbit packaging and addressing information corrected throughout document

-009 Corrected 4-Mbit memory addressing tables in Appendices D and E

-010

-011

-012

Max I

V Added 64-Mbit density and faster speed offerings

Removed access time vs. capacitance load curve Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product

offering. Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit device. Minor text edits throughout document.

changed to 25 µA

CCD

Max on 32 M (28F320B3) changed to 3.3 V

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1.0 Introduction

This datasheet contains the specifications for the 3 Volt Advanced Boot Block flash memory family, which is optimized for low power, portable systems. This family of products features

1.65 V–2.5 V or 2.7 V–3.6 V I/Os and a low V program, and erase operations. In addition this family is capable of fast programming at 12 V. Throughout this document, the term “2.7 V” refers to the full voltage range 2.7 V–3.6 V (except where noted otherwise) and “V overview of the flash memory family including applications, pinouts and pin descriptions. Section

3.0 describes the memory organization and operation for these products. Sections 4.0 and 5.0 contain the operating specifications. Finally, Sections 6.0 and 7.0 provide ordering and other reference information.

The 3 Volt Advanced Boot Block flash memory features:

• Enhanced blocking for easy segmentation of code and data or additional design flexibility

• Program Suspend to Read command

operating range of 2.7 V–3.6 V for read,

CC/VPP

= 12 V” refers to 12 V ±5%. Section 1.0 and 2.0 provide an

• V

input of 1.65 V–2.5 V on all I/Os. See Figures 1 through 4 for pinout diagrams and

CCQ

location

CCQ

• Maximum program and erase time specification for improved data storage.

Table 1. 3 Volt Advanced Boot Block Feature Summary

(2)

Feature

Read Voltage 2.7 V– 3.6 V

I/O Voltage 1.65 V–2.5 V or 2.7 V– 3.6 V Section 4.2, 4.4

CCQ

Program/Erase Voltage 2.7 V– 3.6 V or 11.4 V– 12.6 V Section 4.2, 4.4

Bus Width 8 bit 16 bit Table 3 Speed 70 ns, 80 ns, 90 ns, 100 ns, 110 ns Section 4.5

Memory Arrangement

Blocking (top or bottom)

Locking Operating Tempe rature Extended: –40 °C to +85 °C Section 4.2, 4.4

Program/Erase Cycling 100,000 cycles Section 4.2, 4.4

Packages

NOTES:

1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP.

2. 4-Mbit density not available in µBGA* CSP. Max is 3.3 V on 0.25µm 32-Mbit devices.

3. V

4. 4- and 64-Mbit densities not available on 48-Ball VF BGA.

28F004B3

512 Kbit x 8 (4 Mbit)

1024 Kbit x 8 (8 Mbit),

2048 Kbit x 8 (16 Mbit)

One hundred twenty-seven 64-Kbyte main blocks (64 Mbit)

40-lead TSOP

48-Ball µBGA* CSP

, 28F008B3,

28F016B3

Eight 8-Kbyte parameter blocks and

Seven 64-Kbyte blocks (4 Mbit) or

Fifteen 64-Kbyte blocks (8 Mbit) or

Thirty-one 64-Kbyte main blocks (16 Mbit)

Sixty-three 64-Kbyte main blocks (32 Mbit)

WP# locks/unlocks parameter blocks

All other blocks protected using V

(1)

(2)

28F400B3 28F160B3, 28F320B3

256 Kbit x 16 (4 Mbit),

512 Kbit x 16 (8 Mbit), 1024 Kbit x 16 (16 Mbit), 2048 Kbit x 16 (32 Mbit),

4096 Kbit x 16 (64 Mbit)

48-Ball µBGA CSP

48-Ball VF BGA

, 28F800B3,

28F640B3

48-Lead TSOP,

(3)

(2)

(4)

Reference

Section 4.2, Section 4.4

Section 2.2

Section 2.2 Appendix C

Section 3.3 Table 8

Figure 3, Figure 4

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1.1 Product Overview

Intel provides the most flexible voltage soluti on in the flash industry, providing three discrete voltage supply pins: V erase operation. All 3 Volt Advanced Boot Block flash memory products provide program/erase capability at 2.7 V or 12 V (for fast production programming) and read with V many designs read from the flash memory a larg e percentage of the time, 2.7V V provide substantial power savings.

The 3 Volt Advanced Boot Block flash memory products ar e available in either x8 or x16 packages in the following densities: (see Section 6.0, “Ordering Information” on page 34 for availability.)

• 4-Mbit (4,194,304-bit) flash memory organized as 256 Kwords of 16 bits each or 512 Kbytes

of 8-bits each

• 8-Mbit (8,388,608-bit) flash memory organized as 512 Kwo rds of 16 b its each or 1 024 Kbytes

of 8-bits each

• 16-Mbit (16,777,216-bit) flash memory organized as 1024 Kwords of 16 bits each or

2048 Kbytes of 8-bits each

• 32-Mbit (33,554,432-bit) flash memory organized as 2048 Kwords of 16 bits each

for read o peration, V

for output swing, and VPP for program and

CCQ

at 2.7 V. Since

operation can

• 64-Mbit (67,108,864-bit) flash memory organized as 4096 Kwords of 16 bits each

The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section

3.3, “Block Locking” on page 14 for detai ls).

The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby un-burdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status.

The 3 Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered following the completion of a read cycle (approximately 300 ns later).

The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see

Section 3.6, “Power-Up/Down Operation” on page 16). Section 3.0, “Principles of Operation” on page 7 gives detailed explanation of the different modes

of operation. Complete current and voltage specifications can be found in Section 4.4, “DC

Characteristics” on page 20. Refer to Section 4.5, “AC Characteristics —Read Operations” on page 23 for read, program and erase performance specifications.

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2.0 Product Description

This section explains device pin description and package pinouts.

2.1 Package Pinouts

The 3 Volt Advanced Boot Block flash memory is available in 40-lead TSOP (x8, Figure 1), 48-lead TSOP (x16, Fig u r e 2 ) and 48- bal l µBGA(x8 and x16, Figure 3 and Figure 4, respectively) and 48-ball VF BGA (x16, Figure 4) packages. In all figures, pin changes necessary for density upgrades have been circled.

Figure 1. 40-Lead TSOP Package for x8 Configurations

GND A

DQ DQ DQ DQ V

CCQ

NC DQ DQ DQ DQ OE# GND CE# A

16 M

8 M

7 6 5 4

3 2 1 0

4 M

WE# RP# V

WP# A

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

Advanced Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

NOTES:

1. 40-Lead TSOP available for 8- and 16-Mbit densities only.

2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.

0580_01

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Figure 2. 48-Lead TSOP Package for x16 Configurations

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Advanced Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

64 M 32 M

16 M

WE# RP# V

WP# A

NOTE: Lower densities will have NC on the upper address pins. For example, an 16-Mbit device will have NC

on Pins 9 and 10.

Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)

13254768

16M

WP#

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

CCQ

GND DQ DQ DQ DQ DQ DQ DQ DQ V

DQ DQ DQ DQ DQ DQ DQ DQ OE# GND CE# A

15 7 14 6 13 5 12 4

11 3 10 2 9 1 8 0

0580_02

NOTES:

CCQ

GND D

WE#

NC D

RP#

CE#

NC D

GND

OE#

0580_04

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A 16-Mbit device.

is the upgrade address for the

2. 4-Mbit density not available in µBGA* CSP.

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Figure 4. x16 48-Ball Very Thin Profile Pitch BGA and µBGA* Chip Size Package (Top View,

Ball Down)

13254768

16M

WP#

NOTES:

CCQ

GND D

WE#

64M

RP#

32M

CE#

GND

OE#

0580_03

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A 16-Mbit device. A device.

is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit

is the upgrade address for the

2. 4-Mbit density not available in µBGA CSP.

T able 2, “3 Volt Advanced Boot Block Pin Description s” on page 6 details the usage of each device

pin.

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Table 2. 3 Volt Advanced Boot Block Pin Descriptions

Symbol Type Name and Function

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or

erase cycle. 28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20], 28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19], 28F320B3: A[0-20], 28F640B3: A[0-21]

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, i dentifier and status register data. The dat a pins float to tri-state when the chip is de-selected or the outputs are disabled.

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state when the chip is de-selected. Not included on x8 products.

CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels.

OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation. OE# is active low.

WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse.

RESET/DEEP POWER-DOWN: Uses two voltage levels (V mode.

, VIH) to control reset/deep power-down

When RP# is at logic low, the device is in reset/deep power-down mode , which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (I

When RP# is at logic high, the device is in standard operation. When RP# transitions from logiclow to logic-high, the device defaults to the read array mode.

WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks. When WP# is at logic low, the lockable blocks are locked, preventing program and erase

operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. See Section 3.3 for details on write protection.

OUTPUT V

is regulated to 2.7 V–2.85 V, V

operation (see Section 4.4 This input may be tied directly to V

: Enables all outputs to be driven to 1.8 V – 2.5 V while the VCC is at 2.7 V–3.3 V. If the

)

can be driven at 1.65 V–2.5 V to achieve lowest power

CCQ

(2.7 V–3.6 V).

DEVICE POWER SUPPLY: 2.7 V–3.6 V PROGRAM/ERASE POWER SUPPLY: Supplies power for program and erase operations. VPP may

be the same as V manufacturing, 11.4V–12.6 V may be supplied to V

11.4 V–12.6 V to V cycles on the parameter blocks.

Section 3.4 for details).

< V

PPLK

commands.

(2.7 V–3.6 V) for single supply voltage operation. For fast programming at

can only be done for a maximum of 1000 cycles on the main blocks and 2500

may be connected to 12 V for a total of 80 hours maximum (see

VPP

. This pin cannot be left floating. Applying

protects memory contents against inadvertent or unintended program and erase

INPUT

INPUT/

OUTPUT

INPUT/

OUTPUT

0–A21

DQ DQ

–DQ

–

8 15

CE# INPUT

OE# INPUT

WE# INPUT

RP# INPUT

WP# INPUT

CCQ

INPUT

GND GROUND: For all internal circuitry. All ground inputs must be connected. NC NO CONNECT: Pin may be driven or left floating.

CCD

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2.2 Block Organization

The 3 Volt Advanced Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 100,000 times. For the add ress locatio ns of each block , see the m emory maps in

Appendix C.

2.2.1 Parameter Blocks

The 3 Volt Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM). By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each device contains eight parameter blocks of 8-Kbytes/4-Kwords (8192 bytes/4,096 words) each.

2.2.2 Main Blocks

After the parameter blocks, the remainder of the array is divided into equal size main blocks (65,536 bytes/32,768 words) for data or code storage. The 4-Mbit device contains seven main blocks; 8-Mbit device contains fifteen main blocks; 16-Mbit flash has thirty-one main blocks; 32-Mbit has sixty-three main blocks; 64-Mbit has one hundred twenty-seven main blocks.

3.0 Principles of Operation

Flash memory combines EEPROM functionality with in-circuit electrical program and erase capability. The 3 Volt Advan ced Boot Block flash memory family utilizes a Command User Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power su ppl ie s duri ng erasu re and programming.

When V Array, Read Status Register, Clear Status Register and Read Identifier. The device provides standard EEPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI. All functions associated with altering memory contents, namely program and erase, are accessible via the CUI. The internal Write State Machine (WSM) completely automates program and erase operations while the CUI signals the start of an operation and the status register reports status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.

3.1 Bus Operation

3 Volt Advanced Boot Block flash memory devices read, program and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3.

< V

, the device will only execute the following commands successfully: Read

PPLK

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Table 3. Bus Operations

Mode Note RP# CE# OE# WE# DQ

Read (Array, Status, or Identifier) 2–4 V Output Disable 2 V Standby 2 V Reset 2, 7 V Write 2, 5–7 V

NOTES:

1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].

2. X must be V

DC Characteristics

3. See

4. Manufacturer and device codes may also be accessed in read identifier mode (A

5. Refe r to Table 6 for valid D

6. To program or erase the lockable blocks, hold WP# at V

7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

(1)

, VIH for control pins and addresses.

for V

PPLK

during a write operation.

3.1.1 Read

The flash memory has four read modes available: read array, read identifier, read status and read query. These modes are accessible independent of the V command must be issued to the CUI to enter the co rres ponding mode. Upon initial device powerup or after exit from reset, the device automatically defaults to read array mode.

CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output control and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at V

. Figure 7 illustrates a read cycle.

, V

IH IH IH

PP1

, V

0–7

X X X High Z High Z

, V

PP3

, V

PP2

X X High Z High Z

voltages.

PP4

voltage. The appropriate Read Mode

OUT

High Z High Z

= 0). See Table 5.

1–A21

OUT

8–15

3.1.2 Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a high-impedance state.

3.1.3 Standby

Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete.

3.1.4 Deep Power-Down / Reset

From read mode, RP# at VIL for time t impedance state, and turns off all internal circuits. After r eturn from reset, a time t until the initial read access outputs are valid. A delay (t reset before a write can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. This case is shown in

Figure 9A.

8 3UHOLPLQDU\

deselects the memory, places output drivers in a high-

PLPH

PHQV

PHWL

or t

) is required after return from

PHEL

is required

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

If RP# is taken low for time t aborted and the memory contents at th e abo rted location (for a program) or block (for an erase) ar e no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: When RP# goes low, the device shuts down the operation in progress, a process which takes time t array mode (if RP# h as go ne hi gh dur ing t low after t time t discussed in the previous paragraph. However, in this case, these delays are referenced to the end of t

PLRH

As with any automated device, it is important to assert RP # during system reset. When the system comes out of reset, processor expects to read from the flash memory. Automated flash memories provide status information when read during program or block erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel proper CPU initialization following a sy stem reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.1.5 Write

A write takes place when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control flash operations. The CUI does not occupy an addr essable m emor y loca tio n. The ad dress and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 8 illustrates a program and erase operation. The available commands are shown in Table 6, and

Appendix A provides detailed information on moving between the different modes of op eration

using CUI commands.

during a program or erase operation, the operation will be

PLPH

to complete. After this time t

PLRH

, Figure 9C). In both cases, after returning from an aborted operation, the relevant

PLRH

PHQV

or t

PHWL/tPHEL

must be waited before a read or write operation is initiated, as

rather than when RP# goes high.

, the part will either reset to read

, Figure 9B) or enter reset mode (if RP# is still logic

PLRH

Flash memories allow

There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to V

3.2 Modes of Operation

The flash memory has four read modes and two write modes. The read modes are read array, read identifier, read status and read query (see Appendix B). The write modes are program and block erase. Three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are reached using the commands summarized in Table 4. A comprehensive chart showing the state transitions is in

Appendix A.

3.2.1 Rea d A rray

When RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI commands.

for t

or an appropriate suspend command).

PLRH

3UHOLPLQDU\ 9

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

When the device is in read array mode, four control signals control data output:

• WE# must be logic high (V

• CE# must be logic low (V

• OE# must be logic low (V

• RP# must be logic high (V

)

In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place.

Table 4. Command Codes and Descriptions

Code Device Mode Description

00, 01, 60, 2F, C0, 98

FF Read Array Places the device in read array mode, such that array data will be output on the data pins.

40 Program Set-Up

20 Erase Set-Up

90 Read Identifier

Invalid/

Reserved

Alternate

Program Set-Up

Erase Confirm

Program / Erase

Resume

Program / Erase

Suspend

Read Status

Clear Status

Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions.

This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.2.4.

(See 40H/Program Set-Up) Prepares the CUI for the Erase Confirm command. If the next command is not an Erase

Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,” (b) place the device into the read status register mode, and (c) wait for another command. See

Section 3.2.5.

If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches, and begin erasing the block indicated on the address pins. During erase, the device will only respond to the Read Status Register and Erase Suspend comm ands. The device will output status register data when CE# or OE# is toggled.

If a program or erase operation was previously suspended, this command will resume that operation

Issuing this command will begin to suspend the currently executing program/erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit (SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if it is driven to V

This command places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a program or erase operation has been initiated. See Section 3.2.3.

The WSM can set the block lock status (SR.1) , V erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this command clears those bits to “0.”

Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (A address inputs must be 0). See Section Section 3.2.2.

. See Section 3.2.4.1 and Section 3.2.4.1.

status (SR.3), program status (SR.4), and

= 0 for manufacturer, A0 = 1 for device, all other

NOTE: See Appendix A for mode transition information.

10 3UHOLPLQDU\

3.2.2 Rea d Ident if ier

To read the manufacturer and device codes, the device must be in read identifier mode, which can be reached by writing the Read Identifier command (90H). Once in read identifier mode, A

outputs the manufacturer’s identification code and A

Table 5) Note: A

Table 5. Read Identifier Table

Size Mfr. ID

1–A21

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

= 0

= 1 outputs the device identifier (see

= 0. To return to read array mode, write the Read Array command (FFH).

Device Identifier

-T

(Top Boot)

-B

(Bottom Boot)

28F004B3 28F400B3 8894H 8895H 28F008B3 28F800B3 8892H 8893H 28F016B3 D0H D1H 28F160B3 28F320B3 8896H 8897H 28F640B3 8898H 8899H

0089H

3.2.3 Read Status Register

The device status register indicates when a program or erase operation is complete and the success or failure of that operation. To read the status register issue the Read Status Register (70H) command to the CUI. This causes all subsequent read operations to output data from the status register until another command is written to the CUI. To return to reading from the array, issue the Read Array (FFH) command.

The status register bits are output on DQ Read Status Register command.

The contents of the status register are latched on the falling edge of OE# or CE#. This prevents possible bus errors which might occur if status register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation.

D4H D5H

D2H D3H

8890H 8891H

–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a

When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether or not the WSM was successful in performing the desired operation (see

Table 7 on page 14).

3.2.3.1 Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before

3UHOLPLQDU\ 11

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. Note, again, that the Read Array command must be issued before data can be read from the memory array.

3.2.4 Program Mode

Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. Programming the

memory results in specific bits within an address location being changed to a “0.” If the user attempts to program “1”s, the memory cell contents do not change and no error occurs.

The status register indicates programming status: while the progr am sequence executes, status bit 7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then V command. If SR.1 is set, a program operation was attempted on a locked block and the operation was aborted.

was not within acceptable limits, and the WSM did not execute the program

The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode.

3.2.4.1 Suspending and Resuming Program

The Program Suspend halts the in-progres s program operation to read data from another location of memory . Once the programming pr ocess starts, writing the Program Suspend comm and to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues t o output status reg ister data after the Program Su spend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to “1”). t

WHRH1/tEHRH1

A Read Array command can now be written to the CUI to read data from bloc ks other than that which is suspended. The only other valid commands while program is suspended, are Read Status Register, Read Identifier, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the program process and status register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status register data when read (see Appendix E for Program Suspend and Resume Flowchart). V suspend mode. RP# must also remain at V

must remain at the same VPP level used for program while in program

IH.

3.2.5 Erase Mode

To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute a sequence of internally-timed events to program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”

specify the program suspend latency.

12 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the erase operation was unsuccessful, SR.5 of the status

register will be set to a “1,” indicating an erase failure. If V the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that V

supply voltage was not within acceptable limits.

After an erase operation, clear the status register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete.

3.2.5.1 Suspending and Resuming Erase

Since an erase operation requires on the o rder of se cond s to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended.

A Read Array/Program command can now be written to the CUI in order to read data from/ program data to blocks other than the one currently suspended. The Program command can subsequently be suspended to read yet another array location. The only valid commands while erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read Identifier. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to V

. This reduces active current consumption.

was not within acceptable limits after

Erase Resume continues the erase sequence when CE# = V operation, the status register must be read and cleared before the next instruction is issued.

Table 6. Command Bus Definitions

Command Notes Oper Addr Data Oper Addr Data

Read Array Write X FFH Read Identifier 2 Write X 90H Read IA ID Read Status Register Write X 70H Read X SRD Clear Status Register Wr ite X 50H

Program 3 Write X Block Erase/Confirm Write X 20H Write BA D0H

Program/Erase Suspend Write X B0H Program/Erase Resume Write X D0H

NOTES:

PA: Program Address PD: Program Da ta BA: Block Address IA: Identifier Address ID: Identifier Data SRD: Status Register Data

1. Bus operations are defined in Table 3.

2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.

= 0 for manufacturer code, A0 = 1 for device code. A1–A

3. Either 40H or 10H command is valid although the standard is 40H.

4. When writing commands to the device, the upper data bus [DQ minimize current draw.

(1,4)

. As with the end of a standard erase

First Bus Cycle Second Bus Cycle

40H /

10H

= 0.

–DQ15] should be either VIL or VIH, to

Write PA PD

3UHOLPLQDU\ 13

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Table 7. Status Register Bit Definition

WSMS ESS ES PS VPPS PSS BLS R

76543210

NOTES:

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready 0 = Busy

SR.6 = ERASE- SUSPEND STATUS (ESS)

1 = Erase Suspended 0 = Erase In Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure 0 = Successful Block Erase

SR.4 = PROGRAM STATUS (PS)

1 = Error in Word Program 0 = Successful Word Program

SR.3 = V

SR.2 = PROGRAM SUSPEND STATUS (PSS)

SR.1 = BLOCK LOCK STATUS

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out

STATUS (VPPS)

Low Detect, Operation Abort

1 = V

0 = V

1 = Program Suspended 0 = Program in Progress/Completed

1 = Program/Erase attempted on locked block;

Operation aborted

0 = No operation to locked blocks

Check Write State Machine bit first to determine word program or block erase completion, before checking program or erase status bits.

When erase suspend is issued, WSM halts execution and sets

both WSMS and ESS bits to “1.” ESS bit remains set at “1” until an Erase Resume command is issued.

When this bit is set to “1,” WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure.

When this bit is set to “1,” WSM has attempted but failed to program a word.

The V V Program or Erase command sequences have been entered, and informs the system if V V WSM. The V feedback between V max and V

When program suspend is issued, WSM halts execution and sets both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a Program Resume command is issued.

If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode.

when polling the status register.

status bit does not provide continuous indication of

level. The WSM interrogates VPP level only after the

has not been switched on. The

PPLK

max and V

min or between V

PP1

is also checked before the operation is verified by the

status bit is not guaranteed to report accurate

min.

PP4

PP1

NOTE: A Command Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set.

3.3 Block Locking

The 3 Volt Advanced Boot Block flash memory architecture features two hardware-lockable parameter blocks.

3.3.1 WP# = VIL for Block Locking

The lockable blocks are locked when WP# = VIL; any program or erase oper ation to a locked b lock will result in an error, which will be reflected in the status register. For top configuration, the top two parameter blocks (blocks #133 and #134 for the 64 Mbit, #69 and #70 for the 32 Mbit, blocks #37 and #38 for the 16 Mbi t, b locks #2 1 and #22 for th e 8 Mbi t, b locks # 13 and #14 f or the 4 Mbi t) are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for 4 /8 /16 /32/64 Mbit) are lockable. Unlocked blocks can be programmed or erased no rmally (unless V

is below V

14 3UHOLPLQDU\

PPLK

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.3.2 WP# = VIH for Block Unlocking

WP# = VIH unlocks all lockable blocks. These blocks can now be programmed or erased. Note that RP# does not ov erri d e WP # l o cki ng as i n prev i ous Bo ot B loc k d evi ces . WP# controls all

block locking and V protection methods.

Table 8. Write Protection Truth Table for the Advanced Boot Block Flash Memory Family

provides protection against spurious writes. Table 8 defines the write

XXV

≥ V

PPLK

≥ V

PPLK

WP# RP# Write Protection Provided

All Blocks Locked

XVIHAll Blocks Locked

V V

Lockable Blocks Locked

All Blocks Unlocked

3.4 VPP Program and Erase Voltages

Intel® 3 Volt Advanced Boot Block products provide in-system programming and erase at 2.7 V. For customers requiring fast programming in their manufacturing environment, 3 Volt Advanced Boot Block includes an additional low-cost 12V programming feature.

The 12 V V found in manufacturing processes; however, it is not intended for extended use. 12V may be applied to V blocks and 2500 cycles on the parameter blocks. V hours maximum.

Warning: Stressing the device beyond these limits may cause permanent damage.

During read operations or idle times, V operations, a 5 V supply is not permitted. The V

11.4 V–12.6 V during program and erase operations.

mode enhances programming performance during the short period of time typically

during program and erase operations for a maximum of 1000 cycles on the main

may be tied to a 5 V supply. For program and erase

may be connected to 12 V for a total of 80

must be supplied with either 2.7 V–3.6 V or

3.4.1 VPP = VIL for Complete Protection

The VPP programming voltage can be held low for complete write protectio n of all blocks in the flash device. When V

is below V

, any program or erase operation will result in a error,

PPLK

prompting the corresponding status register bit (SR.3) to be set.

3.5 Power Consumption

Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption.

3UHOLPLQDU\ 15

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.5.1 Active Power

With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer to the DC Characteristic tables for I overall system power consumption. Minimizing the active current could have a profound ef f ect on system power consumption, especially for battery-operated devices.

current values. Active power is the largest contributor to

3.5.2 Automatic Power Savings (APS)

Automatic Power Savings provides low-power operation during read mode. After d ata is read fr om the memory array and the address lines are quiescent, APS circuitry places the device in a mode where typical current is comparable to I until a new location is read.

. The flash stays in this static state with outputs valid

CCS

3.5.3 Standby Power

With CE# at a logic-high level (VIH) and device in read mode, the flash memory is in standby

mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.

System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements.

3.5.4 Deep Power-Down Mode

The deep power-down mode is activated when RP# = VIL (GND ± 0.2 V). During rea d modes, RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery from deep power-down requires a minimum time of t

Operations, Section 4.5).

During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the addr ess bei ng prog rammed or the block bei ng erased are no l onger valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to V the device clears the status register).

3.6 Power-Up/Down Operation

The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, V

or VCC, powers-up first.

(see AC Characteristics—Read

PHQV

or turning off p ower to

16 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.6.1 RP# Connected to Sy stem Reset

The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status in formation i nstead of array dat a. Intel re commends conn ecting RP# t o the system CPU RESET# signal to allow proper CPU/flash initialization following system reset.

System designers must guard against spurious writes when V both WE# and CE# must be low for a command write, driving either signal to V writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to V By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.

3.6.2 VCC, VPP and RP# Tr ansitions

The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after V

transitions above V

(Lockout voltage), is read array mode.

LKO

After any program or block erase operation is complete (even after V V

), the CUI must be reset to read array mode via the Read Array command if access to the

PPLK

flash memory array is desired.

3.7 Power Supply Decoupling

Flash memory’s power switching characteristics require careful device decoupling. System designers should consider three supply current issues:

1. Standby current levels (I

2. Read current levels (I

3. Transient peaks produced by falling and rising edges of CE#.

CCR

CCS

)

voltages are above V

, regardless of the stat e of it s cont ro l inputs.

transitions down to

. Since

LKO

will inhibit

Transient current magnitudes depend on the dev ice outputs’ capacitive and inductive loadin g. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0 .1 µF ceramic capacitor connected between each V GND, and between its V

and GND. These high-frequency, inherently low-inductance capacitors

and

should be placed as close as possible to the package leads.

3UHOLPLQDU\ 17

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.0 Electrical Specifications

4.1 Absolute Maximum Ratings

Parameter Maximum Rating

Extended Operating Temperature

During Read –40 °C to +85 °C

During Block Erase and Program –40 °C to +85 °C

Temperature under Bias –40 °C to +85 °C Storage Temperature –65 °C to +125 °C Voltage On Any Pin (except V VPP Voltage (for Block Erase and Program) with Respect to GND –0.5 V to +13.5 V VCC and V

Supply Voltage with Respect to GND –0.2 V to +3.7 V

CCQ

Output Short Circuit Current 100 mA

NOTES:

1. Minimum DC voltage is -0.5 V on input/output pins, with allowable undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is V <20 ns

2. Maximum DC voltage on V

Program voltage is normally 2.7 V–3.6 V. Connection to a 11.4 V–12.6 V supply can be done for a

3. V

maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase.

may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details.

4. Minimum DC voltage is -0.5 V on V Maximum DC voltage on V of <20 ns.

5. Output shorted for no more than one second. No more than one output shorted at a time.

, V

and VPP) with Respect to GND –0.5 V to +3.7 V

CCQ

+0.5 V, with allowable overshoot to VCC +1.5 for periods of

may overshoot to +14.0 V for periods <20 ns.

and V

CCQ

and V

, with allowable undershoot to -2.0 V for periods <20 ns.

CCQ

pins is VCC +0.5 V, with allowable overshoot to VCC +1.5 for periods

(1)

(1,2,3)

(4)

(5)

NOTICE: This datasheet contains preliminary information on new products in production. Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.

18 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.2 Operating Conditions

Symbol Parameter Notes Min Max Units

V V

V V V V V

CC1 CC2 CC3 CCQ1 CCQ2 CCQ3 PP1 PP2 PP3 PP4

Operating Temperature –40 +85 °C

VCC Supply Voltage

I/O Supply Voltage

Program and Erase Voltage

Cycling Block Erase Cycling 4 100,000 Cycles

NOTES:

, V

1. V

CC1

Max is 3.3 V on 0.25µm 32-Mbit devices.

2. V

3. During read operations or idle time, 5 V may be applied to V

CCQ1

, and V

program and erase operations

4. Applying V

the main blocks and 2500 cycles on the parameter blocks. V

= 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on

80 hours maximum. See Section 3.4 for details.

4.3 Capacitance

1, 2 2.7 3.6

2.7 2.85

2.7 3.3

12.73.6

1.65 2.5

1.8 2.5

12.73.6

2.7 2.85

2.7 3.3

3, 4 11.4 12.6

must share the same supply when all three are between 2.7 V and 3.6 V.

PP3

indefinitely. VPP must be at valid levels for

may be connected to 12 V for a total of

VoltsV

Volts

TA = 25 °C, f = 1 MHz

Sym Parameter Notes Typ Max Units Conditions

C C

IN OUT

Input Capacitance 1 6 8 pF VIN = 0 V Output Capacitance 1 10 12 pF V

OUT

= 0 V

NOTE: Sampled, not 100% tested.

3UHOLPLQDU\ 19

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.4 DC Characteristics

Sym Parameter

CCS

Input Load Current 1,2 ± 1 ± 1 ± 1 µA

Output Leakage Current 1,2 ± 10 ± 10 ± 10 µA

Standby Current for

0.18 Micron Product Standby Current for

0.25 Micron and

0.4 Micron Product

VCC Power-Down Current for 0.18 Micron Product

CCD

Power-Down Current

for 0.25 Micron and

0.4 Micron Product

VCC Read Current for

0.18 Micron Product

CCR

VCC Read Current for

0.25 and 0.4 Micron

Product

PPD

PPR

VPP Deep Power-Down Current

VPP Read Current 1,4

VCC + VPP Program Current for 0.18 Micron Product

CCW+

PPW

+ VPP Program

Current for 0.25 Micron and 0.4 Micron Product

2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V

CCQ

Unit Test ConditionsV

Note Typ Max Typ Max Typ Max

1,2 7 15 20 50 150 250 µA

1,2 18 35 20 50 150 250 µA

1,2 7 15 7 20 7 20 µA

1,2 7 25 7 25 7 25 µA

1,2,3 9 18 8 15 9 15 mA

1,2,3 10 18 8 15 9 15 mA

0.2 5 0.2 5 0.2 5 µA 2 ±15 2 ±15 2 ±15 µA V

50 200 50 200 50 200 µA V

18 55 18 55 18 55 mA

1,2,4

8 1510301030mA

18 55 18 55 18 55 mA

1,2,4

10 30 10 30 10 30 mA

= VCCMax

= V

CCQ

Max

CCQ

or GND

Max

CCQ

or GND

CCQ

= V

= VCCMax

CCQ

= V

= VCCMax

CE# = RP# = V or during Program/ Erase Suspend

= V

CCQ

or GND

Max

or GND

Max

, CE# =V

=0 mA

OUT

or V

WP# = V

= VCCMax

CCQ

= V

RP# = GND ± 0.2 V

= VCCMax

CCQ

OE# = V f = 5 MHz, I Inputs = V

RP# = GND ± 0.2 V

≤ V

> V

PP1, 2, 3

Program in Progress V

= V

PP4

Program in Progress V

PP1, 2, 3

Program in Progress V

= V

PP4

Program in Progress

20 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

DC Characteristics, Continued

Sym Parameter

VCC + VPP Erase Current for 0.18 Micron Product

CCE

PPE

+ VPP Erase Current

for 0.25 Micron and 0.4 Micron Product

PPES

PPWS

VPP Erase Suspend Current

DC Characteristics, Continued

Sym Parameter

V V

V V V

PPLK

PP1 PP2 PP3 PP4

LKO

LKO2

Input Low Voltage –0.4

Input High Voltage 2.0

Output Low Voltage –0.1 0.1 -0.1 0.1 -0.1 0.1 V

Output High Voltage

VPP Lock-Out Voltage 5 1.5 1.5 1.5 V

VPP during Program and Erase Operations

Prog/Erase

Lock Voltage V

Prog/Erase

CCQ

Lock Voltage

CCQ

2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V

Unit Test ConditionsV

Note Typ Max Typ Max Typ Max

= V

PP1, 2, 3

16 45 21 45 21 45 mA

1,2,4

16 45 16 45 16 45 mA

Program in Progress

= V

PP4

Program in Progress

= V

PP1, 2, 3

20 45 21 45 21 45 mA

1,2,4

16 45 16 45 16 45 mA

Program in Progress

= V

PP4

Program in Progress

= V

PP1, 2, 3, 4

1,4 50 200 50 200 50 200 µA

Program or Erase Suspend in Progress

CCQ

2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V

Unit Test ConditionsV

Note Min Max Min Max Min Max

–0.4 0.4 –0.4 0.4 V

CCQ

–0.4V

CCQ

–0.1V

+0.3V

CCQ

–0.4V

CCQ

–0.1V

CCQ

+0.3V

= VCCMin

= V

CCQ

= 100 µA

= VCCMin

= V

CCQ

= –100 µA

CCQ

Min

CCQ

–0.1V

0.22 V V

+0.3V

Complete Write Protection

52.73.6 V 5 2.7 2.85 V

52.73.3V

5,6 11.4 12.6 11.4 12.6 11.4 12.6 V

1.5 1.5 1.5 V

1.2 1.2 1.2 V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal V

, TA = +25 °C.

3UHOLPLQDU\ 21

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

2. Since each column lists specifications for a different VCC and V conditions V voltage listed at the top of each column. V

Max, V

Max, VCCMin, and V

CCQ

3. Automatic Power Savings (APS) reduces I

4. Sampled, not 100% tested.

5. Erase and program are inhibited when V

, V

PP1

PP2, VPP3

indefinitely. However, V

6. Applying V

main blocks and 2500 cycles on the parameter blocks. V

and V

= 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the

For read operations or during idle time, a 5 V supply may be applied to VPP

PP4.

must be at valid levels for program and erase operations.

maximum. See Section 3.4 for details. For read operations or during idle time, a 5 V supply may be applied to

indefinitely. However, VPP must be at valid levels for program and erase operations.

Figure 5. Input/Output Reference Waveform

CCQ

INPUT

0.0

NOTE: AC test inputs are driven at V

timing ends, at V

CCQ

= V

when V

/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are

CCQ

Min.

CCQ

for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output

CCQ

Figure 6. Test Configuration

voltage range combination, the test

Min refer to the maximum or minimum VCC or V

CCQ

Max is 3.3 V on 0.25µm 32-Mbit devices.

to approximately standby levels in static operation.

CCR

< V

and not guaranteed outside the valid VPP ranges of

PPLK

TEST POINTS

CCQ

may be connected to 12 V for a total of 80 hours

CCQ

OUTPUT

CCQ

0580_05

Device

under

Test

NOTE: See table for component values.

Test Configuration Component Values for Worst

Case Speed Conditions

T e st Conf iguration C

Standard Test 50 25 K 25 K

CCQ1

Standard Test 50 14.5 K 14.5 K

CCQ2

Standard Test 50 16 K 16 K

CCQ3

NOTE: C

includes jig capacitance.

(pF) R1 (Ω) R2 (Ω)

Out

0580_06

22 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.5 AC Characteristics —Read Operations

Density 4/8 Mbit

# Sym Parameter

R1 t R2 t R3 t R4 t R5 t R6 t R7 t R8 t R9 t

Read Cycle Time 80 90 100 110 ns

AVAV

Address to Output Delay 80 90 100 110 ns

AVQV

CE# to Output Delay

ELQV

OE# to Output Delay

GLQV

RP# to Output Delay 600 600 600 600 ns

PHQV

CE# to Output in Low Z

ELQX

OE# to Output in Low Z

GLQX

CE# to Output in High Z

EHQZ

OE# to Output in High Z

GHQZ

Output Hold from Address,

R10 t

CE#, or OE# Change,

Whichever Occurs First

Product 90 ns 110 ns

3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V

Min Max Min Max Min Max Min Max

(1)

(2) (2)

(2)

80 90 100 110 ns 30 30 30 30 ns

00 00 ns 00 00 ns

25 25 25 25 ns 25 25 25 25 ns

00 00 ns

Unit

NOTES:

1. OE# may be delayed up to t

2. Sampled, but not 100% tested.

ELQV–tGLQV

after the falling edge of CE# without impact on t

ELQV

See Figure 7, “AC Waveform: Read Operations” on page 26.

See Figure 5, “Input/Output Reference W aveform” on page 22 for timing measurements and maximum allowable input slew rate.

3UHOLPLQDU\ 23

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics, Continued

Density 1 6 Mbit

#Sym

R1 t

AVAV

R2 t

AVQV

R3 t

ELQV

R4 t

GLQV

R5 t

PHQV

R6 t

ELQX

R7 t

GLQX

R8 t

EHQZ

R9 t

GHQZ

R10 t

Parameter

Read Cycle Time 70 80 80 90 100 110 ns Address to Output

Delay CE# to Output

Delay OE# to Output

Delay RP# to Output Delay 150 150 600 600 600 600 ns CE# to Output in

Low Z OE# to Output in

Low Z CE# to Output in

High Z OE# to Output in

High Z Output Hold from

Address, CE#, or OE# Change, Whichever Occurs First

Product 70 ns 80 ns 90 ns 110 ns

2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V

Min Max Min Max Min Max Min Max Min Max Min Max

70 80 80 90 100 110 ns

(1)

(2)

70 80 80 90 100 110 ns

20 20 30 30 30 30 ns

0000 00 ns

20 20 25 25 25 25 ns

0000 00 ns

(2)

Unit

NOTES:

1. OE# may be delayed up to t

2. Sampled, but not 100% tested.

ELQV–tGLQV

after the falling edge of CE# without impact on t

ELQV

See Figure 7, “AC Waveform: Read Operations” on page 26.

See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum allowable input slew rate.

24 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics, Continued

Density 32 Mbit

#Sym

R1 t

AVAV

R2 t

AVQV

R3 t

ELQV

R4 t

GLQV

R5 t

PHQV

R6 t

ELQX

R7 t

GLQX

R8 t

EHQZ

R9 t

GHQZ

R10 t

Para-

meter

Product 70 ns 90 ns 100 ns 110 ns

2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V 3.0 V–3.3 V 2.7 V–3.3 V

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Read Cycle Time 70 90 90 100 100 110 ns Address to Output

Delay CE# to Output

(1)

Delay OE# to Output

(1)

Delay RP# to Output

Delay CE# to Output in

(2)

Low Z OE# to Output in

(2)

Low Z CE# to Output in

(2)

High Z OE# to Output in

(2)

High Z

70 90 90 100 100 110 ns

20 20 30 30 30 30 ns

150 150 600 600 600 600 ns

0000 00 ns

20 20 25 25 25 25 ns

Output Hold from Address, CE#, or OE# Change, Whichever Occurs

(2)

First

0000 00 ns

NOTES:

1. OE# may be delayed up to t

2. Sampled, but not 100% tested.

ELQV–tGLQV

after the falling edge of CE# without impact on t

ELQV

See Figure 7, “AC Waveform: Read Operations” on page 26.

See Figure 5, “Input/Output Reference Waveform” on page22 for timing measurements and maximum allowable input slew rate.

3UHOLPLQDU\ 25

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics, Continued

Density 64 M bit

# Sym Parameter

R1 t R2 t R3 t R4 t R5 t R6 t R7 t R8 t R9 t

R10 t

Read Cycle Time 90 100 ns

AVAV

Address to Output Delay 90 100 ns

AVQV

CE# to Output Delay 1 90 100 ns

ELQV

OE# to Output Delay 1 20 20 ns

GLQV

RP# to Output Delay 150 150 ns

PHQV

CE# to Output in Low Z 2 0 0 ns

ELQX

OE# to Output in Low Z 2 0 0 ns

GLQX

CE# to Output in High Z 2 20 20 ns

EHQZ

OE# to Output in High Z 2 20 20 ns

GHQZ

Output Hold from Address, CE#, or

OE# Change, Whichever Occurs First

NOTES:

1. OE# may be delayed up to t

2. Sampled, but not 100% tested.

ELQV–tGLQV

See Figure 7 for the AC waveform for read operations. See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum

allowable input slew rate.

Figure 7. AC Waveform: Read Operations

Product 90 ns 100 ns

2.7 V–3.6 V 2.7 V–3.6 V

Note Min Max Min Max

20 0 ns

after the falling edge of CE# without impact on t

ELQV

Unit

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

Standby

High Z

Device

Address Selection

Address Stable

Data Valid

R4 R3

Valid Output

R10

High Z

26 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.6 AC Characteristics —Write Operations

Density 4/8 Mbit

Product 90 ns 110 ns

# Sym Parameter

PHWL

W10

W11 t

PHEL

ELWL

WLEL

ELEH

WLWH

DVWH

DVEH

AVWH

AVEH

WHEH

EHWH

WHDX

EHDX

WHAX

EHAX

WHWL /

EHEL

VPWH

VPEH QVVL

RP# High Recovery to WE# (CE#) Going Low 600 600 600 600 ns

CE# (WE#) Setup to WE# (CE#) Going Low 0000ns

WE# (CE#) Pulse Width 1 70 70 70 70 ns

Data Setup to WE# (CE#) Going High 2 50 50 60 60 ns

Address Setup to WE# (CE#) Going High 2 70 70 70 70 ns

CE# (WE#) Hold Time from WE# (CE#) High 0000ns

Data Hold Time from WE# (CE#) High 2 0000ns

Address Hold Time from WE# (CE#) High 2 0000ns

WE# (CE#) Pulse Width High 1 30 30 30 30 ns

VPP Setup to WE# (CE#) Going High 3 200 200 200 200 ns

Hold from Valid SRD 3 0000ns

Note Min Min Min Min

3.0 V –

3.6 V

2.7 V –

3.6 V

3.0 V –

3.6 V

2.7 V –

3.6 V

Unit

NOTES:

= t

EHEL

or DIN.

= t

ELEH

= t

WHEL

WLEH

= t

EHWL

. Similarly, Write pulse width

ELWH

1. Refer to command definition table (Table 6) for valid A

2. Write pulse width (t high (whichever goes high first). Hence, t high (t (whichever goes low first). Hence, t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

3. Sampled, but not 100% tested.

) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

WPH

= t

WHWL

= t

WLWH

Read timing characteristics during program suspend and erase suspend are the same as during read-only operations. See Figure 5 for timing measurements and maximum allowable input slew rate. See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.

3UHOLPLQDU\ 27

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics—Write Operations, continued

Density 16 Mbit

Product 70 ns 80 ns 90 ns 110 ns

# Sym Parameter

RP# High Recovery to WE# (CE#)

PHWL

W10

W11 t

t t

Going Low

PHEL

CE# (WE#) Setup to WE# (CE#) G oing

ELWL

Low

WLEL

ELEH

WE# (CE#) Pulse Width 1 45 50 70 70 70 70 ns

WLWH

DVWH

Data Setup to WE# (CE#) Going High 2 40 40 50 50 60 60 ns

DVEH

Address Setup to WE# (CE#) Going

AVWH

High

AVEH

CE# (WE#) Hold Time from WE#

WHEH

(CE#) High

EHWH

WHDX

Data Hold Time from WE# (CE#) High 2 0 0 0 0 0 0 ns

EHDX

Address Hold Time from WE# (CE#)

WHAX

High

EHAX

WHWL /

WE# (CE#) Pulse Width High 1 25 30 30 30 30 30 ns

EHEL

VPWH

VPP Setup to WE# (CE#) Going High 3 200 200 200 200 200 200 ns

VPEH

QVVL

Hold from Valid SRD 3 0 0 0 0 0 0 ns

2.7 V –

3.6 V

2.7 V –

3.6 V

3.0 V –

3.6 V

Note Min Min Min Min Min Min

150 150 600 600 600 600 ns

000000ns

2505070707070ns

000000ns

2000000ns

2.7 V –

3.6 V

3.0 V –

3.6 V

2.7 V –

3.6 V

Unit

NOTES:

= t

EHEL

or DIN.

= t

ELEH

= t

WHEL

WLEH

= t

EHWL

. Similarly, Wr ite pulse width

ELWH

1. Refer to command definition table (Table 6) for valid A

2. Write pulse width (t high (whichever goes high first). Hence, t high (t (whichever goes low first). Hence, t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

3. Sampled, but not 100% tested.

) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

WPH

= t

WHWL

= t

WLWH

28 3UHOLPLQDU\

AC Characteristics—Write Operations, continued

# Sym Parameter

RP# High Recovery to WE# (CE#)

PHWL

W10

W11 t

t t

Going Low

PHEL

CE# (WE#) Setup to WE# (CE#) Going

ELWL

Low

WLEL

ELEH

WE# (CE#) Pulse Width 1 45 60 70 70 70 70 ns

WLWH

DVWH

Data Setup to WE# (CE#) Going High 2 40 40 50 50 60 60 ns

DVEH

Address Setup to WE# (CE#) Going

AVWH

High

AVEH

CE# (WE#) Hold Time from WE#

WHEH

(CE#) High

EHWH

WHDX

Data Hold Time from WE# (CE#) High 2 0 0 0 0 0 0 ns

EHDX

Address Ho ld Time from WE# (CE#)

WHAX

High

EHAX

WHWL /

WE# (CE#) Pu lse Width High 1 25 30 30 30 30 30 ns

EHEL

VPWH

VPP Setup to WE# (CE#) Going High 3 200 200 200 200 200 200 ns

VPEH

QVVLVPP

Hold from Valid SRD 3 0 0 0 0 0 0 ns

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Density 32 Mbit

Product 70 ns 90 ns 90 ns 110 ns

2.7 V –

3.6 V

2.7 V –

3.6 V

3.0 V –

3.3 V

2.7 V –

3.3 V

3.0 V –

3.3 V

2.7 V –

3.3 V

Note Min Min Min Min Min Min

150 150 600 600 600 600 ns

000000ns

2506070707070ns

000000ns

2000000ns

Unit

NOTES:

= t

EHEL

or DIN.

= t

ELEH

= t

WHEL

WLEH

= t

EHWL

. Similarly, Write pulse width

ELWH

1. Refer to command definition table (Table 6) for valid A

2. Write pulse width (t high (whichever goes high first). Hence, t high (t (whichever goes low first). Hence, t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

3. Sampled, but not 100% tested.

) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

WPH

= t

WHWL

= t

WLWH

3UHOLPLQDU\ 29

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics—Write Operations, continued

Product 90 ns 100 ns

# Sym Parameter

W10 W11 t

PHWL

ELWL

ELEH

WLWH

DVWH

DVEH

AVWH

WHEH

EHWH

WHDX

EHDX

WHAX

WHWL /

VPWH

RP# High Recovery to WE# (CE#) Going Low 150 150 ns

PHEL

CE# (WE#) Setup to WE# (CE#) Going Low 0 0 ns

WLEL

WE# (CE#) Pulse Width 1 60 70 ns

Data Setup to WE# (CE#) Going High 2 40 40 ns

Address Setup to WE# (CE#) Going High 2 60 60 n s

AVEH

CE# (WE#) Hold Time from WE# (CE#) High 0 0 ns

Data Hold Time from WE# (CE#) High 2 0 0 ns

Address Hold Time from WE# (CE#) High 2 0 0 ns

EHAX

WE# (CE#) Pulse Width High 1 30 30 ns

EHEL

VPP Setup to WE# (CE#) Going High 3 200 200 ns

VPEH QVVLVPP

Hold from Valid SRD 3 0 0 ns

Density 64 Mbit

2.7 V –

3.6 V

Note Min Min

2.7 V –

3.6 V

Unit

NOTES:

= t

EHEL

or DIN.

= t

ELEH

= t

WHEL

WLEH

= t

EHWL

. Similarly, Wr ite pulse width

ELWH

1. Refer to command definition table (Table 6) for valid A

2. Write pulse width (t high (whichever goes high first). Hence, t high (t (whichever goes low first). Hence, t

) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

WPH

3. Sampled, but not 100% tested.

) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

WPH

= t

WHWL

= t

WLWH

30 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.7 Program and Erase Timings

Symbol Parameter

8-KB Parameter Block

BWPB

Program Time (Byte) 4-KW Parameter Block

Program Time (Word) 64-KB Main Block

BWMB

Program Time (Byte) 32-KW Main Block

Program Time(Word) Byte Program Time 2, 3, 4 17 165 8 185 µs

Word Program Time for

WHQV1

/ t

EHQV1

0.18 Micron Product Word Program Time for 0.25

Micron and 0.4 Micron Products 8-KB Parameter Block

WHQV2

/ t

EHQV2

Erase Time (Byte) 4-KW Parameter Block

Erase Time (Word) 64-KB Main Block

WHQV3

/ t

EHQV3

Erase Time (Byte) 32-KW Main Block

Erase Time (Word)

WHRH1

WHRH2

/ t / t

EHRH1 EHRH2

Program Suspend Latency 5 10 5 10 µs Erase Suspend Latency 5 20 5 20 µs

Notes Typ

2.7 V–3.6 V 11.4 V–12.6 V

(1)

Max Typ

(1)

Units

Max

2, 3 0.16 0.48 0.08 0.24 s

2, 3 0.10 0.30 0.03 0.12 s

2, 3, 4 1.2 3.7 0.6 1.7 s

2, 3 0.8 2.4 0.24 1 s

2,3 12 200 8 185 µs

2, 3 22 200 8 185 µs

2, 3, 4 1 4 0.8 4 s

2, 30.540.44s

2, 3, 4 1 5 1 5 s

2, 3 1 5 0.6 5 s

NOTES:

1. Typical values measured at nominal voltages and TA = +25 °C.

2. Excludes external system-level overhead.

3. Sampled, not 100% tested.

4. x8 not available on 0.18 µm offerings

3UHOLPLQDU\ 31

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 8. AC Waveform: Program and Erase Operations

AB C D E F

WP#

High Z

PPH

PPLK

(Note 1)

W3 W4 W7

W10

Valid SRD

W11

ADDRESSES [A]

CE#(WE#) [E(W)]

OE# [G]

WE#(CE#) [W(E)]

DATA [D/Q]

RP# [P]

V [V]

NOTES:

1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register Data.

Power-Up and Standby.

A. V

B. Write Program or Erase Setup Command. C. Write Valid Address and Data (for Program) or Erase Confirm Command. D. Automated Program or Erase Delay. E. Read Status Register Data (SRD): reflects completed program/erase operation. F.Write Read Array Command.

0580_08

32 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

5.0 Reset Operations

Figure 9. AC Waveform: Deep Power-Down/Reset Operation

RP# (P)

(A) Reset during Read Mode

RP# (P)

PLPH

(B) Reset during Program or Block Erase, <

Complete

RP# (P)

PLRH

PLPH

Abort

PLPH

Complete

PLRH

Abort

Deep

Power-

Down

PHQV

PHWL

PHEL

PHQV

PHWL

PHEL

PLPHtPLR

PHQV

PHWL

PHEL

PLPHtPLRH

Reset Specifications

Symbol Parameter Notes

PLPH

PLRH

RP# Low to Reset during Read (If RP# is tied to V

, this specification is not applicable)

RP# Low to Reset during Block Erase or Program 2,3 22 µs

NOTES:

1. If t

2. .Sampled, but not 100% tested.

3. If RP# is asserted while a block erase or

is <100 ns the device may still RESET but this is not guaranteed

PLPH

word program operation is not executing, the reset will complete

within 100 ns.

= 2.7 V–3.6 V

Min Max

1,2 100 ns

0580_09

Unit

3UHOLPLQDU\ 33

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

6.0 Ordering Information

T E 2 8 F 3 2 0 B 3 T C 7 0

Package

TE = 40-Lead/48-Lead TSOP

GT = 48-Ball µBGA* CSP GE = VF BGA CSP

Product line designator

for all Intel® Flash products

Device Density

640 = x16 (64 Mbit) 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) 400 = x16 (4 Mbit)

016 = x8 (16 Mbit) 008 = x8 (8 Mbit) 004 = x8 (4 Mbit)

Access Speed (ns)

(70, 80, 90, 100, 110)

Lithography

Not Present = 0.4 µm A = 0.25 µm C = 0.18 µm

T =

Top Blocking

B =

Bottom Blocking

Product Family

B3 = 3 Volt Advanced Boot Block V

= 2.7 V - 3.6 V

11.4 V - 12.6 V

34 3UHOLPLQDU\

Ordering Information Valid Combinations

40-Lead TSOP 48-Ball µBGA* CSP

Ext. Temp. 64 Mbit

Ext. Temp. 32 Mbit

Ext. Temp. 16 Mbit

Ext. Temp. 8 Mbit

TE28F016B3TA90 TE28F016B3BA90 TE28F016B3TA110 TE28F016B3BA110 TE28F008B3TA90 TE28F008B3BA90 TE28F008B3TA110 TE28F008B3BA110

(3)

GT28F016B3TA90

(3)

GT28F016B3BA90

(3)

GT28F016B3TA110

(3)

GT28F016B3BA110

(3)

GT28F008B3T90 TE28F800B3TA90

(3)

GT28F008B3B90 TE28F800B3BA90

(3)

GT28F008B3T110 TE28F800B3TA110

(3)

GT28F008B3B110 TE28F800B3BA110

TE28F004B3T90 TE28F400B3T90

Ext. Temp 4 Mbit

TE28F004B3B90 TE28F400B3B90 TE28F004B3T110 TE28F400B3T110 TE28F004B3B110 TE28F400B3B110

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

(1,2)

48-Lead TSOP 48-Ball µBGA CSP

TE28F640B3TC90 GT28F640B3TC90 TE28F640B3BC90 GT28F640B3BC90 TE28F640B3TC100 GT28F640B3TC100 TE28F640B3BC100 GT28F640B3BC100 TE28F320B3TC70 GE28F320B3TC70 TE28F320B3BC70 GE28F320B3BC70 TE28F320B3TC90 GE28F320B3TC90 TE28F320B3BC90 GE28F320B3BC90 TE28F320B3TA100 GT28F320B3TA100 TE28F320B3BA100 GT28F320B3BA100 TE28F320B3TA110 GT28F320B3TA110 TE28F320B3BA110 GT28F320B3BA110 TE28F160B3TC70 GE28F160B3TC70 TE28F160B3BC70 GE28F160B3BC70 TE28F160B3TC80 GE28F160B3TC80 TE28F160B3BC80 GE28F160B3BC80

(3)

TE28F160B3TA90

(3)

TE28F160B3BA90

(3)

TE28F160B3TA110

(3)

TE28F160B3BA110

(3)

GT28F160B3TA90

(3)

GT28F160B3BA90

(3)

GT28F160B3TA110

(3)

GT28F160B3BA110

(3)

GT28F800B3T90 GE28F800B3TA90

(3)

GT28F800B3B90 GE28F800B3BA90

(3)

GT28F800B3T110 GE28F008B3TA90

(3)

GT28F800B3B110 GE28F008B3BA90

(1,2)

(3)

48-Ball VF BGA

NOTES:

1. The 48-ball µBGA package top side mark reads F160B3 [or F800B3]. This mark is identical for both x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture. However, once the devices are removed from the shipping media, it may be difficult to dif ferentiate based on the top side mark. The device identifier (accessible through the Device ID command: see Section 3.2.2 for further details) enables x8 and x16 µBGA package product differentiation.

2. The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other assembly codes without an “E” or “S” as the first character are production units.

3. Product can be ordered in either 0.25 µm or 0.4 µm material. The “A” before the access speed specifies

0.25 µm material. For new designs, Intel recommends using 0.25 µm Advanced Boot Block devices.

3UHOLPLQDU\ 35

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

7.0 Additional Information

Order Number Document/Tool

297948 292199 292200

Note 2

Contact your Intel Representative

297874

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical

documentation and tools.

3. For the most current information on Intel Advanced and Advanced+ Boot Block Flash memory, visit our microsite at http://developer.intel.com/design/flash/abblock.

3 Volt Advanced Boot Block Flash Memory Family Specification Update AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory 3 Volt Advanced Boot Block Algorithms (‘C’ and assembly)

http://developer.intel.com/design/flash/swtools

Intel® Flash Data Integrator (IFDI) Software Developer’s Kit IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC

36 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix A Write State Machine Current/Next States

Command Input (and Next State)

Current State SR.7

Read Array “1” Array

Read Status “1” Status

Read

Identifier

Prog. Setup “1” Status Program (Command Input = Data to be Programmed)

Program

(continue)

Program

Suspend to

Read Status

Program Suspend to Read Array

Prog. Susp. to

Read

Identifier

Program

(complete)

Data

When

Read

“1” Identifier

“0” Status

“1” Status

“1” Array

“1” Identifier

“1” Status

Read Array (FFH)

Read

Array

Read

Array

Read

Array

Prog.

Sus. to

Read

Array

Prog.

Susp. to

Read

Array

Prog.

Susp. to

Read

Array

Read

Array

Program

Setup (10/

40H)

Program

Setup

Program

Setup

Program

Setup

Program (continue)

Program Suspend

to Read Array

Program Suspend

to Read Array

Program Suspend

to Read Array

Program

Setup

Erase Setup

(20H)

Erase Setup

Erase

Confirm

(D0H)

Program

(continue)

Program

(continue)

Program

(continue)

Prog/Ers Suspend

(B0H)

Read Array

Prog. Susp.

to Rd. Status

Program Susp. to

Read Array

Program Susp. to

Read Array

Program Susp. to

Read Array

Prog/Ers

Resume

(D0H)

Program

(continue)

Program

(continue)

Program

(continue)

Read

Status

(70H)

Read

Status

Read

Status

Read

Status

Program (continue)

Prog.

Susp. to

Read

Status

Prog.

Susp. to

Read

Status

Prog.

Susp. to

Read

Status

Read

Status

Clear

Status

(50H)

Read Array

Prog.

Sus. to

Read Array

Prog.

Sus. to

Read Array

Prog.

Sus. to

Read Array

Read

Identifi er.

(90H)

Read

Identifier

Read

Identifier

Read

Identifier

Prog.

Susp. to

Read

Identifier

Prog.

Susp. to

Read

Identifier

Prog.

Susp. to

Read

Identifier

Read

Identifier

Erase Setup “1” Status

Erase Cmd.

Error

Erase

(continue)

Erase

Suspend to

Status

Erase Susp.

to Read

Array

Erase Susp.

to Read Identifier

Erase

(complete)

“1” St atus

“0” Status

“1” Status

“1” Array

“1” Identifier

“1” Status

Erase Command Error

Read

Array

Erase

Susp. to

Read

Array Erase

Susp. to

Read

Array Erase

Susp. to

Read

Array

Read

Array

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Erase Setup

Erase (continue)

Erase

Susp. to

Read Array

Erase

Susp. to

Read Array

Erase

Susp. to

Read Array

Erase Setup

Erase

(continue)

Erase

Cmd. Error

Read Array

Erase Sus.

to Read

Status

Erase

Susp. to

Read Array

Erase

Susp. to

Read Array

Erase

Susp. to

Read Array

Erase

(continue)

Erase

Erase Command Error

Read

Status

Erase (continue)

Erase

Susp. to

Read

Status

Erase

Susp. to

Read

Status

Erase

Susp. to

Read

Status

Read

Status

Read Array

Erase

Susp. to

Read Array

Erase

Susp. to

Read Array

Erase

Susp. to

Read Array

Read

Identifier

Ers. Susp.

to Read

Identifier

Ers. Susp.

to Read

Identifier

Ers. Susp.

to Read

Identifier

Read

Identifier

3UHOLPLQDU\ 37

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix B Architecture Block Diagram

DQ0-DQ

CCQ

Output Buffer

Identifier Register

Status

A0-A

Input Buffer

Address

Latch

Address

Counter

Power

Reduction

Control

Y-Decoder

X-Decoder

4-KWord

Parameter Block

Output

Multiplexer

Comparator

Y-Gating/Sensing

4-KWord

Parameter Block

Data

32-KWord

Main Block

Data

32-KWord

Main Block

Input Buffer

Command

User

Interface

Write State

Machine

I/O Logic

Program/Erase Voltage Switch

CE#

WE#

OE# RP#

WP#

GND

0580-C1

38 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix C Word-Wide Memory Map Diagrams

16-Mbit and 32-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW)

4 4 4 4 4 4 4

4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

16 Mbit 32 Mbit

FF000-FFFFF 1FF000-1FFFFF 32 1F8000-1FFFFF FE000-FEFFF 1FE000-1FEFFF 32 1F0000-1F7FFF FD000-FDFFF 1FD000-1FDFFF 32 1E8000-1EFFFF FC000-FCFFF 1FC000-1FCFFF 32 1E0000-1E7FFF FB000-FBFFF 1FB000-1FBFFF 32 1D8000-1DFFFF

FA000-FAFFF 1FA000-1FAFFF 32 1D0000-1D7FFF

F9000-F9FFF 1F9000-1F9FFF 32 1C8000-1CFFFF

F8000-F8FFF 1F8000-1F8FFF 32 1C0000-1C7FFF

F0000-F7FFF 1F0000-1F7FFF 32 1B8000-1BFFFF E8000-EFFFF 1E8000-1EFFFF 32 1B0000-1B7FFF

E0000-E7FFF 1E0000-1E7FFF 32 1A8000-1AFFFF D8000-DFFFF 1D8000-1DFFFF 32 1A0000-1A7FFF D0000-D7FFF 1D0000-1D7FFF 32 198000-19FFFF C8000-CFFFF 1C8000-1CFFFF 32 190000-197FFF C0000-C7FFF 1C0000-1C7FFF 32 188000-18FFFF B8000-BFFFF 1B8000-1BFFFF 32 180000-187FFF

B0000-B7FFF 1B0000-1B7FFF 32 178000-17FFFF A8000-AFFFF 1A8000-1AFFFF 32 170000-177FFF

A0000-A7FFF 1A0000-1A7FFF 32 168000-16FFFF

98000-9FFFF 198000-19FFFF 32 160000-167FFF

90000-97FFF 190000-197FFF 32 158000-15FFFF

88000-8FFFF 188000-18FFFF 32 150000-157FFF

80000-87FFF 180000-187FFF 32 148000-14FFFF

78000-7FFFF 178000-17FFFF 32 140000-147FFF

70000-77FFF 170000-177FFF 32 138000-13FFFF

68000-6FFFF 168000-16FFFF 32 130000-137FFF

60000-67FFF 160000-167FFF 32 128000-12FFFF

58000-5FFFF 158000-15FFFF 32 120000-127FFF

50000-57FFF 150000-157FFF 32 118000-11FFFF

48000-4FFFF 148000-14FFFF 32 110000-117FFF

40000-47FFF 140000-147FFF 32 108000-10FFFF

38000-3FFFF 138000-13FFFF 32 100000-107FFF

30000-37FFF 130000-137FFF 32 F8000-FFFFF 0F8000-0FFFFF

28000-2FFFF 128000-12FFFF 32 F0000-F7FFF 0F0000-0F7FFF

20000-27FFF 120000-127FFF 32 E8000-EFFFF 0E8000-0EFFFF

18000-1FFFF 118000-11FFFF 32 E0000-E7FFF 0E 0000-0E7FFF

10000-17FFF 110000-117FFF 32 D8000-DFFFF 0D8000-0DFFFF

08000-0FFFF 108000-10FFFF 32 D0000-D7FFF 0D0000-0D7FFF

00000-07FFF 100000-107FFF 32 C8000-CFFFF 0C8000-0CFFFF

This column continues on next page This column continues on next page

Size

(KW)

8 Mbit 16 Mbit 32 Mbit

3UHOLPLQDU\ 39

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit and 32-Mbit Word-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

Size

(KW)

32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

16 Mbit 32 Mbit

0F8000-0FFFFF 32 C0000-C7FFF 0C0000-0C7FFF

0F0000-0F7FFF 32 B8000-BFFFF 0B8000-0BFFFF 0E8000-0EFFFF 32 B0000-B7FFF 0B0000-0B7FFF 0E0000-0E7FFF 32 A8000-AFFFF 0A8000-0AFFFF 0D8000-0DFFFF 32 A0000-A7FFF 0A0000-0A7FFF 0D0000-0D7FFF 32 98000-9FFFF 098000-09FFFF 0C8000-0CFFFF 32 90000-97FFF 090000-097FFF 0C0000-0C7FFF 32 88000-8FFFF 088000-08FFFF 0B8000-0BFFFF 32 80000-87FFF 080000-087FFF 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF

098000-09FFFF 32 60000-67FFF 60000-67FFF

090000-097FFF 32 58000-5FFFF 58000-5FFFF

088000-08FFFF 32 50000-57FFF 50000-57FFF

080000-087FFF 32 48000-4FFFF 48000-4FFFF

078000-07FFFF 32 40000-47FFF 40000-47FFF

070000-077FFF 32 38000-3FFFF 38000-3FFFF

068000-06FFFF 32 30000-37FFF 30000-37FFF

060000-067FFF 32 28000-2FFFF 28000-2FFFF

058000-05FFFF 32 20000-27FFF 20000-27FFF

050000-057FFF 32 18000-1FFFF 18000-1FFFF

048000-04FFFF 32 10000-17FFF 10000-17FFF

040000-047FFF 32 08000-0FFFF 08000-0FFFF

038000-03FFFF 4 07000-07FFF 07000-07FFF

030000-037FFF 4 06000-06FFF 06000-06FFF

028000-02FFFF 4 05000-05FFF 05000-05FFF

020000-027FFF 4 04000-04FFF 04000-04FFF

018000-01FFFF 4 03000-03FFF 03000-03FFF

010000-017FFF 4 02000-02FFF 02000-02FFF

008000-00FFFF 4 01000-01FFF 01000-01FFF

000000-007FFF 4 00000-00FFF 00000-00FFF

Size

(KW)

16 Mbit 32 Mbit

40 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4-Mbit and 8-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW)

4 30000-37FFF 70000-77FFF 32 38000-3FFFF 38000-3FFFF 4 28000-2FFFF 68000-6FFFF 32 30000-37FFF 30000-37FFF 4 20000-27FFF 60000-67FFF 32 28000-2FFFF 28000-2FFFF 4 18000-1FFFF 58000-5FFFF 32 20000-27FFF 20000-27FFF 4 10000-17FFF 50000-57FFF 32 18000-1FFFF 18000-1FFFF 4 08000-0FFFF 48000-4FFFF 32 10000-17FFF 10000-17FFF 4 00000-07FFF 40000-47FFF 32 08000-0FFFF 08000-0FFFF

4 38000-3FFFF 4 07000-07FFF 07000-07FFF 32 30000-37FFF 4 06000-06FFF 06000-06FFF 32 28000-2FFFF 4 05000-05FFF 05000-05FFF 32 20000-27FFF 4 04000-04FFF 04000-04FFF 32 18000-1FFFF 4 03000-03FFF 03000-03FFF 32 10000-17FFF 4 02000-02FFF 02000-02FFF 32 08000-0FFFF 4 01000-01FFF 01000-01FFF 32 00000-07FFF 4 00000-00FFF 00000-00FFF

4 Mbit

3F000-3FFFF 7F000-7FFFF

3E000-3EFFF 7E000-7EFFF 32 70000-77FFF 3D000-3DFFF 7D000-7DFFF 32 68000-6FFFF 3C000-3CFFF 7C000-7CFFF 32 60000-67FFF

3B000-3BFFF 7B000-7BFFF 32 58000-5FFFF

3A000-3AFFF 7A000-7AFFF 32 50000-57FFF

39000-39FFF 79000-79FFF 32 48000-4FFFF

38000-38FFF 78000-78FFF 32 40000-47FFF

Size

(KW)

32 78000-7FFFF

4 Mbit 8 Mbit

3UHOLPLQDU\ 41

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW)

4 FF000-FFFFF 1FF000-1FFFFF 3FF000-3FFFFF 32 4 FE000-FEFFF 1FE000-1FEFFF 3FE000-3FEFFF 32 4 FD000-FDFFF 1FD000-1FDFFF 3FD000-3FDFFF 32 4 FC000-FCFFF 1FC000-1FCFFF 3FC000-3FCFFF 32 4 FB000-FBFFF 1FB000-1FBFFF 3FB000-3FBFFF 32 4 FA000-FAFFF 1FA000-1FAFFF 3FA000-3FAFFF 32 4 F9000-F9FFF 1F9000-1F9FFF 3F9000-3F9FFF 32

4 F8000-F8FFF 1F8000-1F8FFF 3F8000-3F8FFF 32 32 F0000-F7FFF 1F0000-1F7FFF 3F0000-3F7FFF 32 32 E8000-EFFFF 1E8000-1EFFFF 3E8000-3EFFFF 32 32 E0000-E7FFF 1E0000-1E7FFF 3E0000-3E7FFF 32 32 D8000-DFFFF 1D8000-1DFFFF 3D8000-3DFFFF 32 32 D0000-D7FFF 1D0000-1D7FFF 3D0000-3D7FFF 32 32 C8000-CFFFF 1C8000-1CFFFF 3C8000-3CFFFF 32 32 C0000-C7FFF 1C0000-1C7FFF 3C0000-3C7FFF 32 32 B8000-BFFFF 1B8000-1BFFFF 3B8000-3BFFFF 32 32 B0000-B7FFF 1B0000-1B7FFF 3B0000-3B7FFF 32 32 A8000-AFFFF 1A8000-1AFFFF 3A8000-3AFFFF 32 32 A0000-A7FFF 1A0000-1A7FFF 3A0000-3A7FFF 32 32 98000-9FFFF 198000-19FFFF 398000-39FFFF 32 32 90000-97FFF 190000-197FFF 390000-397FFF 32 32 88000-8FFFF 188000-18FFFF 388000-38FFFF 32 32 80000-87FFF 180000-187FFF 380000-387FFF 32 32 78000-7FFFF 178000-17FFFF 378000-37FFFF 32 32 70000-77FFF 170000-177FFF 370000-377FFF 32 32 68000-6FFFF 168000-16FFFF 368000-36FFFF 32 32 60000-67FFF 160000-167FFF 360000-367FFF 32 32 58000-5FFFF 158000-15FFFF 358000-35FFFF 32 32 50000-57FFF 150000-157FFF 350000-357FFF 32 32 48000-4FFFF 148000-14FFFF 348000-34FFFF 32 32 40000-47FFF 140000-147FFF 340000-347FFF 32 32 38000-3FFFF 138000-13FFFF 338000-33FFFF 32 32 30000-37FFF 130000-137FFF 330000-337FFF 32 32 28000-2FFFF 128000-12FFFF 328000-32FFFF 32 32 20000-27FFF 120000-127FFF 320000-327FFF 32 32 18000-1FFFF 118000-11FFFF 318000-31FFFF 32 32 10000-17FFF 110000-117FFF 310000-317FFF 32 32 08000-0FFFF 108000-10FFFF 308000-30FFFF 32 32 00000-07FFF 100000-107FFF 300000-307FFF 32 32 32 32 32 32 32 32 32 32 32

16 Mbit 32 Mbit 64 Mbit

0F8000-0FFFFF 2F8000-2FFFFF 32 2C0000-2C7FFF

0F0000-0F7FFF 2F0000-2F7FFF 32 2B8000-2BFFFF 0E8000-0EFFFF 2E8000-2EFFFF 32 2B0000-2B7FFF 0E0000-0E7FFF 2E0000-2E7FFF 32 2A8000-2AFFFF

0D8000-0DFFFF 2D8000-2DFFFF 32 2A0000-2A7FFF

0D0000-0D7FFF 2D0000-2D7FFF 32 298000-29FFFF

0C8000-0CFFFF 2C8000-2CFFFF 32 290000-297FFF

0C0000-0C7FFF 2C0000-2C7FFF 32 288000-28FFFF 0B8000-0BFFFF 2B8000-2BFFFF 32 280000-287FFF 0B0000-0B7FFF 2B0000-2B7FFF 32 278000-27FFFF

This column continues on next page This column continues on next page

Size

(KW)

16 Mbit 32 Mbit 64 Mbit

3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF

398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF

300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF

42 3UHOLPLQDU\

Size

(KW)

32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

16 Mbit 32 Mbit 64 Mbit

0A8000-0AFFFF 2A8000-2AFFFF 32 270000-277FFF 0A0000-0A7FFF 2A0000-2A7FFF 32 268000-26FFFF

098000-09FFFF 298000-29FFFF 32 260000-267FFF 090000-097FFF 290000-297FFF 32 258000-25FFFF 088000-08FFFF 288000-28FFFF 32 250000-257FFF 080000-087FFF 280000-287FFF 32 248000-24FFFF 078000-07FFFF 278000-27FFFF 32 240000-247FFF 070000-077FFF 270000-277FFF 32 238000-23FFFF 068000-06FFFF 268000-26FFFF 32 230000-237FFF 060000-067FFF 260000-267FFF 32 228000-22FFFF 058000-05FFFF 258000-25FFFF 32 220000-227FFF 050000-057FFF 250000-257FFF 32 218000-21FFFF 048000-04FFFF 248000-24FFFF 32 210000-217FFF 040000-047FFF 240000-247FFF 32 208000-20FFFF 038000-03FFFF 238000-23FFFF 32 200000-207FFF 030000-037FFF 230000-237FFF 32 1F8000-1FFFFF 1F8000-1FFFFF 028000-02FFFF 228000-22FFFF 32 1F0000-1F7FFF 1F0000-1F7FFF 020000-027FFF 220000-227FFF 32 1E8000-1EFFFF 1E8000-1EFFFF 018000-01FFFF 218000-21FFFF 32 1E0000-1E7FFF 1E0000-1E7FFF 010000-017FFF 210000-217FFF 32 1D8000-1DFFFF 1D8000-1DFFFF 008000-00FFFF 208000-21FFFF 32 1D0000-1D7FFF 1D0000-1D7FFF 000000-007FFF 200000-207FFF 32 1C8000-1CFFFF 1C8000-1CFFFF

1F8000-1FFFFF 32 1C0000-1C7FFF 1C0000-1C7FFF

1F0000-1F7FFF 32 1B8000-1BFFFF 1B8000-1BFFFF 1E8000-1EFFFF 32 1B0000-1B7FFF 1B0000-1B7FFF 1E0000-1E7FFF 32 1A8000-1AFFFF 1A8000-1AFFFF

1D8000-1DFFFF 32 1A0000-1A7FFF 1A0000-1A7FFF

1D0000-1D7FFF 32 198000-19FFFF 198000-19FFFF

1C8000-1CFFFF 32 190000-197FFF 190000-197FFF

1C0000-1C7FFF 32 188000-18FFFF 188000-18FFFF 1B8000-1BFFFF 32 180000-187FFF 180000-187FFF 1B0000-1B7FFF 32 178000-17FFFF 178000-17FFFF 1A8000-1AFFFF 32 170000-177FFF 170000-177FFF 1A0000-1A7FFF 32 168000-16FFFF 168000-16FFFF

198000-19FFFF 32 160000-167FFF 160000-167FFF

190000-197FFF 32 158000-15FFFF 158000-15FFFF

188000-18FFFF 32 150000-157FFF 150000-157FFF

180000-187FFF 32 148000-14FFFF 148000-14FFFF

178000-17FFFF 32 140000-147FFF 140000-147FFF

170000-177FFF 32 138000-13FFFF 138000-13FFFF

168000-16FFFF 32 130000-137FFF 130000-137FFF

160000-167FFF 32 128000-12FFFF 128000-12FFFF

158000-15FFFF 32 120000-127FFF 120000-127FFF

150000-157FFF 32 118000-11FFFF 118000-11FFFF

148000-14FFFF 32 110000-117FFF 110000-117FFF

140000-147FFF 32 108000-10FFFF 108000-10FFFF

138000-13FFFF 32 100000-107FFF 100000-107FFF

130000-137FFF 32 F8000-FFFFF F8000-FFFFF F8000-FFFFF

128000-12FFFF 32 F0000-F7FFF F0000-F7FFF F0000-F7FFF

120000-127FFF 32 E8000-EFFFF E8000-EFFFF E8000-EFFFF

118000-1 1FFFF 32 E0000-E7FFF E0000-E7FFF E0000-E7FFF

110000-117FFF 32 D8000-DFFFF D8000-DFFFF D8000-DFFFF 108000-10FFFF 32 D0000-D7FFF D0000-D7FFF D0000-D7FFF 100000-107FFF 32 C8000-CFFFF C8000-CFFFF C8000-CFFFF

This column continues on next page This column continues on next page

Size

(KW)

16 Mbit 32 Mbit 64 Mbit

3UHOLPLQDU\ 43

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

Size

(KW)

32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32

16 Mbit 32 Mbit 64 Mbit

0F8000-0FFFFF 32 C0000-C7FFF C0000-C7FFF C0000-C7FFF 0F0000-0F7FFF 32 B8000-BFFFF B8000-BFFFF B8000-BFFFF 0E8000-0EFFFF 32 B0000-B7FFF B0000-B7FFF B0000-B7FFF 0E0000-0E7FFF 32 A8000-AFFFF A8000-AFFFF A8000-AFFFF

0D8000-0DFFFF 32 A0000-A7FFF A0000-A7FFF A0000-A7FFF

0D0000-0D7FFF 32 98000-9FFFF 98000-9FFFF 98000-9FFFF

0C8000-0CFFFF 32 90000-97FFF 90000-97FFF 90000-97FFF

0C0000-0C7FFF 32 88000-8FFFF 88000-8FFFF 88000-8FFFF 0B8000-0BFFFF 32 80000-87FFF 80000-87FFF 80000-87FFF 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF

098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF

Size

(KW)

16 Mbit 32 Mbit 64 Mbit

44 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix D Byte-Wide Memory Map Diagrams

8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing

Top Boot Bottom Boot

Size (KB) 8 Mbit 16 Mbit Size (KB) 8 Mbit 16 Mbit

8 FE000-FFFFF 1FE000-1FFFFF 64 8 FC000-FDFFF 1FC000-1FDFFF 64 8 FA000-FBFFF 1FA000-1FBFFF 64 8 F8000-F9FFF 1F8000-1F9FFF 64 8 F6000-F7FFF 1F6000-1F7FFF 64 8 F4000-F5FFF 1F4000-1F5FFF 64 8 F2000-F3FFF 1F2000-1F3FFF 64

8 F0000-F1FFF 1F0000-1F1FFF 64 64 E0000-EFFFF 1E0000-1EFFFF 64 64 D0000-DFFFF 1D0000-1DFFFF 64 64 C0000-CFFFF 1C0000-1CFFFF 64 64 B0000-BFFFF 1B0000-1BFFFF 64 64 A0000-AFFFF 1A0000-1AFFFF 64 64 90000-9FFFF 190000-19FFFF 64 64 80000-8FFFF 180000-18FFFF 64 64 70000-7FFFF 170000-17FFFF 64 64 60000-6FFFF 160000-16FFFF 64 64 50000-5FFFF 150000-15FFFF 64 64 40000-4FFFF 140000-14FFFF 64 64 30000-3FFFF 130000-13FFFF 64 64 20000-2FFFF 120000-12FFFF 64 64 10000-1FFFF 110000-11FFFF 64 64 00000-0FFFF 100000-10FFFF 64 64 0F0000-0FFFFF 64 64 0E0000-0EFFFF 64 64 0D0000-0DFFFF 64 64 0C0000-0CFFFF 64 64 0B0000-0BFFFF 64 64 0A0000-0AFFFF 64 64 090000-09FFFF 64 64 080000-08FFFF 64 64 070000-07FFFF 64 64 060000-06FFFF 64 1F0000-1FFFFF 64 64 64 64 64 64

This column continues on next page This column continues on next page

050000-05FFFF 64 1E0000-1EFFFF 040000-04FFFF 64 1D0000-1DFFFF 030000-03FFFF 64 1C0000-1CFFFF 020000-02FFFF 64 1B0000-1BFFFF 010000-01FFFF 64 1A0000-1AFFFF 000000-00FFFF 64 190000-19FFFF

3UHOLPLQDU\ 45

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

8-Mbit and 16-Mbit Byte-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

Size (KB) 8 Mbit 16 Mbit Size (KB) 8 Mbit 16 Mbit

64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64

64 180000-18FFFF 64 170000-17FFFF 64 160000-16FFFF 64 150000-15FFFF 64 140000-14FFFF 64 130000-13FFFF 64 120000-12FFFF 64 110000-11FFFF 64 100000-10FFFF 64 F0000-FFFFF 0F0000-0FFFFF 64 E0000-EFFFF 0E0000-0EFFFF 64 D0000-DFFFF 0D0000-0DFFFF 64 C0000-CFFFF 0C0000-0CFFFF 64 B0000-BFFFF 0B0000-0BFFFF 64 A0000-AFFFF 0A0000-0AFFFF 64 90000-9FFFF 090000-09FFFF 64 80000-8FFFF 080000-08FFFF 64 70000-7FFFF 070000-07FFFF 64 60000-6FFFF 060000-06FFFF 64 50000-5FFFF 050000-05FFFF 64 40000-4FFFF 040000-04FFFF 64 30000-3FFFF 030000-03FFFF 64 20000-2FFFF 020000-02FFFF 64 10000-1FFFF 010000-01FFFF

8 0E000-0FFFF 00E000-00FFFF 8 0C000-0DFFF 00C000-00DFFF 8 0A000-0BFFF 00A000-00BFFF 8 08000-09FFF 008000-009FFF 8 06000-07FFF 006000-007FFF 8 04000-05FFF 004000-005FFF 8 02000-03FFF 002000-003FFF 8 00000-01FFF 000000-001FFF

46 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4-Mbit Byte-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KB)

8 7E000-7FFFF 8 7C000-7DFFF 64 60000-6FFFF 8 7A000-7BFFF 64 50000-5FFFF 8 78000-79FFF 64 40000-4FFFF 8 76000-77FFF 64 30000-3FFFF 8 74000-75FFF 64 20000-2FFFF 8 72000-73FFF 64 10000-1FFFF

8 70000-71FFF 8 0E000-0FFFF 64 60000-6FFFF 8 0C000-0DFFF 64 50000-5FFFF 8 0A000-0BFFF 64 40000-4FFFF 8 08000-09FFF 64 30000-3FFFF 8 06000-07FFF 64 20000-2FFFF 8 04000-05FFF 64 10000-1FFFF 8 02000-03FFF 64 00000-0FFFF 8 00000-01FFF

4 Mbit

Size

(KB)

64 70000-7FFFF

4 Mbit

3UHOLPLQDU\ 47

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix E Program and Erase Flowcharts

Figure 10. Program Flowchart

Start

Write 40H

Program Address/Data

Read Status Register

SR.7 = 1?

Yes

Full Status

Check if Desired

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

SR.3 =

SR.4 =

VPP Range Error

Programming Error

SR.1 =

Attempted Program to

Locked Block - Aborted

Program Successful

Bus Operation

Write

Read

Standby

Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of

program operations. Write FFH after the last program operation to reset device to read array mode.

Bus Operation

Standby

SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked.

If an error is detected, clear the status register before attempting retry or other error recovery.

Command

Program Setup

Program

Command Comments

Comments

Data = 40H

Data = Data to Program Addr = Location to Program

Status Register Data Toggle CE# or OE# to Update Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.3 1 = V

Low Detect

Check SR.4 1 = V

Program Error

Check SR.1 1 = Attempted Program to Locked Block - Program Aborted

0580_E1

48 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 11. Program Suspend/Resume Flowchart

Start

Write B0H

Write 70H

Read Status Register

SR.7 =

SR.2 =

Write FFH

Read Array Data

Done

Reading

Program Completed

Bus

Operation

Write

Read

Standby

Write

Read

Write

Command

Program Suspend

Read Status

Read Array

Program Resume

Comments

Data = B0H Addr = X

Data = 70H Addr = X

Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.2 1 = Program Suspended 0 = Program Completed

Data = FFH Addr = X

Read array data from block other than the one being programmed.

Data = D0H Addr = X

Yes

Write FFHWrite D0H

Program Resumed Read Array Data

0580_E2

3UHOLPLQDU\ 49

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 12. Block Erase Flowchart

Start

Write 20H

Write D0H and

Block Address

Read Status Register

SR.7 =

Suspend Erase

Full Status

Check if Desired

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

SR.3 =

SR.4,5 =

VPP Range Error

Command Sequence

Block Erase ErrorSR.5 =

SR.1 =

Attempted Erase of

Locked Block - Aborted

Block Erase

Successful

Error

Suspend

Erase Loop

Yes

Bus Operation

Write

Read

Standby

Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of

block erasures. Write FFH after the last write operation to reset device to read array mode.

Bus Operation

Standby

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked.

If an error is detected, clear the status register before attempting retry or other error recovery.

Command

Erase Setup

Erase Confirm

Command Comments

Comments

Data = 20H Addr = Within Block to Be Erased

Data = D0H Addr = Within Block to Be Erased

Status Register Data Toggle CE# or OE# to Update Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.3 1 = V

Low Detect

Check SR.4,5 Both 1 = Command Sequence Error

Check SR.5 1 = Block Erase Error

Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted

0580_E3

50 3UHOLPLQDU\

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 13. Erase Suspend/Resume Flowchart

Start

Write B0H

Write 70H

Read Status Register

SR.7 =

SR.6 =

Write FFH

Read Array Data

Done

Reading

Yes

Erase Completed

Bus Operation

Write

Write Read Status

Read

Standby

Write

Read

Write Erase Resume

Erase Suspend

Read Array

Command

Comments

Data = B0H Addr = X

Data = 70H Addr = X

Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.6 1 = Erase Suspended 0 = Erase Completed

Data = FFH Addr = X

Read array data from block other than the one being erased.

Data = D0H Addr = X

Write FFHWrite D0H

Erase Resumed Read Array Data

0580_E4

3UHOLPLQDU\ 51

INTEL 28F320B3, 28F640B3 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual