INTEL 28F160S3, 28F320S3 User Manual

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查询28F160S3供应商

Two 32-Byte Write Buffers

Low Voltage Operation

100 ns Read Access Time (16 Mbit) 110 ns Read Access Time (32 Mbit)

High-Density Symmetrically-Blocked Architecture

System Performance Enhancements

Industry-Standard Packaging

WORD-WIDE

FlashFile™ MEMORY FAMILY

28F160S3, 28F320S3

Includes Extended Temperature Specifications

2.7 µs per Byte Effective Programming Time

2.7V or 3.3V V

2.7V, 3.3V or 5V V

32 64-Kbyte Erase Blocks (16 Mbit) 64 64-Kbyte Erase Blocks (32 Mbit)

STS Status Output

µBGA* package, SSOP, and TSOP (16 Mbit) µBGA* package and SSOP (32 Mbit)

ADVANCE INFORMATION

Cross-Compatible Command Support

Intel Standard Command Set Common Flash Interface (CFI) Scaleable Command Set (SCS)

100,000 Block Erase Cycles

Enhanced Data Protection Features

Absolute Protection with VPP = GND

Flexible Block Locking Block Erase/Program Lockout during Power Transitions

Configurable x8 or x16 I/O

Automation Suspend Options

Program Suspend to Read Block Erase Suspend to Program Block Erase Suspend to Read

ETOX™ V Nonvolatile Flash Technology

Intel’s Word-Wide FlashFile™ m emory fam ily prov ides high-dens ity, low-cost , non-volat ile, read/ write st orage solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various densities in the same pac kage type. Thei r symmet rically-bloc ked architec ture, flex ible voltage, and ext ended cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend capabilities provide an ideal soluti on for code or data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of prot ect ion: absolut e protec ti on with V alternatives give designers ultimate control of their code security needs.

This family of product s is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It c omes in the industry-standard 56-lead SSOP and µBGA packages. In addition, the 16-Mb device is available in the industry-standard 56-lead TSOP package.

at GND, selective block locking, and program/erase lockout during power transitions. These

June 1997 Order Number: 290608-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The 28F160S3 and 28F320S3 may contain design defects or errors known as errata. Current characterized errata are available

on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com

*Third-party brands and names are the property of their respective owners.

E 28F160S3, 28F320S3

CONTENTS

PAGE PAGE

1.0 INTRODUCTION .............................................5

1.1 New Features...............................................5

1.2 Product Overview.........................................5

1.3 Pinout and Pin Description...........................6

2.0 PRINCIPLES OF OPERATION .....................10

2.1 Data Protection ..........................................11

3.0 BUS OPERATION.........................................12

3.1 Read..........................................................12

3.2 Output Disable...........................................12

3.3 Standby......................................................12

3.4 Deep Power-Down.....................................12

3.5 Read Query Operation...............................12

3.6 Read Identifier Codes Operation................13

3.7 Write ..........................................................13

4.0 COMMAND DEFINITIONS............................13

4.1 Read Array Command................................16

4.2 Read Query Mode Command.....................17

4.2.1 Query Structure Output .......................17

4.2.2 Query Structure Overview ...................19

4.2.3 Block Status Register..........................20

4.2.4 CFI Query Identification String.............21

4.2.5 System Interface Information...............22

4.2.6 Device Geometry Definition.................23

4.2.7 Intel-Specific Extended Query Table ...24

4.3 Read Identifier Codes Command...............25

4.4 Read Status Register Command................25

4.5 Clear Status Register Command................26

4.6 Block Erase Command ..............................26

4.7 Full Chip Erase Command.........................26

4.8 Write to Buffer Command...........................27

4.9 Byte/Word Write Command........................27

4.10 STS Configuration Command...................28

4.11 Block Erase Suspend Command..............28

4.12 Program Suspend Command...................28

4.13 Set Block Lock-Bit Commands.................29

4.14 Clear Block Lock-Bits Command..............29

5.0 DESIGN CONSIDERATIONS........................39

5.1 Three-Line Output Control..........................39

5.2 STS and WSM Polling................................39

5.3 Power Supply Decoupling ..........................39

Trace on Printed Circuit Boards...........39

5.4 V

, VPP, RP# Transitions..........................39

5.5 V

5.6 Power-Up/Down Protection........................39

6.0 ELECTRICAL SPECIFICATIONS..................40

6.1 Absolute Maximum Ratings........................40

6.2 Operating Conditions..................................40

6.2.1 Capacitance.........................................41

6.2.2 AC Input/Output Test Conditions .........41

6.2.3 DC Characteristics...............................42

6.2.4 AC Characteristics - Read-Only

Operations..........................................44

6.2.5 AC Characteristics - Write Operations .46

6.2.6 Reset Operations.................................48

6.2.7 Erase, Program, And Lock-Bit

Configuration Performance.................49

APPENDIX A: Device Nomenclature and

Ordering Information ..................................51

APPENDIX B: Additional Information...............52

ADVANCE INFORMATION

28F160S3, 28F320S3 E

REVISION HISTORY

Number Description

-001 Original version

ADVANCE INFORMATION

E 28F160S3, 28F320S3

1.0 INTRODUCTION

This datasheet contains 16- and 32-Mbit WordWide FlashFile 28F320S3) specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organizat ion and f unctional ity. Section 6 covers electrical specifications for extended temperature product offerings.

memory (28F160S3 and

1.1 New Features

The Word-Wide FlashFile memory family maintains

basic compatibility with Intel’s 28F016SA and 28F016SV. Key enhancements include:

• Common Flash Interface (CFI) Support

• Scaleable Command Set (SCS) Support

• Low Voltage Technology

• Enhanced Suspend Capabilities

They share a compatible Status Register, basic software commands, and pinout . These similarities enable a clean migration from the 28F016SA or 28F016SV. When upgrading, it is important to note the following differences:

• Because of new feature and density options, the devices have different manufacturer and device identifier codes. This allows for soft ware optimization.

• New software commands.

• To take advantage of low voltage on the

28F160S3 and 28F320S3, allow V connection to VCC. The 28F160S3 and 28F320S3 do not support a 12V V

option.

1.2 Product Overview

The Word-Wide FlashFile memory family provides density upgrades with pinout compatibility for the 16- and 32-Mbit densities. They are highperformance memories arranged as 1 Mword and 2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of 8 bits. This data is grouped in thirty-two and s ixtyfour 64-Kbyte blocks that can be erased, locked and unlocked in-system. Figure 1 shows the block diagram, and Figure 5 illustrates the memory organization.

This family of product s are optimized for fast factory programming and low power designs. Specifically designed for 3V systems, the 28F160S3 and 28F320S3 support read operations at 2.7V–3.6V Vcc with block erase and program operations at

2.7V–3.6V and 5V V performance is achieved through highly-optimized write buffers. A 5V V faster factory programm ing. For a si mple l ow power design, V Additionally, the dedic ated V data protection when V

Internal V configures the device for optimized write operations.

A Common Flash Interface (CFI) permits OEMspecified software algori thms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direc t-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor and internal device operation. A valid command sequence written to the CUI initiates device automation. An internal Write State M ac hi ne (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 64-Kbyte blocks typically within t independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block.

Data is programmed in byte, word or page increments. Program suspend mode enables the system to read data or execute code from any other flash memory array location.

and VPP can be tied to 2.7V.

detection circuitry automatically

. High programming

option is available for ev en

pin gives complet e

≤ V

PPLK

WHQV2/EHQV2

ADVANCE INFORMATION

28F160S3, 28F320S3 E

The device incorporates two Write Buffers of 32 bytes (16 words) to allow optimum-performance data programming. This feature can improve system program performance by up to four times over non-buffer programming.

Individual block loc king us es a c ombi nation of bl ock lock-bits to lock and unlock blocks. Block lock-bits gate block erase, full chi p erase, program and write to buffer operations. Lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) set and clear lock-bits.

The Status Register and the STS pin in RY/BY# mode indicate whether or not the device is busy executing an operation or ready for a new command. Polling the Status Register, system software retrieves WSM f eedback. STS in RY/BY# mode gives an additional indicator of WSM ac tivity by providing a hardware status signal. Like the Status Register, RY/BY#-low indicates that the WSM is performing a block erase, program , or l ock bit operation. RY/BY#-high indicat es that the WSM is ready for a new command, block erase is suspended (and program is inactive), program is suspended, or the device is in deep power-down mode.

The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching).

The BYTE# pin allows either x 8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode with address A byte and high byte. BYTE# at logic high enables 16-bit operation with address A lowest order address. Addres s A bit mode.

When one of the CE pins are at V

selecting between the low

becoming the

is not used in 16-

# pins (CE0#, CE1#) and RP#

, the component enters a CMOS standby mode. Driving RP# t o GND enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and cl ears the St atus Regis ter. A reset time (t

) is required from RP# switching

PHQV

high until outputs are valid. Likewise, the device has a wake time (t

) from RP#-high until writes

PHEL

to the CUI are recognized.

1.3 Pinout and Pin Description

The 16-Mbit device is available in the 56-lead TSOP, 56-lead SSOP and µBGA packages. The 32- Mb device is available i n the 56-lead S SOP and

µBGA packages. The pinouts are shown in Figures 2, 3 and 4.

DQ0 - DQ

16-Mbit: A0- A 32-Mbit: A

0 - A21

Input Buffer

Address

Latch

Address Counter

Y-Decoder

X-Decoder

Output Buffer

Output

Multiplexer

Comparator

16-Mbit: Thirty-two 32-Mbit: Sixty-four

Query

Identifier Register

Status

Data

Y-Gating

64-Kbyte Blocks

Input Buffer

Data

Multiplexer

STS

BYTE# CE#

WE# OE# RP# WP#

GND

I/O Logic

Command

User

Interface

Write Buffer

Write State

Machine

Program/Erase Voltage Switch

Figure 1. Block Diagram

ADVANCE INFORMATION

E 28F160S3, 28F320S3

Table 1. Pin Descriptions

Sym Type Name and Function

A0–A

–

CE0#, CE

RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations

OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle. WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data

STS OPEN

WP# INPUT WRITE PROTECT: Master control for block locking. When VIL, locked blocks

BYTE# INPUT BYTE ENABLE: Configures x8 mode (low) or x16 mode (high). V

GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated.

INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally

INPUT/

OUTPUT

INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and

DRAIN

OUTPUT

SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:

SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. Do not attempt block

latched during a write cycle. A In x16 mode, A

DATA INPUTS/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, Status Register, query and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle.

sense amplifiers. With CE0# or CE1# high, the device is deselected and power consumption reduces to standby levels. Both CE the device. Device selection occurs with the latter falling edge of CE first rising edge of CE

which provides data protection during system power transitions, puts the device in deep power-down mode, and resets internal automation. RP#-high enables normal operation. Exit from deep power-down sets the device to read array mode.

are latched on the rising edge of the WE# pulse.

STATUS: Indicates the status of the internal state machine. When configured in level mode (default), it acts as a RY/BY# pin. For this and alternate configurations of the STATUS pin, see the Configuration command. Tie STS to V resistor.

cannot be erased or programmed, and block lock-bits cannot be set or cleared.

Necessary voltage to perform block erase, program, and lock-bit configuration operations. Do not float any power pins.

erase, program, or block-lock configuration with invalid V

is not used; input buffer is off.

16-Mbit → A

0–A20

# or CE1# disables the device.

selects high or low byte when operating in x8 mode.

32-Mbit → A0–A

# and CE1# must be low to select

values.

# or CE1#. The

with a pull-up

ADVANCE INFORMATION

28F160S3, 28F320S3 E

28F016SA 28F016SV

3/5#

NC A

CE0#

RP#

GND

28F160S3 28F160S5

NC A

CE0#

RP#

GND

1 56

2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29

56-LEAD TSOP

STANDARD PINOUT

14 mm x 20 mm

TOP VIEW

28F160S3 28F160S5

WP# WE# OE#

STS

DQ GND DQ

DQ DQ

GND DQ

DQ DQ

BYTE#

NC NC

9 1 8 0

28F016SA 28F016SV

WP# WE# OE#

RY/BY#

GND DQ

BYTE#

NC NC

Highlights pinout changes.

Figure 2. TSOP 56-Lead Pinout

ADVANCE INFORMATION

E 28F160S3, 28F320S3

Figure 3. SSOP 56-Lead Pinout

ADVANCE INFORMATION

28F160S3, 28F320S3 E

GND A10 VPP CE0 A14 VCC

A4 A7 A9 A11 A12 A15 A17 A19

A5 A6 A8 RP# A13 A16 A21 A20

A2 A1 A3 A18 CE1 NC

NC NC BYTE# DQ7 WP# WE#

A0 DQ8 DQ1 DQ3 DQ12DQ6 DQ15OE#

DQ0 DQ9 DQ2 DQ11DQ4 DQ13DQ14 STS

VCC DQ10 GND VCC DQ5 GND

Bottom View

NOTES:

1. Figures are not drawn to scale.

2. Address A21 is not included in the 28F160S3.

3. More information on µBGA* packages is available by contacting your Intel/Distribution sales office.

This is the view of the package as surface mounted on

the board. Note that the signal s are mirror imaged.

GNDA10VPPCE0A14VCC

NCNCBYTE#DQ7WP#WE#

DQ0DQ9DQ2DQ11DQ4DQ13DQ14 STS

VCCDQ10 GNDVCCDQ5GND

Figure 4. µBGA* Package Pinout

A4A7A9A11A12A15A17A19

A5A6A8RP#A13A16A21A20

A2A1A3A18CE1NC

A0DQ8DQ1DQ3DQ12DQ6DQ15OE#

2.0 PRINCIPLES OF OPERATION

The word-wide memories include an on-chip Write State Machine (WSM) to manage block erase, program, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power suppli es duri ng block erasure, programming, lock-bit c onfiguration, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from deep power-down mode (see Bus Operations), the

device defaults to read array mode. Manipul ation of external memory control pins all ow array read, standby, and output disable operations.

Read Array, Status Regis ter, query , and identif ier codes can be accessed through the CUI independent of the V programming voltage on V

voltage. Proper

enables successful

block erasure, program, and lock-bit configuration. All functions associated with altering memory contents—bloc k erase, program,

lock-bit configuration—are acces sed via the CUI and verified through the Status Register.

ADVANCE INFORMATION

E 28F160S3, 28F320S3

Commands are written using standard microprocessor write timings. The CUI c ontents serve as input to the WSM that controls the block erase, programming, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, identifier codes, or Status Register data.

Interface software that initiates and polls progress of block erase, program ming, and lockbit configuration can be stored in any bl ock. This code is copied to and executed from system RAM during flash memory updates. After successful com pletion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write dat a from any other block. Program suspend all ows system software to suspend a program to read data from any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer may choose to make the V supply switchable or hardwired to V device supports either design practice, and encourages optimization of the processormemory interface.

When V altered. When high voltage is appli ed to V two-step block erase, program, or lock-bit configuration command sequences provide protection from unwanted operations. All write functions are disabled when V the write lockout v oltage V V

provides additional protection from inadvertent code or data alteration.

≤ V

. The device’s block locking capability

, memory contents cannot be

PPLK

voltage is below

or when RP# is at

LKO

PPH1/2

power

. The

, the

ADVANCE INFORMATION

Figure 5. Memory Map

28F160S3, 28F320S3 E

3.0 BUS OPERATION

The local CPU reads and writes fl ash m emory i nsystem. All bus cycles to or from the flash memory conform to standard mic roprocessor bus cycles.

3.1 Read

Block information, query information, identifier codes and Status Registers can be read independent of the V

voltage.

The first task is to place the device into the desired read mode by writing the appropriate read-mode command (Read Array, Query, Read Identifier Codes, or Read Stat us Register) to t he CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically reset s to read array mode. Control pins dictate the data flow in and out of the component. CE active to obtain data at the outputs. CE CE

# are the device selection controls, and,

#, CE1# and OE# must be driven

# and

when both are active, enable the selected memory device. OE# is the data output (DQ

) control: When active it drives the selected

memory data onto the I/O bus. WE# must be at V

and RP# must be at VIH. Figure 17 illustrates

a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ

–DQ15 are

placed in a high-impedance state.

3.3 Standby

CE0# or CE1# at a logic-high level (VIH) places the device in standby mode, substantially reducing device power consumption. DQ (or DQ0– DQ7 in x8 mode) outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, programming, or lock-bit configuration, the device continues functioning and consuming act ive power until the operation completes.

–DQ

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode. In read mode, RP#-low deselects the memory,

places output drivers in a high-impedance state, and turns off all internal circuits. RP# must be held low for time t

PLPH

. Time t

is required

PHQV

after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the Status Register is set to 80H.

During block erase, programming, or lock-bit configuration modes, RP#-low will abort the operation. STS in RY/BY# mode remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after programming or partially altered af ter an erase or lock-bit configuration. Time t RP# goes to logic-high (V command can be written.

is required after

PHWL

) before another

It is important in any automated system to assert

–

RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status informat ion when access ed during block erase, programming, or lock-bit configuration modes. I f a CPU reset occurs with no flash memory reset , proper CPU initialization may not occur because the f las h memory may be providing status inform ati on inst ead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In t his application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.5 Read Query Operation

The read query operation outputs block status, Common Flash Interface (CFI) ID string, system interface, device geometry, and Intel-specific extended query information.

ADVANCE INFORMATION

E 28F160S3, 28F320S3

3.6 Read Identifier Codes Operation

The read-identifier codes operation outputs the manufacturer code, devic e code, and block lock configuration codes for each block configuration (see Figure 6). Using the manufacturer and device codes, the system software can automatically match the device with its proper algorithms. The block-lock configuration codes

identify each block’s lock-bit setting.

3.7 Write

Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the Status Register. Additionally, when V and lock-bit configuration can also be performed.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Write command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and address within the block to be locked. The Clear Block Lock-Bits command requires the command and an address within the device.

The CUI does not occupy an addressable memory location. I t is written when WE#, CE and CE and data needed to execute a command are latched on the rising edge of WE# or CE (CE Standard microprocessor writ e timings are used. Figure 18 illustrates a write operation.

= V

# are active and OE# = VIH. The address

#, CE1#), whichever goes high first.

, block erasure, programming,

PPH1/2

4.0 COMMAND DEFINITIONS

VPP voltage ≤ V from the Status Register, identifier codes, or memory blocks. Placing V successful bloc k erase, programming, and lockbit configuration operations.

enables read operations

PPLK

on VPP enables

PPH1/2

Figure 6. Device Identifier Code Memory Map

ADVANCE INFORMATION

Device operations are selec ted by writ ing spec ifi c commands into the CUI. and Table 3 define these commands.

28F160S3, 28F320S3 E

Table 2. Bus Operations

Mode Notes RP# CE0#CE1# OE#

Read 1,2 V Output Disable V Standby V

Reset/Power-

10 V

Down Mode Read Identifier

4VIHV

Codes Read Query 5 V Write 3,6,7 V

X X X X X X High Z High Z

(11)

X X X X High Z X

NOTES:

1. Refer to Table 19. When V

2. X can be V

or VIH for control and address input pins and V

≤ V

, memory contents can be read, but not altered.

PPLK

voltages.

3. STS in level RY/BY# mode (default) is V

configuration algorithms. It is V

when the WSM is executing internal block erase, programming, or lock-bit

when the WSM is not busy, in block erase suspend mode (with programming inactive),

program suspend mode, or deep power-down mode.

4. See Section 4.3 for read identifier code data.

5. See Section 4.2 for read query data.

6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when V

= V

7. Refer to Table 3 for valid D

8. DQ refers to DQ

9. High Z will be V

(see Section 6.2).

CC1/2

if BYTE# is low and DQ

0–7

with an external pull-up resistor.

during a write operation.

if BYTE# is high.

0–15

10. RP# at GND ± 0.2V ensures the lowest deep power-down current.

11. OE# = V

and WE# = VIL concurrently is an undefined state and should not be attempted.

(11)

WE#

Address V

XXD X X High Z X

See

Figure 6

VIHSee Table 6 X D

or V

PPH1/2

for VPP. See Table 19, for V

(8)

OUT

and V

PPLK

= V

PPH1/2

and

STS

High Z

PPH1/2

(3)

(9)

ADVANCE INFORMATION

E 28F160S3, 28F320S3

Table 3. Word-Wide FlashFile™ Memory Command Set Definitions

Command Scaleable

Read Array SCS/BCS 1 Write X FFH Read Identifier Codes SCS/BCS ≥2 5 Write X 90H Read IA ID Read Query SCS ≥ 2 Write X 98H Read QA QD Read Status Register SCS/BCS 2 Write X 70H Read X SRD Clear Status Register SCS/BCS 1 Write X 50H Write to Buffer SCS > 2 8, 9, 10 Write BA E8H Write BA N Word/Byte Program SCS/BCS 2 6,7 Write X 40H

Block Erase SCS/BCS 2 6,10 Write X 20H Write BA D0H Block Erase, Word/Byte

Program Suspend Block Erase, Word/Byte

Program Resume STS pin Configuration SCS 2 Write X B8H Write X CC Set Block Lock-Bit SCS 2 11 Write X 60H Write BA 01H Clear Block Lock-Bits SCS 2 12 Write X 60H Write X D0H Full Chip Erase SCS 2 10 Write X 30H Write X D0H

or Basic

Command

Set

SCS/BCS 1 6 Write X B0H

SCS/BCS 1 6 Write X D0H

(14)

Bus

Cycles

Req'd

Notes First Bus Cycle Second Bus Cycle

Oper

(1)

Addr

(2)

Data

10H

(3,4)

(13)

(1)

Oper

Write PA PD

Addr

(2)

Data

(3,4)

ADVANCE INFORMATION

28F160S3, 28F320S3 E

NOTES:

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.

BA = Address within the block being erased or locked. IA = Identifier Code Address: see Table 12. QA = Query database Address. PA = Address of memory location to be programmed.

3. ID = Data read from Query database.

SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. (See Table 14.)

4. The upper byte of the data bus (DQ

5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See

Section 4.3 for read identifier code data.

6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at V

suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V will fail.

7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.

8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.

9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1

byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the buffer boundary causes unexpected results and should be avoided.

10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.

Confirm also reactivates suspended operations.

11. A block lock-bit can be set only while WP# is V

12. WP# must be at V

to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.

13. Commands other than those shown above are reserved for future use and should not be used.

14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The

Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.

) during command writes is a “Don’t Care” in x16 operation.

8–15

in order to perform block erase, program and

ADVANCE INFORMATION

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