INTEL 28F128J3A, 28F640J3A, 28F320J3A User Manual

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3 Volt Intel® StrataFlash™ Memory

28F128J3A, 28F640J3A, 28F320J3A (x8/x16)

Preliminary Datasheet

Product Features

■ High-Density Symmetrically-Blocked

Architecture

—128 128-Kbyte Erase Blocks (128 M) —64 128-Kbyte Erase Blocks (64 M) —32 128-Kbyte Erase Blocks (32 M)

■ High Performance Interface Asynchronous

Page Mode Reads

—110/25 ns Read Access Time (32 M) —120/25 ns Read Access Time (64 M) —150/25 ns Read Access Time (128 M)

■ 2.7 V–3.6 V V

■ 128-bit Protection Register

Operation

—64-bit Unique Device Identifier —64-bit User Programmable OTP Cells

■ Enhanced Data Protection Features

Absolute Protection with V

—Flexible Block Locking

PEN

= GND

—Block Erase/Program Lockout during

Power Transitions

■ Packaging

—56-Lead TSOP Package —64-Ball Intel

■ Cross-Compatib le Com m and Support Intel

Easy BGA Package

Basic Command Set

—Common Flash Interface —Scalable Command Set

■ 32-Byte Write Buffer

—6 µs per Byte Effective Programming

Time

■ 12.8M Total Min. Erase Cycles (128 Mbit)

6.4M Total Min. Erase Cycles (64 Mbit)

3.2M Total Min. Erase Cycles (32 Mbit) —100K Minimum Erase Cycles per Block

■ Automation Suspend Options

—Block Erase Suspend to Read —Block Erase Suspend to Program —Program Suspend to Read

■ 0.25 µ Intel

StrataFlash™ Memory

Technology

Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel®

StrataFlash™ memory products provide 2X the bi ts in 1X the space, with new features for mainstream performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring reliable, two-bit-pe r-cell storage technology to the flash market segment.

Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR de vices, support for code and data storage, and easy migration to futur e devices.

Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash memory devices take advantage of over one billion units of manufa cturing experience since 1987. As a result, Intel StrataFlash components are ideal for code and data applic ations where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging.

By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F 160S3 and 28F320S3 ), and first generat ion Intel StrataFl as h me mo r y (28 F 6 40 J 5 an d 28F320J5) devices.

Intel StrataFlash memory components deliver a new generation of f orward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density up grades and optimized write capabilities of future Inte l StrataFlash memory devices.

Manufactured on In te l® 0.25 micron ETOX™ VI process technology, Intel StrataFlash memory provides the highest levels of quality and reliability.

Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number: 290667-008

April 2001

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F128J3A, 28F640J3A, 28F320J3A may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Contents

1.0 Product Overview.......................................................................................................1

2.0 Principles of Operation............................................................................................6

2.1 Data Protection......................................................................................................6

3.0 Bus Operations...........................................................................................................7

3.1 Read......................................................................................................................8

3.2 Output Disable.......................................................................................................8

3.3 Standby.................................................................................................................8

3.4 Reset/Power-Down ...............................................................................................8

3.5 Read Query...........................................................................................................9

3.6 Read Identifier Codes............................................................................................9

3.7 Write......................................................................................................................9

4.0 Command Definitions...............................................................................................9

4.1 Read Array Command.........................................................................................13

4.2 Read Query Mode Command .............................................................................13

4.2.1 Query Structure Output ..........................................................................13

4.2.2 Query Structure Overview......................................................................14

4.2.3 Block Status Register.............................................................................15

4.2.4 CFI Query Identification String ...............................................................15

4.2.5 System Interface Information .................................................................16

4.2.6 Device Geometry Definition....................................................................17

4.2.7 Primary-Vendor Specific Extended Query Table....................................18

4.3 Read Identifier Codes Command........................................................................19

4.4 Read Status Register Command.........................................................................20

4.5 Clear Status Register Command.........................................................................22

4.6 Block Erase Command........................................................................................22

4.7 Block Erase Suspend Command ........................................................................22

4.8 Write to Buffer Command...................... ...... ....... ...... ...........................................23

4.9 Byte/Word Program Commands .........................................................................24

4.10 Program Suspend Command.......... ...... ...... .............................................. ...... ....24

4.11 Set Read Configuration Command .....................................................................24

4.11.1 Read Configuration ................................................................................25

4.12 Configuration Command .................................... ...... ....... ...... ....... ...... ....... ..........25

4.13 Set Block Lock-Bit Commands............................................................................26

4.14 Clear Block Lock-Bits Command.........................................................................27

4.15 Protection Register Program Command .............................................................27

4.15.1 Reading the Protection Register ............................................................27

4.15.2 Programming the Protection Register ....................................................27

4.15.3 Locking the Protection Register .............................................................28

5.0 Design Considerations..........................................................................................38

5.1 Three-Line Output Control...................................................................................38

5.2 STS and Block Erase, Program, and Lock-Bit Configuration Polling ..................38

5.3 Power Supply Decoupling ...................................................................................38

5.4 Input Signal Transitions - Reducing Overshoots and Undershoots When Using

Preliminary iii

28F128J3A, 28F640J3A, 28F320J3A

Buffers or Transceivers39

5.5 VCC, VPEN, RP# Transitions.............................................................................39

5.6 Power-Up/Down Protection.................................................................................39

5.7 Power Dissipation ...............................................................................................40

6.0 Electrical Specifications........................................................................................40

6.1 Absolute Maximum Ratings ................................................................................40

6.2 Operating Conditions ..........................................................................................41

6.3 Capacitance ........................................................................................................41

6.4 DC Characteristics ..............................................................................................42

6.5 AC Characteristics— Read-Only Operations

6.6 AC Characteristics— Write Operations

6.7 Block Erase, Program, and Lock-Bit Configuration Performance

(1,2)

.................................................45

.........................................................47

(1,2,3)

...............48

7.0 Ordering Information..............................................................................................51

8.0 Additional Information...........................................................................................52

iv Preliminary

Revision History

Date of Revision Version Description

07/07/99 -001 Original Version 08/03/99 -002 A 09/07/99 -003 Changed Minimum Block Erase time,I

12/16/99 -004 Changed Block Erase time and t

03/16/00 -005 Added Program Max time

06/26/00 -006 Updated cover sheet statement of 700 million units to one billion.

2/15/01 -007 Updated cover page to reflect 100K minimum erase cycles.

04/13/01 -008 Revised Section 7.0, Ordering Information

28F128J3A, 28F640J3A, 28F320J3A

indicated on block diagram

0–A2

, IOH, Page Mode and Byte

Mode currents. Modified RP# on AC Waveform for Write Operations

Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries Changed Min program time to 211 µs Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart

Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter

table Removed V

setting and changed V

CCQ1

Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed V Removed V Updated I

of 0.45 V

of 2.4 V

Typ values

CCR

Added Max lock-bit program and lock times Added note on max measurements

Corrected Table 10 to show correct maximum program tim es. Corrected error in Max block program time in section 6.7 Corrected typical erase time in section 6.7

Updated cover page to reflect 110 ns 32M read speed. Removed Set Read Configuration command from Table 4. Updated Table 8 to reflect reserved bits are 1-7; not 2-7. Updated Table 16 bit 2 definition from R to PSS. Changed V

Characteristics

Max voltage from 0.8 V to 2.0 V, Section 6.4, DC

PENLK

Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5, AC Characteristics–Read-Only Operations

Updated write parameter W13 (t

6.6, AC Characteristics–Write Operations Updated Max. Program Suspend Latency W16 (t

µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Per-

formance

(1,2,3)

AVWH

to V

CCQ2/3

) from 90 ns to 500 ns, Section

WHRL

CCQ1/2

(1,2)

WHRH1

) from 30 to 75

Preliminary v

1.0 Product Overview

The 0.25 µ 3 Volt Intel StrataFlash memory family contains high-density memories organized as 16 Mbytes or 8 Mwords (128-Mbit ), 8 Mbytes or 4 Mwords (64-Mbi t), and 4 Mbyt es or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable insystem. A 128-bit prot ection regist er has multi ple uses, incl uding unique flash device identification.

The device’s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems.

A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

Scalable Command Set (SCS) allows a single, simple software driver in al l host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs.

28F128J3A, 28F640J3A, 28F320J3A

A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software t o suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended.

Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the W rite Buf fer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer w rites.

Individual block locking u ses block lock-bits to lock and un lock blo cks. Block lock- bits gate b lock erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands ).

The status register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished.

The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software po lling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# pin. When low , STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is

Preliminary 1

28F128J3A, 28F640J3A, 28F320J3A

suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the S TS pin to be confi gured to puls e on completion of programmi ng and/or block erases.

Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2,

“Chip Enable Truth Table” on page 7) reduces decoder logic typically required for mu lti- chip

designs. External logic is not required when designing a s ingle chip, a dual chip, or a 4-chip miniature card or SIMM module.

The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode; address A operation; address A

selects between the low byte and high byte. BYTE# at logic high enables 16-bit

becomes the lowest order address and address A0 is not used (don’t care). A

device block diagram is shown in Figure 1 on page 2. When the device is disabled (see Table 2 on page 7) and the R P# pin is at V

enabled. When the RP# pin is at GND, a further po wer-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (t from RP# switching high until outputs are valid. Likewise, the device has a wake time (t from RP#-high until writes to the CUI are recognized. W ith RP# at GND, the WSM is reset and the status register is cleared.

3 Volt Intel StrataFlash memory devices are available in two package types. Both 56-lead TSOP (Thin Small Outline Package) and BGA (Ball Grid Array Package) s upport all offered densities.

Figure 2 and Figure 3 show the pinouts.

Figure 1. 3 Volt Intel

CCQ

32-Mbit: A0- A 64-Mbit: A0 - A

128-Mbit: A0 - A

21 22

Input Buffer

Address

Latch

Address Counter

StrataFlash™ Memory Block Diagram

DQ0 - DQ

A0- A

Y-Decoder

X-Decoder

Output

Buffer

Output

Latch/Multiplexer

128-Mbit: One-hundred

Identifier Register

Comparator

32-Mbit: Thirty-two 64-Mbit: Sixty-four

128-Kbyte Blocks

Query

Status

Data

Y-Gating

twenty-eight

Input Buffer

Data

Multiplexer

, the standby mode is

) is required

PHQV

Logic

STS

BYTE#

CE CE

CE WE# OE# RP#

PEN

V GND

I/O Logic

Command

Write Buffer

User

Interface

Write State

Machine

Program/Erase Voltage Switch

0 1 2

PHWL

)

2 Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Table 1. Lead Descriptions

Symbol Type Name and Function

1–A23

DQ0–DQ

–

INPUT

INPUT/

OUTPUT

INPUT/

OUTPUT

INPUT

RP# INPUT

OE# INPUT

WE# INPUT

OPEN

STS

DRAIN

OUTPUT

BYTE# INPUT

PEN

INPUT

SUPPLY DEVICE POWER SUPPLY: With VCC ≤ V

OUTPUT

CCQ

BUFFER

SUPPLY GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated. DU DON’T USE: Do not drive bal l t o V

BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high).

ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A 64-Mbit: A0–A 128-Mbit: A0–A

0–A21

LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during Command User Interface (CUI) writes. Outputs array, query, identifier, or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs

–DQ0 are also floated when the Write State Machine (WSM) is busy. Check SR.7 (status register

bit 7) to determine WSM status. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs

array, query, or identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy.

CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 2 on page 7), power reduces to standby levels.

All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE CE

, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of

, CE1, or CE2 that disables the device (see Table 2 on page 7).

RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions.

OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle. OE# is active low.

WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks. WE# is active low. Addresses and data are lat ched on the rising edge of the WE# pulse.

STATUS: Indicates the status of t he internal state machine. When configured in level mode (default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS pin, see the Configurations command. Tie STS to V

with a pull-up resistor.

CCQ

BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ

, while DQ8–DQ15 float. Address A0 selects between the high and low byte. BYTE# high places

the device in x16 mode, and turns off the A address.

input buffer. Address A1 then becomes the lowest order

ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits.

With V

PEN

≤ V

, memory contents cannot be altered.

PENLK

LKO

, all write attempts to the flash memory are inhibited.

OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output voltages. To obtain output voltages compatible with system data bus voltages, connect V

or VIL, leave disconnected

to the system supply voltage.

CCQ

–

Preliminary 3

28F128J3A, 28F640J3A, 28F320J3A

Figure 2. 3 Volt Intel® StrataFlash™ Memory Easy BGA Package

1 2 3 4 5 6 7 8

A1A6A8V

PENA13VCCA18A22

(1)

A2GND A9CE0#A14DU A19CE1#

3A7A10A12A15

DU A20A

A4A5A

DQ8DQ1DQ9DQ3DQ4DU DQ15STS

RP# DU DU A16A

BYTE# DQ

(2)

0DQ10DQ11DQ12

A0DQ2V

CCQDQ5DQ6DQ14

DU DU OE#

#DU VCCGND DQ13GND DQ7A

WE#

(3)

Top View - Ball Side Down Bottom View - Ball Side Up

32 Mbit, 64 Mbit and 128 Mbit: 10 x 13 x 1.2 mm

1.0 mm-ball pitch

NOTES:

1. Address A

2. Address A

3. Address A

4. Don’t Use (DU) pins refer to pins that should not be connected

is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC)

is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC)

is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC)

8 7 6 5 4 3 2 1

(1)

A18VCCA13V

CE1#A19DU A14CE0#A9GND A

A21A20DU A15A12A10A7A

A17A16DU

STS DQ

DU DQ4DQ3DQ9DQ1DQ

PENA8A6A1

DU RP# A

11A5A4

OE# DU DU DQ12DQ11DQ10DQ0BYTE#

WE# DQ

14DQ6DQ5VCCQDQ2A0A23

(3)

DQ7GND DQ13GND VCCDU CE2#

(2)

0667-02

4 Preliminary

28F128J3A, 28F640J3A, 28F320J3A

Figure 3. 3 Volt Intel® StrataFlash™ Memory 56-Lead TSOP (32/64/128 Mbit) Offers an Easy

Migration from the 32-Mbit Intel StrataFlash Component (28F320J5) or the 16-Mbit FlashFile™ Component (28F160S3)

28F160S3

RP#

GND

28F320J5

(4)

PEN

RP#

GND

3 Volt Intel

StrataFlash

Memory

32/64/128M

(1)

PEN

RP#

GND

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Intel® StrataFlash™ Memory

56-Lead TSOP

Standard Pinout

14 mm x 20 mm

Top View

3 Volt Intel

StrataFlash

Memory

32/64/128M

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

(3)

WE# OE# STS DQ

GND DQ

CCQ

GND DQ

BYTE#

(2)

Highlights pinout changes

NOTES:

exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this pin is a no-connect (NC).

1. A

exists on 128-Mbit densities. On 32- and 64-Mbit densities this pin is a no-connect (NC).

2. A

exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this pin is a no-connect (NC) .

3. A

= 5 V ± 10% for the 28F640J5/28F320J5.

4. V

28F320J5

NC WE# OE# STS DQ

GND DQ

CCQ

GND DQ

2 (4)

BYTE#

NC CE

28F160S3

WP# WE# OE# STS DQ

GND DQ

BYTE#

NC NC

0667-03

Preliminary 5

28F128J3A, 28F640J3A, 28F320J3A

2.0 Principles of Operation

The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program, and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from reset/power-down mode (see Section 3.0, “Bus

Operations” on page 7), the device defaults to read array mode. Manipulation of external memory

control pins allows array read, standby, and output disable operations. Read array, s tatus register, query, and identifier codes can be accessed through the CUI (Comma nd

User Interface) independent of the V erasure, programming, and lock-bit configuration. All functions associated with altering memory contents—block erase, program, lock-bit configuration—are accessed via the CUI and verified through the status register.

Commands are written using standard micro-processor write timings. The CUI contents serve as input to the WSM, which controls the block erase, program, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during program cycles.

voltage. V

PEN

PENH

on V

enables successful block

PEN

Interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or program dat a from/to any other block. Program suspend allows system so ftware to suspe nd a program to read data from any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer may choose to make the V (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to V optimization of the processor-memory interface.

When V

PEN

≤ V

word program, and lock-bit configuration command sequences provide protection from unwanted operations even when V below the write lockout voltage V provides additional protection from inadvertent code or data alteration by gating erase and program operations.

. The device accommodates either design practice and encourages

PENH

, memory contents cannot be altered. The CUI’s two-step block erase, byte/

PENLK

is applied to V

PENH

switchable

PEN

. All program functions are disabled when VCC is

PEN

or when RP# is VIL. The device’s block locking capability

LKO

6 Preliminary

3.0 Bus Operations

The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

Figure 4. Memory Map

28F128J3A, 28F640J3A, 28F320J3A

A [23-0]:128 Mbit

A [22-0]: 64 Mbit A [21-0]: 32 Mbit

FFFFFF

FE0000

7FFFFF

7E0000

3FFFFF

3E0000

03FFFF

020000

01FFFF

000000

Byte-Wide (x8) Mode

128-Kbyte Block

128-Kbyte Block 128-Kbyte Block

127

A [23-1]: 128 Mbit

A [22-1]: 64 Mbit A [21-1]: 32 Mbit

7FFFFF

7F0000

3FFFFF

3F0000

1FFFFF

1F0000

64-Kword Block

127

128-Mbit

64-Mbit

01FFFF

010000

00FFFF

000000

64-Kword Block 64-Kword Block

32-Mbit

Word Wide (x16) M ode

Table 2. Chip Enable Truth Table

NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND.

V V V V V V V

IL IH IH

DEVICE

Enabled Disabled Disabled Disabled

Enabled

Enabled Disabled

Preliminary 7

28F128J3A, 28F640J3A, 28F320J3A

3.1 Read

Information can be read from any block, query, identifier codes, or status register i ndependent of

PEN

voltage.

the V Upon initial device power-up or after exit from reset/power-down mode, the device automatically

resets to read array mode. Otherwise, write the appropriate read m ode command (Read Array, Read Query , Read Identifier Codes, or Read St atus Register) to the CUI. Six control pins dictate the data flow in and out of the component: CE enabled (see Table 2, “Chip Enable Truth Table” on page 7), and OE# must be driven active to obtain data at the outputs. CE (see Table 2), select the memory device. OE# is the data output (DQ active, drives the selected memory data onto the I/O bus. WE# must be at V

When reading information in read array mode, the device defaults to asynchronous page mode. This mode provides high data transfer rate for memory subsystems. In this state, data is internally read and stored in a high-speed page buffer. A four words or eight bytes. Asynchronous word/byte mode is supported with no additional commands required.

3.2 Output Disable

, CE1, CE2, OE#, WE#, and RP#. The device must be

, CE1, and CE2 are the device selection controls and, when enabled

addresses data in the page buf fer. The page size is

2:0

–DQ15) control and, when

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ15 are placed in a high-impedance state.

3.3 Standby

CE0, CE1, and CE2 can disable the device (see Table 2) and place it in standby mode which substantially reduces device power consumption. DQ impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.

3.4 Reset/Power-Down

RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory , places output drivers in a high-impedance state, and

turns off numerous int ernal circu i ts. R P# mus t be held l o w for a mi n imum o f t required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.

During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of t reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time t

is required after RP# goes to logic-high (VIH) before another command can be written.

PHWL

–DQ15 outputs are placed in a high-

. Time t

PLPH

+ t

PLPH

PHRH

PHQV

until the

8 Preliminary

As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper i nitialization may not occur because the flash memory may be providi ng status information instead of array data. Intel allow proper initialization following a system reset thr ough the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.5 Read Query

The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, device geometry information, and Intel-specific extended query information.

3.6 Read Identifier Codes

The read identifier codes operation outputs the manufacturer code, device code and the block lock configuration codes for each block (see Figure 5 on page 10). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algo rithms. The block lock configuration codes identify locked and unlo cked bl ocks .

28F128J3A, 28F640J3A, 28F320J3A

Flash memories

3.7 Write

Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when V configuration.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command req uires the co mmand and add res s within the d evice.

The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed t o execute a command are latched on the rising edge of WE# or the first edge of CE

, CE1, or CE2 that disables the device (see Table 2). Standard

microprocessor write timings are used.

4.0 Command Definitions

When the V codes, or blocks are enabled. Placing V and lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Tab le 4 defines these commands.

voltage ≤ V

PEN

, only read operations from the status register, query, identifier

PENLK

PENH

PEN

on V

= V

PEN

, block erasure, program, and lock-bit

PENH

additionally enables block erase, program,

Preliminary 9

28F128J3A, 28F640J3A, 28F320J3A

Figure 5. Device Identifier Code Memory Map

Word

Address 7FFFFF

7F0003 7F0002

7F0000

7EFFFF

3FFFFF

3F0003 3F0002

3F0000

3EFFFF

1F0003 1F0002

1F0000

1EFFFF

01FFFF

010003 010002

010000

00FFFF

000004 000003 000002 000001 000000

A[23-1]: 128 Mbit

A[22-1]: 64 Mbit A[21-1]: 32 Mbit

Block 127

Reserved for Future

Implementation

Block 127 Lock Configuration

Reserved for Future

Implementation

(Blocks 64 through 126)

Block 63

Reserved for Future

Implementation

Block 63 Lock Configuration

Reserved for Future

Implementation

(Blocks 32 through 62)

Block 31

Reserved for Future

Implementation

Block 31 Lock Configuration

Reserved for Future

Implementation

(Blocks 2 through 30)

Block 1

Reserved for Future

Implementation

Block 1 Lock Configuration

Reserved for Future

Implementation

Block 0

Reserved for Future

Implementation

Block 0 Lock Configuration

Device Code

Manufacturer Code

128 Mbit

64 Mbit

32 Mbit

NOTE: A

is not used in either x8 or x16 modes when obtaining these identifier codes. Data is always given on the low byte in

x16 mode (upper byte contains 00h).

0606-06a

10 Preliminary

T a ble 3. Bus Operations

28F128J3A, 28F640J3A, 28F320J3A

Mode Notes RP# CE

Read Array 4,5,6 V

Enabled V

0,1,2

(1)

OE#

Output Disable VIH Enabled V Standby V Reset/Power-Down

Mode

Disabled X X X X High Z X

X X X X X High Z High Z

Read Identifier Codes VIH Enabled V

Read Query VIH Enabled V Read Status (WSM off) VIH Enabled V

Read Status (WSM on) VIH Enabled V

Write 6,10,11 V

Enabled V

NOTES:

1. See Table 2 for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.

3. DQ refers to DQ

4. Refer to DC Characteristics. When V

5. X can be V V

PENLK

6. In default mode, STS is V

or VIH for control and address pins, and V

and V

PENH

configuration algorithms. It is V programming inactive), program suspend mode, or reset/power-down mode.

7. High Z will be V

8. See Section 3.6 for read identifier code data.

if BYTE# is low and DQ0–DQ15 if BYTE# is high.

0–DQ7

PEN

voltages.

when the WSM is executing internal block erase, program, or lock-bit

when the WSM is not busy, in block erase suspend mode (with

with an external pull-up resistor.

9. See Section 4.2 for read query data.

10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V and VCC is within specification.

PENH

11.Refer to Table 4 for valid D

during a write operation.

≤ V

(2)

WE#

Address V

PEN

XX D XX High Z X

See

Figure 5

See

Table 7

X Note 8 High Z

X Note 9 High Z

XX D

, memory contents can be read, but not altered.

PENLK

or V

PENLK

PENH

for V

15–8

6–0

. See DC Characteristics for

PEN

(3)

OUT

= D

= High Z

OUT

STS

(default

mode)

High Z

PEN

(7)

Preliminary 11

28F128J3A, 28F640J3A, 28F320J3A

Data

(5,6)

(1)

Oper

(3)

Addr

(4)

Data

Table 4. Intel® StrataFlash™ Memory Command Set Definitions

Command

Scalable or

Basic

Command

(2)

Set

Bus

Cycles

Req’d.

Notes First Bus Cycle Second Bus Cycle

Oper

(3)

Addr

(4)

Read Array SCS/BCS 1 Write X FFH Read Identifier Codes SCS/BCS ≥ 2 7 Write X 90H Read IA ID Read Query SCS ≥ 2 Write X 98H Read QA QD Read Status Register SCS/BCS 2 8 Write X 70H Read X SRD Clear Status Register SCS/BCS 1 Write X 50H

Write to Buffer SCS/BCS > 2

9, 10,

Write BA E8H Write BA N

40H

Word/Byte Program SCS/BCS 2 12,13 Write X

Write PA PD

10H Block Erase SCS/BCS 2 11,12 Write BA 20H Write BA D0H Block Erase, Program

Suspend Block Erase, Program

Resume

SCS/BCS 1 12,14 Write X B0H

SCS/BCS 1 12 Write X D0H

Configuration SCS 2 Write X B8H Write X CC Set Block Lock-Bit SCS 2 Write X 60H Write BA 01H Clear Block Lock-Bits SC S 2 15 Write X 60H Write X D0H Protection Program 2 Write X C0H Write PA PD

(5,6)

NOTES:

1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.

2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set.

3. Bus operations are defined in Table 3.

4. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Figure 5 and Table 15. QA = Query database Address. PA = Address of m e mo ry location to be programmed. RCD = Data to be written to the read configuration register. This data is presented to the device on A other address inputs are ignored.

16-1

; all

5. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from status register. See Table 16 for a description of the status register bits. PD = Data to be programmed at location P A . Data is latched on the rising edge of WE#. CC = Configuration Code.

6. The upper byte of the data bus (DQ

7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock

) during command writes is a “Don’t Care” in x16 operation.

8–DQ15

codes. See Section 4.3 for read identifier code data.

8. If the WSM is running, only DQ impedance state.

is valid; DQ

and DQ6–DQ0 float, which places them in a high-

15–DQ8

9. After the Write to Buffer command is issued check the X SR to make sure a buffer is available for writing.

12 Preliminary

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