INTEL 28F320B3, 28F640B3 User Manual

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3 Volt Advanced Boot Block Flash Memory

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Product Features

Preliminary Datasheet

■ Flexible Smar tVoltage Technology

—2.7 V–3.6 V Read/Program/Erase —12 V V

■ 2.7 V or 1.65 V I/O Option

Fast Production Programming

—Reduces Overall System Power

■ High Performance

—2.7 V–3.6 V: 70 ns Max Access Time

■ Optimized Block Sizes

—Eight 8-KB Blocks for Data,Top or

Bottom Locations

—Up to One Hundred Twenty-Seven 64-

KB Blocks for Code

■ Block Locking

—V

-Level Control through WP#

■ Low Power Consumption

—9 mA Typical Read Current

■ Absolute Hardware-Protection

—V

= GND Option

—V

Lockout Voltage

■ Extended Temperature Operation

—–40 °C to +85 °C

■ Automated Program and Block Erase

—Status Reg isters

■ Intel

Flash Data Integrator Software

—Flash Memory Manager —System Interrupt Manager —Supports Parameter Storage, Streaming

Data (e.g., Voice)

■ Extended Cycling Capabilit y

—Minimum 100,000 Block Erase Cycles

Guaranteed

■ Automatic Power Savings Feature

—Typical I

■ Standard Surface Mount Packaging

after Bus Inactivity

CCS

—48-Ball CSP Packages —40- and 48-Lead TSOP Packages

■ Density and Footprint Upgradeable for

common package

—4-, 8-, 16-, 32- and 64-Mbit Densities

■ ETOX™ VII (0.18 µ) Flash Technology

—28F160/320/640B3xC —4-, 8-, 16-, and 32-Mbit also exist on

ETOX™ V (0.4µ) and/or ETOX ™ VI (0.25µ) Flash Technology

■ x8 not recommended for new designs

■ 4-Mbit density not recommended for new

designs

The 3 Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.18 µm technology, represents a feature-rich solution at overall lower system cost. The 3Volt Advanced Boot Block flash memory products in x16 will be available in 48-lead TSOP and 48-ball CSP packages. The x8 option of this product family will o nly be available in 40-lead TSOP and 48ball µBGA* packages. Additional information on this product family can be obtained by accessing Intel’s website at: http://www.intel.com/design/flash.

Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number: 290580-012

October 2000

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause

the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

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Contents

1.0 Introduction..................................................................................................................1

1.1 Product Overview..................................................................................................2

2.0 Product Description..................................................................................................3

2.1 Package Pinouts ...................................................................................................3

2.2 Block Organization ................................................................................................7

2.2.1 Parameter Blocks.....................................................................................7

2.2.2 Main Blocks..............................................................................................7

3.0 Principles of Operation............................................................................................7

3.1 Bus Operation .......................................................................................................7

3.1.1 Read.........................................................................................................8

3.1.2 Output Disable..........................................................................................8

3.1.3 Standby ....................................................................................................8

3.1.4 Deep Power-Down / Reset.......................................................................8

3.1.5 Write.........................................................................................................9

3.2 Modes of Operation...............................................................................................9

3.2.1 Read Array ...............................................................................................9

3.2.2 Read Identifier........................................................................................11

3.2.3 Read Status Register .............................................................................11

3.2.4 Program Mode....... ...... ....... ...... ...... ....... ...... ....................................... ....12

3.2.5 Erase Mode............................................................................................12

3.3 Block Locking ......................................................................................................14

3.3.1 WP# = V

3.3.2 WP# = V

3.4 V

3.5 Power Consumption............................................................................................15

3.6 Power-Up/Down Operation ............. ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... ....16

3.7 Power Supply Decoupling ...................................................................................17

Program and Erase Voltages.......................................................................15

3.4.1 V

3.5.1 Active Power ..........................................................................................16

3.5.2 Automatic Power Savings (APS)............................................................16

3.5.3 Standby Power.......................................................................................16

3.5.4 Deep Power-Down Mode .......................................................................16

3.6.1 RP# Connected to System Reset...........................................................17

3.6.2 V

for Block Locking ..................................................................14

for Block Unlocking ..............................................................15

= VIL for Complete Protection .........................................................15

, VPP and RP# Transitions...............................................................17

4.0 Electrical Specifications........................................................................................18

4.1 Absolute Maximum Ratings.................................................................................18

4.2 Operating Conditions...........................................................................................19

4.3 Capacitance ........................................................................................................19

4.4 DC Characteristics ................... ....... ...................................... ....... ...... ....... ...... ....20

4.5 AC Characteristics —Read Operations...............................................................23

4.6 AC Characteristics —Write Operations...............................................................27

4.7 Program and Erase Timings................................................................................31

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5.0 Reset Operations .....................................................................................................33

6.0 Ordering Information..............................................................................................34

7.0 Additional Information............. ...................................... ....................................... .36

Appendix A Write State Machine Current/Next States.................................................37

Appendix B Architecture Block Diagram... ........................................................................38

Appendix C Word-Wide Memory Map Diagrams.............................................................39

Appendix D Byte-Wide Memory Map Diagrams................................... ...........................45

Appendix E Program and Erase Flowcharts....................................................................48

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Revision History

Number Description

-001 Original version

VPP Program and Erase Voltages

maximum specification change from ±25 µA to ±50 µA

Ordering Information Additional Information

Program Flowchart

Program Suspend/Resume Flowchart

= 0 when in read identifier mode (Section 3.2.2)

absolute maximum specification = 3.7 V (Section 4.1)

CCQ

PPW PPE

test conditions corrected (Section 4.4)

and VILSpecification change (Section 4.4) test conditions clarification (Section 4.4)

-002

-003

-004

-005

-006

-007

Section 3.4, Updated Figure 9: Updated Figure 10: Updated Figure 16: I

PPR

Program and Erase Suspend Latency specification change Updated Appendix A: Updated Figure, Appendix D: Minor wording changes

Combined byte-wide specification (previously 290605) with this document Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V) Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4) Improved several DC characteristics (Section 4.4) Improved several AC characteristics (Sections 4.5 and 4.6) Combined 2.7 V and 1.8 V DC characteristics (Section 4.4) Added 5 V V Removed 120 ns and 150 ns speed offerings Moved Moved Updated figure Appendix B, Updated figure Appendix C, Moved Program and Erase Flowcharts to Appendix E Updated Updated Minor text edits throughout

Added 32-Mbit density Added 98H as a reserved command (Table 4) A

1–A20

Status register clarification for SR3 (Table 7)

and V

Combined I Combined I Max Parameter Block Erase Time (t Max Main Block Erase Time (t Erase suspend time @ 12 V (t (Section 4.7)

Ordering Information

Write State Machine Current/Next States Table updated (Appendix A) Program Suspend/Resume Flowchart updated (Appendix F) Erase Suspend/Resume Flowchart updated (Appendix F) Text clarifications throughout

µBGA package diagrams corrected (Figures 3 and 4) I

PPD

32-Mbit ordering information corrected (Section 6) µBGA package top side mark information added (Section 6)

CCS

Added Command Sequence Error Note (Table 7) Datasheet renamed from

Memory Family.

Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes

Corrected RP# pin description in Table 2, Corrected typographical error fixed in

Automated Block Erase Flowchart

, added

Erase Suspend/Resume Flowchart AC Waveform: Program and Erase Operations

Ordering Information

(included 8 M and 4 M information)

Architecture Block Diagram

read specification (Section 3.4)

from Appendix to Section 6.0; updated information

from Appendix to Section 7.0

Access Time vs. Capacitive Load

Architecture Block Diagram

and I

into one specification (Section 4.4)

CCW

into one specification (Section 4.4)

CCE

updated (Section 6.0)

WHQV2/tEHQV2 WHQV3/tEHQV3 WHRH2/tEHRH2

) reduced to 5 sec (Section 4.7) ) changed to 5 µs typical and 20 µs maximum

) reduced to 4 sec (Section 4.7)

Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash

3 Volt Advanced Boot Block Pin Descriptions

Ordering Information

(added program to table)

(updated notes)

(Block info. in words not bytes)

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Number Description

-008 4-Mbit packaging and addressing information corrected throughout document

-009 Corrected 4-Mbit memory addressing tables in Appendices D and E

-010

-011

-012

Max I

V Added 64-Mbit density and faster speed offerings

Removed access time vs. capacitance load curve Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product

offering. Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit device. Minor text edits throughout document.

changed to 25 µA

CCD

Max on 32 M (28F320B3) changed to 3.3 V

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1.0 Introduction

This datasheet contains the specifications for the 3 Volt Advanced Boot Block flash memory family, which is optimized for low power, portable systems. This family of products features

1.65 V–2.5 V or 2.7 V–3.6 V I/Os and a low V program, and erase operations. In addition this family is capable of fast programming at 12 V. Throughout this document, the term “2.7 V” refers to the full voltage range 2.7 V–3.6 V (except where noted otherwise) and “V overview of the flash memory family including applications, pinouts and pin descriptions. Section

3.0 describes the memory organization and operation for these products. Sections 4.0 and 5.0 contain the operating specifications. Finally, Sections 6.0 and 7.0 provide ordering and other reference information.

The 3 Volt Advanced Boot Block flash memory features:

• Enhanced blocking for easy segmentation of code and data or additional design flexibility

• Program Suspend to Read command

operating range of 2.7 V–3.6 V for read,

CC/VPP

= 12 V” refers to 12 V ±5%. Section 1.0 and 2.0 provide an

• V

input of 1.65 V–2.5 V on all I/Os. See Figures 1 through 4 for pinout diagrams and

CCQ

location

CCQ

• Maximum program and erase time specification for improved data storage.

Table 1. 3 Volt Advanced Boot Block Feature Summary

(2)

Feature

Read Voltage 2.7 V– 3.6 V

I/O Voltage 1.65 V–2.5 V or 2.7 V– 3.6 V Section 4.2, 4.4

CCQ

Program/Erase Voltage 2.7 V– 3.6 V or 11.4 V– 12.6 V Section 4.2, 4.4

Bus Width 8 bit 16 bit Table 3 Speed 70 ns, 80 ns, 90 ns, 100 ns, 110 ns Section 4.5

Memory Arrangement

Blocking (top or bottom)

Locking Operating Tempe rature Extended: –40 °C to +85 °C Section 4.2, 4.4

Program/Erase Cycling 100,000 cycles Section 4.2, 4.4

Packages

NOTES:

1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP.

2. 4-Mbit density not available in µBGA* CSP. Max is 3.3 V on 0.25µm 32-Mbit devices.

3. V

4. 4- and 64-Mbit densities not available on 48-Ball VF BGA.

28F004B3

512 Kbit x 8 (4 Mbit)

1024 Kbit x 8 (8 Mbit),

2048 Kbit x 8 (16 Mbit)

One hundred twenty-seven 64-Kbyte main blocks (64 Mbit)

40-lead TSOP

48-Ball µBGA* CSP

, 28F008B3,

28F016B3

Eight 8-Kbyte parameter blocks and

Seven 64-Kbyte blocks (4 Mbit) or

Fifteen 64-Kbyte blocks (8 Mbit) or

Thirty-one 64-Kbyte main blocks (16 Mbit)

Sixty-three 64-Kbyte main blocks (32 Mbit)

WP# locks/unlocks parameter blocks

All other blocks protected using V

(1)

(2)

28F400B3 28F160B3, 28F320B3

256 Kbit x 16 (4 Mbit),

512 Kbit x 16 (8 Mbit), 1024 Kbit x 16 (16 Mbit), 2048 Kbit x 16 (32 Mbit),

4096 Kbit x 16 (64 Mbit)

48-Ball µBGA CSP

48-Ball VF BGA

, 28F800B3,

28F640B3

48-Lead TSOP,

(3)

(2)

(4)

Reference

Section 4.2, Section 4.4

Section 2.2

Section 2.2 Appendix C

Section 3.3 Table 8

Figure 3, Figure 4

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1.1 Product Overview

Intel provides the most flexible voltage soluti on in the flash industry, providing three discrete voltage supply pins: V erase operation. All 3 Volt Advanced Boot Block flash memory products provide program/erase capability at 2.7 V or 12 V (for fast production programming) and read with V many designs read from the flash memory a larg e percentage of the time, 2.7V V provide substantial power savings.

The 3 Volt Advanced Boot Block flash memory products ar e available in either x8 or x16 packages in the following densities: (see Section 6.0, “Ordering Information” on page 34 for availability.)

• 4-Mbit (4,194,304-bit) flash memory organized as 256 Kwords of 16 bits each or 512 Kbytes

of 8-bits each

• 8-Mbit (8,388,608-bit) flash memory organized as 512 Kwo rds of 16 b its each or 1 024 Kbytes

of 8-bits each

• 16-Mbit (16,777,216-bit) flash memory organized as 1024 Kwords of 16 bits each or

2048 Kbytes of 8-bits each

• 32-Mbit (33,554,432-bit) flash memory organized as 2048 Kwords of 16 bits each

for read o peration, V

for output swing, and VPP for program and

CCQ

at 2.7 V. Since

operation can

• 64-Mbit (67,108,864-bit) flash memory organized as 4096 Kwords of 16 bits each

The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section

3.3, “Block Locking” on page 14 for detai ls).

The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby un-burdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status.

The 3 Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered following the completion of a read cycle (approximately 300 ns later).

The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see

Section 3.6, “Power-Up/Down Operation” on page 16). Section 3.0, “Principles of Operation” on page 7 gives detailed explanation of the different modes

of operation. Complete current and voltage specifications can be found in Section 4.4, “DC

Characteristics” on page 20. Refer to Section 4.5, “AC Characteristics —Read Operations” on page 23 for read, program and erase performance specifications.

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2.0 Product Description

This section explains device pin description and package pinouts.

2.1 Package Pinouts

The 3 Volt Advanced Boot Block flash memory is available in 40-lead TSOP (x8, Figure 1), 48-lead TSOP (x16, Fig u r e 2 ) and 48- bal l µBGA(x8 and x16, Figure 3 and Figure 4, respectively) and 48-ball VF BGA (x16, Figure 4) packages. In all figures, pin changes necessary for density upgrades have been circled.

Figure 1. 40-Lead TSOP Package for x8 Configurations

GND A

DQ DQ DQ DQ V

CCQ

NC DQ DQ DQ DQ OE# GND CE# A

16 M

8 M

7 6 5 4

3 2 1 0

4 M

WE# RP# V

WP# A

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

Advanced Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

NOTES:

1. 40-Lead TSOP available for 8- and 16-Mbit densities only.

2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.

0580_01

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Figure 2. 48-Lead TSOP Package for x16 Configurations

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Advanced Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

64 M 32 M

16 M

WE# RP# V

WP# A

NOTE: Lower densities will have NC on the upper address pins. For example, an 16-Mbit device will have NC

on Pins 9 and 10.

Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)

13254768

16M

WP#

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

CCQ

GND DQ DQ DQ DQ DQ DQ DQ DQ V

DQ DQ DQ DQ DQ DQ DQ DQ OE# GND CE# A

15 7 14 6 13 5 12 4

11 3 10 2 9 1 8 0

0580_02

NOTES:

CCQ

GND D

WE#

NC D

RP#

CE#

NC D

GND

OE#

0580_04

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A 16-Mbit device.

is the upgrade address for the

2. 4-Mbit density not available in µBGA* CSP.

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Figure 4. x16 48-Ball Very Thin Profile Pitch BGA and µBGA* Chip Size Package (Top View,

Ball Down)

13254768

16M

WP#

NOTES:

CCQ

GND D

WE#

64M

RP#

32M

CE#

GND

OE#

0580_03

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A 16-Mbit device. A device.

is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit

is the upgrade address for the

2. 4-Mbit density not available in µBGA CSP.

T able 2, “3 Volt Advanced Boot Block Pin Description s” on page 6 details the usage of each device

pin.

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Table 2. 3 Volt Advanced Boot Block Pin Descriptions

Symbol Type Name and Function

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or

erase cycle. 28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20], 28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19], 28F320B3: A[0-20], 28F640B3: A[0-21]

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, i dentifier and status register data. The dat a pins float to tri-state when the chip is de-selected or the outputs are disabled.

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state when the chip is de-selected. Not included on x8 products.

CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels.

OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation. OE# is active low.

WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse.

RESET/DEEP POWER-DOWN: Uses two voltage levels (V mode.

, VIH) to control reset/deep power-down

When RP# is at logic low, the device is in reset/deep power-down mode , which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (I

When RP# is at logic high, the device is in standard operation. When RP# transitions from logiclow to logic-high, the device defaults to the read array mode.

WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks. When WP# is at logic low, the lockable blocks are locked, preventing program and erase

operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. See Section 3.3 for details on write protection.

OUTPUT V

is regulated to 2.7 V–2.85 V, V

operation (see Section 4.4 This input may be tied directly to V

: Enables all outputs to be driven to 1.8 V – 2.5 V while the VCC is at 2.7 V–3.3 V. If the

)

can be driven at 1.65 V–2.5 V to achieve lowest power

CCQ

(2.7 V–3.6 V).

DEVICE POWER SUPPLY: 2.7 V–3.6 V PROGRAM/ERASE POWER SUPPLY: Supplies power for program and erase operations. VPP may

be the same as V manufacturing, 11.4V–12.6 V may be supplied to V

11.4 V–12.6 V to V cycles on the parameter blocks.

Section 3.4 for details).

< V

PPLK

commands.

(2.7 V–3.6 V) for single supply voltage operation. For fast programming at

can only be done for a maximum of 1000 cycles on the main blocks and 2500

may be connected to 12 V for a total of 80 hours maximum (see

VPP

. This pin cannot be left floating. Applying

protects memory contents against inadvertent or unintended program and erase

INPUT

INPUT/

OUTPUT

INPUT/

OUTPUT

0–A21

DQ DQ

–DQ

–

8 15

CE# INPUT

OE# INPUT

WE# INPUT

RP# INPUT

WP# INPUT

CCQ

INPUT

GND GROUND: For all internal circuitry. All ground inputs must be connected. NC NO CONNECT: Pin may be driven or left floating.

CCD

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2.2 Block Organization

The 3 Volt Advanced Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 100,000 times. For the add ress locatio ns of each block , see the m emory maps in

Appendix C.

2.2.1 Parameter Blocks

The 3 Volt Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM). By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each device contains eight parameter blocks of 8-Kbytes/4-Kwords (8192 bytes/4,096 words) each.

2.2.2 Main Blocks

After the parameter blocks, the remainder of the array is divided into equal size main blocks (65,536 bytes/32,768 words) for data or code storage. The 4-Mbit device contains seven main blocks; 8-Mbit device contains fifteen main blocks; 16-Mbit flash has thirty-one main blocks; 32-Mbit has sixty-three main blocks; 64-Mbit has one hundred twenty-seven main blocks.

3.0 Principles of Operation

Flash memory combines EEPROM functionality with in-circuit electrical program and erase capability. The 3 Volt Advan ced Boot Block flash memory family utilizes a Command User Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power su ppl ie s duri ng erasu re and programming.

When V Array, Read Status Register, Clear Status Register and Read Identifier. The device provides standard EEPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI. All functions associated with altering memory contents, namely program and erase, are accessible via the CUI. The internal Write State Machine (WSM) completely automates program and erase operations while the CUI signals the start of an operation and the status register reports status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.

3.1 Bus Operation

3 Volt Advanced Boot Block flash memory devices read, program and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3.

< V

, the device will only execute the following commands successfully: Read

PPLK

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Table 3. Bus Operations

Mode Note RP# CE# OE# WE# DQ

Read (Array, Status, or Identifier) 2–4 V Output Disable 2 V Standby 2 V Reset 2, 7 V Write 2, 5–7 V

NOTES:

1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].

2. X must be V

DC Characteristics

3. See

4. Manufacturer and device codes may also be accessed in read identifier mode (A

5. Refe r to Table 6 for valid D

6. To program or erase the lockable blocks, hold WP# at V

7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

(1)

, VIH for control pins and addresses.

for V

PPLK

during a write operation.

3.1.1 Read

The flash memory has four read modes available: read array, read identifier, read status and read query. These modes are accessible independent of the V command must be issued to the CUI to enter the co rres ponding mode. Upon initial device powerup or after exit from reset, the device automatically defaults to read array mode.

CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output control and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at V

. Figure 7 illustrates a read cycle.

, V

IH IH IH

PP1

, V

0–7

X X X High Z High Z

, V

PP3

, V

PP2

X X High Z High Z

voltages.

PP4

voltage. The appropriate Read Mode

OUT

High Z High Z

= 0). See Table 5.

1–A21

OUT

8–15

3.1.2 Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a high-impedance state.

3.1.3 Standby

Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete.

3.1.4 Deep Power-Down / Reset

From read mode, RP# at VIL for time t impedance state, and turns off all internal circuits. After r eturn from reset, a time t until the initial read access outputs are valid. A delay (t reset before a write can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. This case is shown in

Figure 9A.

8 3UHOLPLQDU\

deselects the memory, places output drivers in a high-

PLPH

PHQV

PHWL

or t

) is required after return from

PHEL

is required

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

If RP# is taken low for time t aborted and the memory contents at th e abo rted location (for a program) or block (for an erase) ar e no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: When RP# goes low, the device shuts down the operation in progress, a process which takes time t array mode (if RP# h as go ne hi gh dur ing t low after t time t discussed in the previous paragraph. However, in this case, these delays are referenced to the end of t

PLRH

As with any automated device, it is important to assert RP # during system reset. When the system comes out of reset, processor expects to read from the flash memory. Automated flash memories provide status information when read during program or block erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel proper CPU initialization following a sy stem reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.1.5 Write

A write takes place when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control flash operations. The CUI does not occupy an addr essable m emor y loca tio n. The ad dress and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 8 illustrates a program and erase operation. The available commands are shown in Table 6, and

Appendix A provides detailed information on moving between the different modes of op eration

using CUI commands.

during a program or erase operation, the operation will be

PLPH

to complete. After this time t

PLRH

, Figure 9C). In both cases, after returning from an aborted operation, the relevant

PLRH

PHQV

or t

PHWL/tPHEL

must be waited before a read or write operation is initiated, as

rather than when RP# goes high.

, the part will either reset to read

, Figure 9B) or enter reset mode (if RP# is still logic

PLRH

Flash memories allow

There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to V

3.2 Modes of Operation

The flash memory has four read modes and two write modes. The read modes are read array, read identifier, read status and read query (see Appendix B). The write modes are program and block erase. Three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are reached using the commands summarized in Table 4. A comprehensive chart showing the state transitions is in

Appendix A.

3.2.1 Rea d A rray

When RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI commands.

for t

or an appropriate suspend command).

PLRH

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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

When the device is in read array mode, four control signals control data output:

• WE# must be logic high (V

• CE# must be logic low (V

• OE# must be logic low (V

• RP# must be logic high (V

)

In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place.

Table 4. Command Codes and Descriptions

Code Device Mode Description

00, 01, 60, 2F, C0, 98

FF Read Array Places the device in read array mode, such that array data will be output on the data pins.

40 Program Set-Up

20 Erase Set-Up

90 Read Identifier

Invalid/

Reserved

Alternate

Program Set-Up

Erase Confirm

Program / Erase

Resume

Program / Erase

Suspend

Read Status

Clear Status

Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions.

This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.2.4.

(See 40H/Program Set-Up) Prepares the CUI for the Erase Confirm command. If the next command is not an Erase

Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,” (b) place the device into the read status register mode, and (c) wait for another command. See

Section 3.2.5.

If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches, and begin erasing the block indicated on the address pins. During erase, the device will only respond to the Read Status Register and Erase Suspend comm ands. The device will output status register data when CE# or OE# is toggled.

If a program or erase operation was previously suspended, this command will resume that operation

Issuing this command will begin to suspend the currently executing program/erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit (SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if it is driven to V

This command places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a program or erase operation has been initiated. See Section 3.2.3.

The WSM can set the block lock status (SR.1) , V erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this command clears those bits to “0.”

Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (A address inputs must be 0). See Section Section 3.2.2.

. See Section 3.2.4.1 and Section 3.2.4.1.

status (SR.3), program status (SR.4), and

= 0 for manufacturer, A0 = 1 for device, all other

NOTE: See Appendix A for mode transition information.

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3.2.2 Rea d Ident if ier

To read the manufacturer and device codes, the device must be in read identifier mode, which can be reached by writing the Read Identifier command (90H). Once in read identifier mode, A

outputs the manufacturer’s identification code and A

Table 5) Note: A

Table 5. Read Identifier Table

Size Mfr. ID

1–A21

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

= 0

= 1 outputs the device identifier (see

= 0. To return to read array mode, write the Read Array command (FFH).

Device Identifier

-T

(Top Boot)

-B

(Bottom Boot)

28F004B3 28F400B3 8894H 8895H 28F008B3 28F800B3 8892H 8893H 28F016B3 D0H D1H 28F160B3 28F320B3 8896H 8897H 28F640B3 8898H 8899H

0089H

3.2.3 Read Status Register

The device status register indicates when a program or erase operation is complete and the success or failure of that operation. To read the status register issue the Read Status Register (70H) command to the CUI. This causes all subsequent read operations to output data from the status register until another command is written to the CUI. To return to reading from the array, issue the Read Array (FFH) command.

The status register bits are output on DQ Read Status Register command.

The contents of the status register are latched on the falling edge of OE# or CE#. This prevents possible bus errors which might occur if status register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation.

D4H D5H

D2H D3H

8890H 8891H

–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a

When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether or not the WSM was successful in performing the desired operation (see

Table 7 on page 14).

3.2.3.1 Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before

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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. Note, again, that the Read Array command must be issued before data can be read from the memory array.

3.2.4 Program Mode

Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. Programming the

memory results in specific bits within an address location being changed to a “0.” If the user attempts to program “1”s, the memory cell contents do not change and no error occurs.

The status register indicates programming status: while the progr am sequence executes, status bit 7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then V command. If SR.1 is set, a program operation was attempted on a locked block and the operation was aborted.

was not within acceptable limits, and the WSM did not execute the program

The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode.

3.2.4.1 Suspending and Resuming Program

The Program Suspend halts the in-progres s program operation to read data from another location of memory . Once the programming pr ocess starts, writing the Program Suspend comm and to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues t o output status reg ister data after the Program Su spend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to “1”). t

WHRH1/tEHRH1

A Read Array command can now be written to the CUI to read data from bloc ks other than that which is suspended. The only other valid commands while program is suspended, are Read Status Register, Read Identifier, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the program process and status register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status register data when read (see Appendix E for Program Suspend and Resume Flowchart). V suspend mode. RP# must also remain at V

must remain at the same VPP level used for program while in program

IH.

3.2.5 Erase Mode

To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute a sequence of internally-timed events to program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”

specify the program suspend latency.

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