INTEL 28F160S3, 28F320S3 User Manual

28F160S3E

ADVANCE INFORMATION

WORD-WIDE

FlashFile™ MEMORY FAMILY 28F160S3, 28F320S3

Includes Extended Temperature Specifications

nTwo 32-Byte Write Buffers

¾2.7 μs per Byte Effective

Programming Time

nLow Voltage Operation

¾2.7V or 3.3V VCC

¾2.7V, 3.3V or 5V VPP

n100 ns Read Access Time (16 Mbit)

110 ns Read Access Time (32 Mbit)

nHigh-Density Symmetrically-Blocked Architecture

¾32 64-Kbyte Erase Blocks (16 Mbit)

¾64 64-Kbyte Erase Blocks (32 Mbit)

nSystem Performance Enhancements ¾ STS Status Output

nIndustry-Standard Packaging

¾μBGA* package, SSOP, and

TSOP (16 Mbit)

¾μBGA* package and SSOP (32 Mbit)

nCross-Compatible Command Support

¾Intel Standard Command Set

¾Common Flash Interface (CFI)

¾Scaleable Command Set (SCS)

n100,000 Block Erase Cycles

nEnhanced Data Protection Features

¾Absolute Protection with VPP = GND

¾Flexible Block Locking

¾Block Erase/Program Lockout during Power Transitions

nConfigurable x8 or x16 I/O

nAutomation Suspend Options

¾Program Suspend to Read

¾Block Erase Suspend to Program

¾Block Erase Suspend to Read

nETOX™ V Nonvolatile Flash Technology

Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, non-volatile, read/write storage solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection with VPP at GND, selective block locking, and program/erase lockout during power transitions. These alternatives give designers ultimate control of their code security needs.

This family of products is manufactured on Intel’s 0.4 mm ETOX™ V process technology. It comes in the industry-standard 56-lead SSOP and mBGA packages. In addition, the 16-Mb device is available in the industry-standard 56-lead TSOP package.

June 1997

Order Number: 290608-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F160S3 and 28F320S3 may contain design defects or errors known as errata. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com

COPYRIGHT © INTEL CORPORATION, 1997

CG-041493

*Third-party brands and names are the property of their respective owners.

E	28F160S3, 28F320S3

CONTENTS

	PAGE
1.0 INTRODUCTION .............................................		5
1.1	New Features...............................................	5
1.2	Product Overview.........................................	5
1.3	Pinout and Pin Description ...........................	6
2.0 PRINCIPLES OF OPERATION .....................		10
2.1	Data Protection ..........................................	11
3.0 BUS OPERATION .........................................		12
3.1	Read ..........................................................	12
3.2	Output Disable ...........................................	12
3.3	Standby......................................................	12
3.4	Deep Power-Down .....................................	12
3.5	Read Query Operation ...............................	12
3.6	Read Identifier Codes Operation ................	13
3.7	Write ..........................................................	13
4.0 COMMAND DEFINITIONS ............................		13
4.1 Read Array Command................................		16
4.2 Read Query Mode Command.....................		17
4.2.1 Query Structure Output .......................		17
4.2.2 Query Structure Overview ...................		19
4.2.3 Block Status Register ..........................		20
4.2.4 CFI Query Identification String.............		21
4.2.5 System Interface Information...............		22
4.2.6 Device Geometry Definition .................		23
4.2.7 Intel-Specific Extended Query Table ...		24
4.3	Read Identifier Codes Command ...............	25
4.4	Read Status Register Command................	25
4.5	Clear Status Register Command................	26
4.6	Block Erase Command ..............................	26
4.7	Full Chip Erase Command .........................	26
4.8	Write to Buffer Command...........................	27

		PAGE
4.9	Byte/Word Write Command........................	27
4.10 STS Configuration Command...................		28
4.11 Block Erase Suspend Command..............		28
4.12 Program Suspend Command ...................		28
4.13 Set Block Lock-Bit Commands .................		29
4.14 Clear Block Lock-Bits Command ..............		29
5.0 DESIGN CONSIDERATIONS ........................		39
5.1	Three-Line Output Control..........................	39
5.2	STS and WSM Polling ................................	39
5.3	Power Supply Decoupling ..........................	39
5.4	VPP Trace on Printed Circuit Boards...........	39
5.5	VCC, VPP, RP# Transitions..........................	39
5.6	Power-Up/Down Protection ........................	39
6.0 ELECTRICAL SPECIFICATIONS..................		40
6.1	Absolute Maximum Ratings........................	40
6.2	Operating Conditions..................................	40
6.2.1 Capacitance.........................................		41
6.2.2 AC Input/Output Test Conditions .........		41
6.2.3 DC Characteristics...............................		42
6.2.4 AC Characteristics - Read-Only
	Operations..........................................	44
6.2.5 AC Characteristics - Write Operations .46
6.2.6 Reset Operations.................................		48
6.2.7 Erase, Program, And Lock-Bit
	Configuration Performance.................	49
APPENDIX A: Device Nomenclature and
Ordering Information ..................................		51
APPENDIX B: Additional Information ...............		52

ADVANCE INFORMATION	3

28F160S3, 28F320S3

Number

-001

E

REVISION HISTORY

Description

Original version

4	ADVANCE INFORMATION

E

1.0INTRODUCTION

This datasheet contains 16and 32-Mbit WordWide FlashFileTM memory (28F160S3 and 28F320S3) specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications for extended temperature product offerings.

1.1New Features

The Word-Wide FlashFile memory family maintains basic compatibility with Intel’s 28F016SA and 28F016SV. Key enhancements include:

∙Common Flash Interface (CFI) Support

∙Scaleable Command Set (SCS) Support

∙Low Voltage Technology

∙Enhanced Suspend Capabilities

They share a compatible Status Register, basic software commands, and pinout. These similarities enable a clean migration from the 28F016SA or 28F016SV. When upgrading, it is important to note the following differences:

∙Because of new feature and density options, the devices have different manufacturer and device identifier codes. This allows for software optimization.

∙New software commands.

∙To take advantage of low voltage on the 28F160S3 and 28F320S3, allow VPP connection to VCC. The 28F160S3 and 28F320S3 do not support a 12V VPP option.

1.2Product Overview

The Word-Wide FlashFile memory family provides density upgrades with pinout compatibility for the 16and 32-Mbit densities. They are highperformance memories arranged as 1 Mword and 2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of 8 bits. This data is grouped in thirty-two and sixtyfour 64-Kbyte blocks that can be erased, locked and unlocked in-system. Figure 1 shows the block diagram, and Figure 5 illustrates the memory organization.

ADVANCE INFORMATION

28F160S3, 28F320S3

This family of products are optimized for fast factory programming and low power designs. Specifically designed for 3V systems, the 28F160S3 and 28F320S3 support read operations at 2.7V–3.6V Vcc with block erase and program operations at 2.7V–3.6V and 5V VPP. High programming performance is achieved through highly-optimized write buffers. A 5V VPP option is available for even faster factory programming. For a simple low power design, VCC and VPP can be tied to 2.7V. Additionally, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK.

Internal VPP detection circuitry automatically configures the device for optimized write operations.

A Common Flash Interface (CFI) permits OEMspecified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forwardand backward-compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor and internal device operation. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 64-Kbyte blocks typically within tWHQV2/EHQV2 independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block.

Data is programmed in byte, word or page increments. Program suspend mode enables the system to read data or execute code from any other flash memory array location.

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28F160S3, 28F320S3

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The device incorporates two Write Buffers of 32 bytes (16 words) to allow optimum-performance data programming. This feature can improve system program performance by up to four times over non-buffer programming.

Individual block locking uses a combination of block lock-bits to lock and unlock blocks. Block lock-bits gate block erase, full chip erase, program and write to buffer operations. Lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) set and clear lock-bits.

The Status Register and the STS pin in RY/BY# mode indicate whether or not the device is busy executing an operation or ready for a new command. Polling the Status Register, system software retrieves WSM feedback. STS in RY/BY# mode gives an additional indicator of WSM activity by providing a hardware status signal. Like the Status Register, RY/BY#-low indicates that the WSM is performing a block erase, program, or lockbit operation. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and program is inactive), program is suspended, or the device is in deep power-down mode.

The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching).

The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode with address A0 selecting between the low byte and high byte. BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest order address. Address A0 is not used in 16bit mode.

When one of the CEX# pins (CE0#, CE1#) and RP# pins are at VCC, the component enters a CMOS standby mode. Driving RP# to GND enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the Status Register. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized.

1.3Pinout and Pin Description

The 16-Mbit device is available in the 56-lead TSOP, 56-lead SSOP and μBGA packages. The 32Mb device is available in the 56-lead SSOP and µBGA packages. The pinouts are shown in Figures 2, 3 and 4.

	DQ0 - DQ15
Output Buffer	Input Buffer

			Query				I/O Logic	VCC
								BYTE#
		Output Multiplexer
			Identifier	Data Register	Write Buffer	Command		CE#
			Register					WE#
						User
								OE#
						Interface
			Status					RP#
								WP#
			Register
				Multiplexer
			Data
			Comparator
16-Mbit: A0- A20	Input Buffer	Y-Decoder	Y-Gating					STS
						Write State
32-Mbit: A0 - A21							Program/Erase	VPP
						Machine
							Voltage Switch
	Address		16-Mbit: Thirty-two
			32-Mbit: Sixty-four					VCC
	Latch	X-Decoder
			64-Kbyte Blocks					GND
	Address
	Counter

Figure 1. Block Diagram

6	ADVANCE INFORMATION

E			28F160S3, 28F320S3
			Table 1. Pin Descriptions
	Sym	Type	Name and Function
	A0–A21	INPUT	ADDRESS INPUTS: Address inputs for read and write operations are internally
			latched during a write cycle. A0 selects high or low byte when operating in x8 mode.
			In x16 mode, A0 is not used; input buffer is off.
			16-Mbit → A0–A20 32-Mbit → A0–A21
	DQ0–	INPUT/	DATA INPUTS/OUTPUTS: Inputs data and commands during CUI write cycles;
	DQ15	OUTPUT	outputs data during memory array, Status Register, query and identifier code read
			cycles. Data pins float to high-impedance when the chip is deselected or outputs
			are disabled. Data is internally latched during a write cycle.
	CE0#,	INPUT	CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
	CE1#		sense amplifiers. With CE0# or CE1# high, the device is deselected and power
			consumption reduces to standby levels. Both CE0# and CE1# must be low to select
			the device. Device selection occurs with the latter falling edge of CE0# or CE1#. The
			first rising edge of CE0# or CE1# disables the device.
	RP#	INPUT	RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
			which provides data protection during system power transitions, puts the device in
			deep power-down mode, and resets internal automation. RP#-high enables normal
			operation. Exit from deep power-down sets the device to read array mode.
	OE#	INPUT	OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
	WE#	INPUT	WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
			are latched on the rising edge of the WE# pulse.
	STS	OPEN	STATUS: Indicates the status of the internal state machine. When configured in
		DRAIN	level mode (default), it acts as a RY/BY# pin. For this and alternate configurations
		OUTPUT	of the STATUS pin, see the Configuration command. Tie STS to VCC with a pull-up
			resistor.
	WP#	INPUT	WRITE PROTECT: Master control for block locking. When VIL, locked blocks
			cannot be erased or programmed, and block lock-bits cannot be set or cleared.
	BYTE#	INPUT	BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).
	VPP	SUPPLY	BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
			Necessary voltage to perform block erase, program, and lock-bit configuration
			operations. Do not float any power pins.
	VCC	SUPPLY	DEVICE POWER SUPPLY: Do not float any power pins. Do not attempt block
			erase, program, or block-lock configuration with invalid VCC values.
	GND	SUPPLY	GROUND: Do not float any ground pins.
	NC		NO CONNECT: Lead is not internally connected; it may be driven or floated.

ADVANCE INFORMATION	7

28F160S3, 28F320S3

E

28F016SA	28F160S3
28F016SV	28F160S5

3/5#	NC			1
CE1# CE1#				2
NC	NC			3
A20	A20			4
A19	A19			5
A18	A18			6
A17	A17			7
A16	A16			8
VCC	VCC			9
A15	A15			10
A14	A14			11
A13	A13			12
A12	A12			13
CE0#	CE0#			14
VPP	VPP			15
RP#	RP#			16
A11	A11			17
A10	A10			18
A9	A9			19
A8	A8			20
GND	GND			21
A7	A7			22
A6	A6			23
A5	A5			24
A4	A4			25
A3	A3			26
A2	A2			27
A1	A1			28

56-LEAD TSOP

STANDARD PINOUT

14 mm x 20 mm TOP VIEW

			28F160S3		28F016SA
			28F160S5		28F016SV
56			WP#		WP#
55			WE#		WE#
54			OE#		OE#
53			STS		RY/BY#
52			DQ15		DQ15
51			DQ7		DQ7
50			DQ14		DQ14
49			DQ6		DQ6
48			GND		GND
47			DQ13		DQ13
46			DQ5		DQ5
45			DQ12		DQ12
44			DQ4		DQ4
43			VCC		VCC
42			GND		GND
41			DQ11		DQ11
40			DQ3		DQ3
39			DQ10		DQ10
38			DQ2		DQ2
37			VCC		VCC
36			DQ9		DQ9
35			DQ1		DQ1
34			DQ8		DQ8
33			DQ0		DQ0
32			A0		A0
31			BYTE#		BYTE#
30			NC		NC
29			NC		NC

Highlights pinout changes.

Figure 2. TSOP 56-Lead Pinout

8	ADVANCE INFORMATION

E	28F160S3, 28F320S3

Figure 3. SSOP 56-Lead Pinout

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E

	GND	A10	VPP	CE0	A14	VCC
A4	A7	A9	A11	A12	A15	A17	A19
A5	A6	A8	RP#	A13	A16	A21	A20
A2	A1	A3			A18	CE1	NC
NC	NC BYTE#				DQ7	WP#	WE#

A0 DQ8 DQ1 DQ3 DQ12 DQ6 DQ15 OE# DQ0 DQ9 DQ2 DQ11 DQ4 DQ13 DQ14 STS VCC DQ10 GND VCC DQ5 GND

	VCC	A14	CE0	VPP A10 GND
A19	A17	A15	A12	A11	A9	A7	A4
A20	A21	A16	A13	RP#	A8	A6	A5
NC	CE1	A18			A3	A1	A2
WE#	WP# DQ7				BYTE# NC		NC
OE# DQ15 DQ6 DQ12 DQ3					DQ1 DQ8		A0
STSDQ14 DQ13 DQ4 DQ11 DQ2 DQ9							DQ0
	GND DQ5 VCC GNDDQ10 VCC

Bottom View

This is the view of the package as surface mounted on the board. Note that the signals are mirror imaged.

NOTES:

1.Figures are not drawn to scale.

2.Address A21 is not included in the 28F160S3.

3.More information on µBGA* packages is available by contacting your Intel/Distribution sales office.

Figure 4. μBGA* Package Pinout

2.0PRINCIPLES OF OPERATION

The word-wide memories include an on-chip Write State Machine (WSM) to manage block erase, program, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, programming, lock-bit configuration, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from deep power-down mode (see Bus Operations), the

10

device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations.

Read Array, Status Register, query, and identifier codes can be accessed through the CUI independent of the VPP voltage. Proper programming voltage on VPP enables successful block erasure, program, and lock-bit configuration. All functions associated with altering memory contents—block erase, program, lock-bit configuration—are accessed via the CUI and verified through the Status Register.

ADVANCE INFORMATION

E

Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM that controls the block erase, programming, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, identifier codes, or Status Register data.

Interface software that initiates and polls progress of block erase, programming, and lockbit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location.

28F160S3, 28F320S3

2.1Data Protection

Depending on the application, the system designer may choose to make the VPP power supply switchable or hardwired to VPPH1/2. The device supports either design practice, and encourages optimization of the processormemory interface.

When VPP ≤ VPPLK, memory contents cannot be altered. When high voltage is applied to VPP, the two-step block erase, program, or lock-bit configuration command sequences provide protection from unwanted operations. All write functions are disabled when VCC voltage is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration.

Figure 5. Memory Map

ADVANCE INFORMATION	11

28F160S3, 28F320S3

3.0BUS OPERATION

The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1Read

Block information, query information, identifier codes and Status Registers can be read independent of the VPP voltage.

The first task is to place the device into the desired read mode by writing the appropriate read-mode command (Read Array, Query, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Control pins dictate the data flow in and out of the component. CE0#, CE1# and OE# must be driven active to obtain data at the outputs. CE0# and CE1# are the device selection controls, and, when both are active, enable the selected memory device. OE# is the data output (DQ0– DQ15) control: When active it drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH. Figure 17 illustrates a read cycle.

3.2Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ15 are placed in a high-impedance state.

3.3Standby

CE0# or CE1# at a logic-high level (VIH) places the device in standby mode, substantially

reducing device power consumption. DQ0–DQ15 (or DQ0– DQ7 in x8 mode) outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, programming, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes.

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3.4Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read mode, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RP# must be held low for time tPLPH. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the Status Register is set to 80H.

During block erase, programming, or lock-bit configuration modes, RP#-low will abort the operation. STS in RY/BY# mode remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after programming or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.

It is important in any automated system to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, programming, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.5Read Query Operation

The read query operation outputs block status, Common Flash Interface (CFI) ID string, system interface, device geometry, and Intel-specific extended query information.

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3.6Read Identifier Codes Operation

The read-identifier codes operation outputs the manufacturer code, device code, and block lock configuration codes for each block configuration (see Figure 6). Using the manufacturer and device codes, the system software can automatically match the device with its proper algorithms. The block-lock configuration codes identify each block’s lock-bit setting.

Figure 6. Device Identifier Code Memory Map

ADVANCE INFORMATION

28F160S3, 28F320S3

3.7Write

Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the Status Register. Additionally, when VPP = VPPH1/2, block erasure, programming, and lock-bit configuration can also be performed.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Write command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and address within the block to be locked. The Clear Block Lock-Bits command requires the command and an address within the device.

The CUI does not occupy an addressable memory location. It is written when WE#, CE0#, and CE1# are active and OE# = VIH. The address and data needed to execute a command are latched on the rising edge of WE# or CEX# (CE0#, CE1#), whichever goes high first. Standard microprocessor write timings are used. Figure 18 illustrates a write operation.

4.0COMMAND DEFINITIONS

VPP voltage ≤ VPPLK enables read operations from the Status Register, identifier codes, or memory blocks. Placing VPPH1/2 on VPP enables successful block erase, programming, and lockbit configuration operations.

Device operations are selected by writing specific commands into the CUI. and Table 3 define these commands.

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Table 2. Bus Operations

Mode

Notes

RP#

CE0#

CE1#

OE#(11)

WE#(11)

Address

VPP

DQ(8)

STS(3)

Read

1,2

VIH

VIL

VIL

VIL

VIH

X

X

DOUT

X

Output Disable

VIH

VIL

VIL

VIH

VIH

X

X

High Z

X

Standby

VIH

VIL

VIH

X

X

X

X

High Z

X

VIH

VIL

VIH

VIH

Reset/Power-

10

VIL

X

X

X

X

X

X

High Z

High Z(9)

Down Mode

Read Identifier

4

VIH

VIL

VIL

VIL

VIH

See

X

DOUT

High Z(9)

Codes

Figure 6

Read Query

5

VIH

VIL

VIL

VIL

VIH

See Table 6

X

DOUT

High Z(9)

Write

3,6,7

VIH

VIL

VIL

VIH

VIL

X

VPPH1/2

DIN

X

NOTES:

1.Refer to Table 19. When VPP ≤ VPPLK, memory contents can be read, but not altered.

2.X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See Table 19, for VPPLK and VPPH1/2 voltages.

3.STS in level RY/BY# mode (default) is VOL when the WSM is executing internal block erase, programming, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or deep power-down mode.

4.See Section 4.3 for read identifier code data.

5.See Section 4.2 for read query data.

6.Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2 (see Section 6.2).

7.Refer to Table 3 for valid DIN during a write operation.

8.DQ refers to DQ0–7 if BYTE# is low and DQ0–15 if BYTE# is high.

9.High Z will be VOH with an external pull-up resistor.

10.RP# at GND ± 0.2V ensures the lowest deep power-down current.

11.OE# = VIL and WE# = VIL concurrently is an undefined state and should not be attempted.

14	ADVANCE INFORMATION

E								28F160S3, 28F320S3
Table 3. Word-Wide FlashFile™ Memory Command Set Definitions (13)
Command	Scaleable		Bus	Notes	First Bus Cycle			Second Bus Cycle
	or Basic		Cycles
	Command		Req'd
	Set(14)
					Oper(1)	Addr(2)	Data(3,4)	Oper(1)		Addr(2)	Data(3,4)
Read Array	SCS/BCS		1		Write	X	FFH
Read Identifier Codes	SCS/BCS		³2	5	Write	X	90H	Read		IA	ID
Read Query	SCS		³ 2		Write	X	98H	Read		QA	QD
Read Status Register	SCS/BCS		2		Write	X	70H	Read		X	SRD
Clear Status Register	SCS/BCS		1		Write	X	50H
Write to Buffer	SCS		> 2	8, 9, 10	Write	BA	E8H	Write		BA	N
Word/Byte Program	SCS/BCS		2	6,7	Write	X	40H	Write		PA	PD
							or
							10H
Block Erase	SCS/BCS		2	6,10	Write	X	20H	Write		BA	D0H
Block Erase, Word/Byte	SCS/BCS		1	6	Write	X	B0H
Program Suspend
Block Erase, Word/Byte	SCS/BCS		1	6	Write	X	D0H
Program Resume
STS pin Configuration	SCS		2		Write	X	B8H	Write		X	CC
Set Block Lock-Bit	SCS		2	11	Write	X	60H	Write		BA	01H
Clear Block Lock-Bits	SCS		2	12	Write	X	60H	Write		X	D0H
Full Chip Erase	SCS		2	10	Write	X	30H	Write		X	D0H

ADVANCE INFORMATION	15

28F160S3, 28F320S3		E
NOTES:
1.	Bus operations are defined in Table 2.
2.	X = Any valid address within the device.
	BA = Address within the block being erased or locked.
	IA = Identifier Code Address: see Table 12.
	QA = Query database Address.
	PA = Address of memory location to be programmed.
3.	ID = Data read from Query database.
	SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits.
	PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
	CC = Configuration Code. (See Table 14.)
4.	The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation.
5.	Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See
	Section 4.3 for read identifier code data.
6.	If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at VIH in order to perform block erase, program and
	suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is VIL
	will fail.

7.Either 40H or 10H are recognized by the WSM as the byte/word program setup.

8.After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.

9.N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1 byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the buffer boundary causes unexpected results and should be avoided.

10.The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued. Confirm also reactivates suspended operations.

11.A block lock-bit can be set only while WP# is VIH.

12.WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.

13.Commands other than those shown above are reserved for future use and should not be used.

14.The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.

16	ADVANCE INFORMATION