INTEL 28F800C3, 28F160C3, 28F320C3, 28F640C3 User Manual
Intel£Advanced+ Boot Block Flash
Memory (C3)
28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16)
Datasheet
Product Features
■ Flexible SmartVoltage Technology
—2.7 V– 3.6 V Read/Program/Erase
—12 V for Fast Production Programming
■ 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
—Reduces Overall System Power
■ High Performance
—2.7 V– 3.6 V: 70 ns Max Access Time
■ Optimized Architecture for Code Plus
Data Storage
—Eight 4 Kword Blocks, Top or Bottom
Parameter Boot
—Up to One Hundred-Twenty-Seven 32
Kword Blocks
—Fast Program Suspend Capability
—Fast Erase Suspend Capability
■ Flexible Block Locking
—Lock/Unlock Any Block
—Full Protection on Power-Up
—WP# Pin for Hardware Block Protection
■ Low Power Consumption
—9 mA Typical Read
—7 A Typical Standby with Automatic
Power Savings Feature (APS)
■ Extended Temperature Operation
—–40°C to+85 °C
■ 128-bit Protection Register
—64 bit Unique Device Identifier
—64 bit User Programmable OTP Cells
■ Extended Cycling Capability
—Minimum 100,000 Block Erase Cycles
■ Software
—Intel
®
Flash Data Integrator (FDI)
—Supports Top or Bottom Boot Storage,
Streaming Data (e.g., voice)
—Intel Basic Command Set
—Common Flash Interface (CFI)
■ Standard Surface Mount Packaging
—48-Ball µBGA*/VFBGA
—64-Ball Easy BGA Packages
—48-Lead TSOP Package
■ ETOX™ VIII (0.13 µm) Flash
Technology
—16, 32 Mbit
■ ETOX™ VII (0.18 µm)Flash Technology
—16, 32, 64 Mbit
■ ETOX™ VI (0.25 µm) Flash Technology
—8, 16 and 32 Mbit
The Intel®Advanced+ Book Block Flash Memory (C3) device, manufactured on Intel’s latest
0.13 µm and 0.18 µm technologies, represents a feature-rich solution for low-power applications.
The C3 device incorporates low-voltage capability (3 V read, program, and erase) with highspeed, low-power operation. Flexible block locking allows any block to be independently locked
or unlocked. Add to this the Intel
effective, flexible, monolithic code plus data storage solution. Intel
Memory (C3) products will be available in 48-lead TSOP, 48-ball CSP, and 64-ball Easy BGA
packages. Additional information on this product family can be obtained by accessing the Intel
®
Flash Data Integrator (FDI) software and you have a cost-
®
Advanced+ Boot Block Flash
®
Flash website: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
Order Number: 290645-017
October 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2003
*Third-party brands and names are the property of their respective owners.
2 Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................7
1.1 Document Purpose ...............................................................................................................7
1.2 Nomenclature .......................................................................................................................7
1.3 Conventions..........................................................................................................................7
2.0 Device Description ........................................................................................................................8
2.1 Product Overview .................................................................................................................8
2.2 Ballout Diagram ....................................................................................................................8
2.3 Signal Descriptions .............................................................................................................13
2.4 Block Diagram ....................................................................................................................14
2.5 Memory Map.......................................................................................................................15
3.0 Device Operations.......................................................................................................................17
3.1 Bus Operations ...................................................................................................................17
3.1.1 Read ......................................................................................................................17
3.1.2 Write ......................................................................................................................17
3.1.3 Output Disable .......................................................................................................17
3.1.4 Standby..................................................................................................................18
3.1.5 Reset .....................................................................................................................18
4.0 Modes of Operation.....................................................................................................................19
4.1 Read Mode .........................................................................................................................19
4.1.1 Read Array.............................................................................................................19
4.1.2 Read Identifier .......................................................................................................19
4.1.3 CFI Query ..............................................................................................................20
4.1.4 Read Status Register.............................................................................................20
4.1.4.1 Clear Status Register.............................................................................21
4.2 Program Mode ....................................................................................................................21
4.2.1 12-Volt Production Programming...........................................................................21
4.2.2 Suspending and Resuming Program.....................................................................22
4.3 Erase Mode ........................................................................................................................22
4.3.1 Suspending and Resuming Erase .........................................................................23
5.0 Security Modes ............................................................................................................................27
5.1 Flexible Block Locking ........................................................................................................27
5.1.1 Locking Operation..................................................................................................28
5.1.1.1 Locked State ..........................................................................................28
5.1.1.2 Unlocked State.......................................................................................28
5.1.1.3 Lock-Down State....................................................................................28
5.2 Reading Block-Lock Status.................................................................................................28
5.3 Locking Operations during Erase Suspend ........................................................................29
5.4 Status Register Error Checking ..........................................................................................29
5.5 128-Bit Protection Register.................................................................................................29
5.5.1 Reading the Protection Register............................................................................30
5.5.2 Programming the Protection Register....................................................................30
5.5.3 Locking the Protection Register.............................................................................30
5.6 V
Program and Erase Voltages ......................................................................................30
PP
Datasheet 3
Contents
5.6.1 Program Protection................................................................................................31
6.0 Power Consumption....................................................................................................................32
6.1 Active Power (Program/Erase/Read)..................................................................................32
6.2 Automatic Power Savings (APS) ........................................................................................32
6.3 Standby Power ................................................................................................................... 32
6.4 Deep Power-Down Mode.................................................................................................... 32
6.5 Power and Reset Considerations .......................................................................................33
6.5.1 Power-Up/Down Characteristics............................................................................33
6.5.2 RP# Connected to System Reset ..........................................................................33
6.5.3 VCC, VPP and RP# Transitions ............................................................................33
6.6 Power Supply Decoupling................................................................................................... 34
7.0 Thermal and DC Characteristics ................................................................................................ 34
7.1 Absolute Maximum Ratings ................................................................................................ 34
7.2 Operating Conditions..........................................................................................................35
7.3 DC Current Characteristics................................................................................................. 35
7.4 DC Voltage Characteristics................................................................................................. 38
8.0 AC Characteristics ......................................................................................................................39
8.1 AC Read Characteristics ....................................................................................................39
8.2 AC Write Characteristics.....................................................................................................43
8.3 Erase and Program Timings ............................................................................................... 47
8.4 Reset Specifications ...........................................................................................................48
8.5 AC I/O Test Conditions.......................................................................................................49
8.6 Device Capacitance............................................................................................................49
Appendix A Write State Machine States.............................................................................................50
Appendix B Flow Charts ......................................................................................................................52
Appendix C Common Flash Interface.................................................................................................58
Appendix D Mechanical Specifications..............................................................................................64
Appendix E Additional Information ....................................................................................................67
Appendix F Ordering Information .......................................................................................................68
4 Datasheet
Revision History
Contents
Date of
Revision
05/12/98 -001 Original version
07/21/98 -002
10/03/98 -003
12/04/98 -004
12/31/98 -005 Removed all references to x8 configurations
02/24/99 -006 Removed reference to 40-Lead TSOP from front page
06/10/99 -007
03/20/00 -008
04/24/00 -009
10/12/00 -010
7/20/01 -011
10/02/01 -012 Added specifications for 0.13 micron product offerings throughout document
2/05/02 -013
Version Description
48-Lead TSOP package diagram change
µBGA package diagrams change
32-Mbit ordering information change (Section 6)
CFI Query Structure Output Table Change (Table C2)
CFI Primary-Vendor Specific Extended Query Table Change for Optional
Features and Command Support change (Table C8)
Protection Register Address Change
test conditions clarification (Section 4.3)
I
PPD
µBGA package top side mark information clarification (Section 6)
Byte-Wide Protection Register Address change
Specification change (Section 4.3)
V
IH
Maximum Specification change (Section 4.3)
V
IL
test conditions clarification (Section 4.3)
I
CCS
Added Command Sequence Error Note (Table 7)
Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash
Memory Family.
Added t
BHWH/tBHEH
Programming the Protection Register clarification (Section 3.4.2)
Added Easy BGA package (Section 1.2)
Removed 1.8 V I/O references
Locking Operations Flowchart changed (Appendix B)
Added t
WHGL
CFI Primary Vendor-Specific Extended Query changed (Appendix C)
Max I
Table 10, added note indicating V
Added specifications for 0.18 micron product offerings throughout document
Added 64-Mbit density
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the
faster product offering.
Changed VccMax=3.3V reference to indicate that the affected product is the
0.25µm 32Mbit device.
Minor text edits throughout document.
Added 1.8v I/O operation documentation where applicable
Added TSOP PCN ‘Pin-1’ indicator information
Changed references in 8 x 8 BGA pinout diagrams from ‘GND’ to ‘Vssq’
Added ‘Vssq’ to Pin Descriptions Information
Removed 0.4 µm references in DC characteristics table
Corrected 64Mb package Ordering Information from 48-uBGA to 48-VFBGA
Corrected‘bottom’parameterblocksizestoon8Mbdeviceto8x4KWords
Minor text edits throughout document
Corrected Iccw / Ippw / Icces /Ippes values.
Added mechanicals for 16Mb and 64Mb
Minor text edits throughout document.
changedto25µA
CCD
and t
(Section 4.6)
QVBL
(Section 4.6)
Max = 3.3 V for 32-Mbit device
CC
Datasheet 5
Contents
Date of
Revision
4/05/02 -014
3/06/03 -016 Complete technical update.
10/03 -017 Corrected information in the Device Geometry Details table, address 0x34.
Version Description
Updated 64Mb product offerings.
Updated 16Mb product offerings.
Revised and corrected DC Characteristics Table.
Added mechanicals for Easy BGA.
Minor text edits throughout document.
6 Datasheet
1.0 Introduction
1.1 Document Purpose
This datasheet contains the specifications for the Intel®Advanced+ Boot Block Flash Memory
(C3) device family. These flash memories add features such as instant block locking and protection
registers that can be used to enhance the security of systems.
1.2 Nomenclature
0x Hexadecimal prefix
0b Binary prefix
Byte 8 bits
Word 16 bits
Kword 1024 words
Mword 1,048,576 words
Kb 1024 bits
KB 1024 bytes
Mb 1,048,576 bits
MB 1,048,576 bytes
APS Automatic Power Savings
CUI Command User Interface
OTP One Time Programmable
PR Protection Register
PRD Protection Register Data
PLR Protection Lock Register
RFU Reserved for Future Use
SR Status Register
SRD Status Register Data
WSM Write State Machine
Intel£Advanced+ Boot Block Flash Memory (C3)
1.3 Conventions
The terms pin and signal are often used interchangeably to refer to the external signal connections
on the package. (ball is the term used for CSP).
Group Membership Brackets: Square brackets will be used to designate group membership or to
define a group of signals with similar function (i.e. A[21:1], SR[4:1])
Set: When referring to registers, the term set means the bit is a logical 1.
Clear: When referring to registers, the term clear means the bit is a logical 0.
Block: A group of bits (or words) that erase simultaneously with one block erase instruction.
Main Block: A block that contains 32 Kwords.
Parameter Block: A block that contains 4 Kwords.
Datasheet 7
Intel£Advanced+ Boot Block Flash Memory (C3)
2.0 Device Description
This section provides an overview of the Intel®Advanced+ Boot Block Flash Memory (C3) device
features, packaging, signal naming, and device architecture.
2.1 Product Overview
The C3 device provides high-performance asynchronous reads in package-compatible densities
with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data
storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of
the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase
and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC and VPP can be tied
together for a simple, ultra-low-power design. In addition to I/O voltage flexibility, the dedicated
VPP input provides complete data protection when V
The device features a 128-bit protection register enabling security techniques and data protection
schemes through a combination of factory-programmed and user-programmable OTP data
registers. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. Additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
PP
≤ V
PPLK
.
A command User Interface(CUI) serves as the interface between the system processor and internal
operation of the device. A valid command sequence issued to the CUI initiates device automation.
An internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS), standby
mode, and deep power-down mode. The device automatically enters APS mode following read
cycle completion. Standby mode begins when the system deselects the flash memory by
deasserting CE#. The deep power-down mode begins when RP# is asserted, which deselects the
memory and places the outputs in a high-impedance state, producing ultra-low power savings.
Combined, these three power-savings features significantly enhanced power consumption
flexibility.
2.2 Ballout Diagram
The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball µBGA, and Easy BGA
packages. (Refer to Figure1onpage9, Figure 3 on page 11,andFigure 4 on page 12,
respectively.)
8 Datasheet
Figure 1. 48-Lead TSOP Package
Intel£Advanced+ Boot Block Flash Memory (C3)
64 M
32 M
16 M
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
21
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
Advanced+ Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
V
CCQ
GND
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
CC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A
0
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
NOTES:
1. For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on
Pins 9 and 10.
Datasheet 9
Intel£Advanced+ Boot Block Flash Memory (C3)
Figure 2. Mark for Pin-1 indicator on 48-Lead 8Mb, 16Mb and 32Mb TSOP
Current Mark:
New Mark:
Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel
£
Advanced and Advanced + Boot Block
48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the
white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in
package size, materials, functionality, customer handling, or manufacturability. Product will
continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes
shown in Table 1 .
Table 1. 48-Lead TSOP
Extended 64 Mbit Extended 32 Mbit Extended 16 Mbit Extended 8 Mbit
TE28F640C3TC80
TE28F640C3BC80
TE28F320C3TD70
TE28F320C3BD70
TE28F320C3TC70
TE28F320C3BC70
TE28F320C3TC90
TE28F320C3BC90
TE28F320C3TA100
TE28F320C3BA100
TE28F320C3TA110
TE28F320C3BA110
TE28F160C3TD70
TE28F160C3BD70
TE28F160C3TC80
TE28F160C3BC80
TE28F160C3TA90
TE28F160C3BA90
TE28F160C3TA110
TE28F160C3BA110
TE28F800C3TA90
TE28F800C3BA90
TE28F800C3TA110
TE28F800C3BA110
10 Datasheet
Intel£Advanced+ Boot Block Flash Memory (C3)
Figure 3. 48-Ball µBGA* and 48-Ball Very Fine Pitch BGA (VF BGA) Chip Size Package
(TopView,BallDown)
1,2,3
13254768
16M
A
B
A13
A14
A11
A10
A8
WE#
VPP
RP#
WP#
A18
A19
A17
A7
A5
A4
A2
32M64M
C
D
E
A15
A16
V
CCQ
A12
D14
D15
A9
D5
D6
A21
D11
D12
A20
D2
D3
A6
D8
D9
A3
CE#
D0
A1
A0
GND
F
GND D7 D13 D4 VCC D10 D1 OE#
NOTES:
1. Shaded connections indicate the upgrade address connections. Routing is not recommended in this area.
2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
3. Unused address balls are not populated.
Datasheet 11
Intel£Advanced+ Boot Block Flash Memory (C3)
Figure 4. 64-Ball Easy BGA Package
1 2 3 4 5 6 7 8
A
A1A6A18VPPVCCGND A10A
B
A2A17A
C
A3A7WP# WE# DU A
D
A4A5DU
E
DQ
8DQ1DQ9DQ3DQ12DQ6
F
CE# DQ
G
A
0VSSQDQ2DQ4DQ13DQ15
H
(2)
A
22
NOTES:
1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
2. Unused address balls are not populated.
(1)
RP# DU A
19
DU DU DU A
0DQ10DQ11DQ5DQ14
OE# V
CCQVCCVSSQDQ7VCCQ
Top View
-BallSide
(1)
20
(1)
21
A11A
A12A
8A9
DU DU
DU DU
SSQ
V
1,2
A
15
14
13
16
DU
8 7 6 5 4 3 2 1
A
A
15A10
GND VCCVPPA18A6A
B
A14A11A
(1)
20
DU RP# A
(1)
19
C
A13A12A
(1)
DU WE# W P# A7A
21
D
A9A8DU
DU DU DU A5A
E
DU DU DQ
6DQ12DQ3DQ9DQ1DQ8
F
DU DU DQ14DQ5DQ11DQ
10
G
SSQ
V
A
16
D15D13DQ4DQ2V
H
DU V
CCQD7VSSQVCCVCCQ
Bottom View - Ball Side
A17A
DQ
0
SSQA0
OE# A
1
2
3
4
CE#
22
(2)
12 Datasheet
Intel£Advanced+ Boot Block Flash Memory (C3)
2.3 Signal Descriptions
Tabl e 2 lists the active signals used and provides a brief description of each.
Table 2. Signal Descriptions
Symbol Type Name and Function
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
A[MAX:0] INPUT
DQ[15:0]
CE# INPUT
OE# INPUT
RP# INPUT
WE# INPUT
WP# INPUT
VPP
VCC POWER
VCCQ POWER
GND POWER
DU -
NC -
INPUT/
OUTPUT
INPUT/
POWER
8 Mbit: AMAX= A18
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense
amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption
to standby levels.
OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a
Read operation.
RESET/DEEP POWER-DOWN: Active-low input.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to
High-Z, resets the Write State Machine, and minimizes current levels (I
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
logic-high, the device resets all blocks to locked and defaults to the read array mode.
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
therisingedgeoftheWE#pulse.
WRITE PROTECT: Active-low input.
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot
be unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are
now locked and can be unlocked and locked through software. After WP# goes low, any blocks
previously marked lock-down revert to the lock-down state.
See Section 5.0, “Security Modes” on page 27 for details on block locking.
PROGRAM/ERASE POWER SUPPLY: Operates as an input at logic levels to control complete device
protection. Supplies power for accelerated Program and Erase operations in 12 V
cannot be left floating.
Lower VPP
Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can
drop as low as 1.65 V to allow for resistor or diode drop from the system supply.
Apply VPP to 12 V
to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the
boot blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 5.6 for
details on VPP voltage configurations.
DEVICE CORE POWER SUPPLY: Supplies power for device operations.
OUTPUT POWER SUPPLY: Output-driven source voltage. This ball can be tied directly to V
operating within V
GROUND: For all internal circuitry. All ground inputs must be connected.
DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
NO CONNECT: Pin must be left floating.
≤ VPPLK to protect all contents against Program and Erase commands.
± 5% for faster program and erase in a production environment. Applying 12 V ± 5%
range.
CC
CCD
).
± 5% range. This pin
CC
if
Datasheet 13
Intel£Advanced+ Boot Block Flash Memory (C3)
2.4 Block Diagram
V
CCQ
Power
Reduction
Control
A[MAX:MIN]
Input B uff er
Address
Latch
Address
Counter
Y-Decoder
X-Decoder
Output Buffer
Output
Multiplexer
Y-G ating/ Sensing
4-KWord
Paramet er B lock
DQ0-DQ
Comparat or
4-KWord
Paramet er B lock
Identifier
Register
Stat us
Register
Dat a
32- KWor d
Main Block
15
Input Buffer
Data
Re gist er
Command
User
Interface
Write State
Machine
32- KWor d
Main Block
I/O Logic
Program /Eras e
Voltage Switch
CE#
WE#
OE#
RP#
WP#
V
GND
V
PP
CC
14 Datasheet
2.5 Memory Map
The C3 device is asymmetrically blocked, which enables system code and data integration within a
single flash device. The bulk of the array is divided into 32 Kword main blocks that can store code
or data, and 4 Kword boot blocks to facilitate storage of boot code or for frequently changing small
parameters. See Table 3, “Top Boot Memory Map” on page 15 and Table 4, “Bottom Boot Memory
Map” on page 16 for details.
Table 3. Top Boot Memory Map
Size
Blk
(KW)
422
421
420
419
418
417
4 16 79000-79FFF
4 15 78000-78FFF
32 14 70000-77FFF
32 13 68000-6FFFF
32 12 60000-67FFF
32 11 58000-5FFFF
... ... ...
32 2 10000-17FFF
32 1 8000-0FFFF
32 0 0000-07FFF
8-Mbit
Memory
Addressing
(HEX)
7F000-
7FFFF
7E000-
7EFFF
7D0007DFFF
7C0007CFFF
7B000-
7BFFF
7A000-
7AFFF
Size
(KW)
4 38 FF000-FFFFF 470
4 37 FE000-FEFFF 469
4 36 FD000-FDFFF 468
4 35 FC000-FCFFF 467
4 34 FB000-FBFFF 466
4 33 FA000-FAFFF 465
4 32 F9000-F9FFF 464
4 31 F8000-F8FFF 463
32 30 F0000-F7FFF 32 62
32 29 E8000-EFFFF 32 61
32 28 E0000-E7FFF 32 60
32 27 D8000-DFFFF 32 59
... ... ... ... ... ... ... ... ...
32 2 10000-17FFF 32 2 10000-17FFF 32 2 10000-17FFF
32 1 08000-0FFFF 32 1 08000-0FFFF 32 1 08000-0FFFF
32 0 00000-07FFF 32 0 00000-07FFF 32 0 00000-07FFF
Blk
16-Mbit
Memory
Addressing
(HEX)
Intel£Advanced+ Boot Block Flash Memory (C3)
Size
(KW)
Blk
32-Mbit
Memory
Addressing
(HEX)
1FF000-
1FFFFF
1FE000-
1FEFFF
1FD000-
1FDFFF
1FC000-
1FCFFF
1FB000-
1FBFFF
1FA000-
1FAFFF
1F90001F9FFF
1F80001F8FFF
1F00001F7FFF
1E8000-
1EFFFF
1E0000-
1E7FFF
1D8000-
1DFFFF
Size
(KW)
4 134 3FF000-3FFFFF
4 133 3FE000-3FEFFF
4 132 3FD000-3FDFFF
4 131 3FC000-3FCFFF
4 130 3FB000-3FBFFF
4 129 3FA000-3FAFFF
4 128 3F9000-3F9FFF
4 127 3F8000-3F8FFF
32 126 3F0000-3F7FFF
32 125 3E8000-3EFFFF
32 124 3E0000-3E7FFF
32 123 3D8000-3DFFFF
Blk
64-Mbit Memory
Addressing
(HEX)
Datasheet 15
Intel£Advanced+ Boot Block Flash Memory (C3)
Table 4. Bottom Boot Memory Map
Size
Blk
(KW)
32 22 78000-7FFFF
32 21 70000-77FFF
32 20 68000-6FFFF
32 19 60000-67FFF
... ... ...
32 10 18000-1FFFF
32 9 10000-17FFF
32 8 08000-0FFFF
4 7 07000-07FFF
4 6 06000-06FFF
4 5 05000-05FFF
4 4 04000-04FFF
4 3 03000-03FFF
4 2 02000-02FFF
4 1 01000-01FFF
4 0 00000-00FFF
8-Mbit
Memory
Addressing
(HEX)
Size
Blk
(KW)
32 38 F8000-FFFFF 32 70 1F8000-1FFFFF 32 134 3F8000-3FFFFF
32 37 F0000-F7FFF 32 69 1F0000-1F7FFF 32 133 3F0000-3F7FFF
32 36 E8000-EFFFF 32 68 1E8000-1EFFFF 32 132 3E8000-3EFFFF
32 35 E0000-E7FFF 32 67 1E0000-1E7FFF 32 131 3E0000-3E7FFF
... ... ... ... ... ... . ... ...
32 10 18000-1FFFF 32 10 18000-1FFFF 32 10 18000-1FFFF
32 9 10000-17FFF 32 9 10000-17FFF 32 9 10000-17FFF
32 8 08000-0FFFF 32 8 08000-0FFFF 32 8 08000-0FFFF
4 7 07000-07FFF 4 7 07000-07FFF 4 7 07000-07FFF
4 6 06000-06FFF 4 6 06000-06FFF 4 6 06000-06FFF
4 5 05000-05FFF 4 5 05000-05FFF 4 5 05000-05FFF
4 4 04000-04FFF 4 4 04000-04FFF 4 4 04000-04FFF
4 3 03000-03FFF 4 3 03000-03FFF 4 3 03000-03FFF
4 2 02000-02FFF 4 2 02000-02FFF 4 2 02000-02FFF
4 1 01000-01FFF 4 1 01000-01FFF 4 1 01000-01FFF
4 0 00000-00FFF 4 0 00000-00FFF 4 0 00000-00FFF
16-Mbit
Memory
Addressing
(HEX)
Size
(KW)
Blk
32-Mbit
Memory
Addressing
(HEX)
Size
(KW)
Blk
64-Mbit Memory
Addressing
(HEX)
16 Datasheet
3.0 Device Operations
The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations.
The CUI allows for 100% CMOS
programming.
The internal WSM completely automates Program and Erase operations while the CUI signals the
start of an operation and the status register reports device status. The CUI handles the WE#
interface to the data and address latches, as well as system status requests during WSM operation.
3.1 Bus Operations
The C3 device performs read, program, and erase operations in-system via the local CPU or
microcontroller. Four control pins (CE#, OE#, WE#, and RP#) manage the data flow in and out of
the flash device. Table 5 on page 17 summarizes these bus operations.
Table 5. Bus Operations
Intel£Advanced+ Boot Block Flash Memory (C3)
-level control inputs and fixed power supplies during erasure and
3.1.1 Read
When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted.
CE# is the device selection control; when active low, it enables the flash memory device. OE# is
the data output control; when low, data is output on DQ[15:0]. See Figure 8, “Read Operation
Wav ef orm” on page 42.
3.1.2 Write
A write cycle occurs when both CE# and WE# are low; RP# and OE# are high. Commands are
issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory
location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever
occurs first. See Figure 9, “Write Operations Waveform” on page 47.
Mode RP# CE# OE# WE# DQ[15:0]
Read V
Write V
Output Disable V
Standby V
Reset V
NOTE: X = Don’t Care (V
IL
or VIH)
IH
IH
IH
IH
IL
V
IL
V
IL
V
IL
V
IH
XXXHigh-Z
V
IL
V
IH
V
IH
X X High-Z
V
IH
V
IL
V
IH
D
OUT
D
High-Z
IN
3.1.3 Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. DQ[15:0] are placed in a
-impedance state.
high
Datasheet 17
Intel£Advanced+ Boot Block Flash Memory (C3)
3.1.4 Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during a Program or Erase operation, the device continues to consume active power
until the Program or Erase operation is complete.
3.1.5 Reset
From read mode, RP# at VILfor time t
impedance state, and turns off all internal circuits. After return from reset, a time t
until the initial read-access outputs are valid. A delay (t
reset before a write cycle can be initiated. After this wake
deselects the memory, places output drivers in a high-
PLPH
PHQV
PHWL
or t
) is required after return from
PHEL
-up interval, normal operation is restored.
is required
The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See
Figure 10, “Reset Operations Waveforms” on page 48.
If RP# is taken low for time t
during a Program or Erase operation, the operation will be
PLPH
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process which takes time
to complete.
t
PLRH
2. After time t
enter reset mode (if RP# is deasserted after t
, the part will either reset to read-array mode (if RP# is asserted during t
PLRH
). See Figure 10, “Reset Operations Waveforms”
PLRH
PLRH
)or
on page 48.
In both cases, after returning from an aborted operation, the relevant time t
PHQV
or t
PHWL/tPHEL
must be observed before a Read or Write operation is initiated, as discussed in the previous
paragraph. However, in this case, these delays are referenced to the end of t
rather than when
PLRH
RP# goes high.
As with any automated device, it is important to assert RP# during a system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the
flash memory may be providing status information instead of array data. Intel
®
Flash memories
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
18 Datasheet
4.0 Modes of Operation
4.1 Read Mode
The flash memory has four read modes (read array, read identifier, read status, and CFI query), and
two write modes (program and erase). Three additional modes (erase suspend to program, erase
suspend to read, and program suspend to read) are available only during suspended operations.
Table 7, “Command Bus Operations” on page 24 and Table 8, “Command Codes and
Descriptions”onpage25summarize the commands used to reach these modes. Appendix A,
“Write State Machine States” on page 50 is a comprehensive chart showing the state transitions.
4.1.1 Read Array
When RP# transitions from VIL(reset) to VIH, the device defaults to read-array mode and will
respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
When the device is in read array mode, four control signals control data output.
• WE# must be logic high (V
• CE# must be logic low (V
• OE# must be logic low (V
• RP#mustbelogichigh(V
)
IH
)
IL
)
IL
)
IH
Intel£Advanced+ Boot Block Flash Memory (C3)
In addition, the address of the desired location must be applied to the address pins. If the device is
not in read-array mode, as would be the case after a Program or Erase operation, the Read Array
command (0xFF) must be issued to the CUI before array reads can occur.
4.1.2 Read Identifier
The read-identifier mode outputs three types of information: the manufacturer/device identifier, the
block locking status, and the protection register. The device is switched to this mode by issuing the
Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 6
retrieve the specified information. To return to read-array mode, issue the Read Array command
(0xFF).
Datasheet 19
Intel£Advanced+ Boot Block Flash Memory (C3)
Table 6. Device Identification Codes
Item
Manufacturer ID Block 0x00 0x0089
Device ID Block 0x01
Block Lock Status
Block Lock-Down Status
Protection Register Lock Status Block 0x80 Lock Data
Protection Register Block
NOTES:
1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status
for block number 38 in a bottom boot device, set the address to 0x0F8000 plus the
0x0F8002. Then examine DQ0 of the data to determine if the block is locked.
2. See Section 5.2, “Reading Block-Lock Status” on page 28 for valid lock status.
2
2
Address
Base Offset
Block 0x02
Block 0x02
1
0x81 -
0x88
Data Description
0x88C0 8-Mbit Top Boot Device
0x88C1 8-Mbit Bottom Boot Device
0x88C2 16-Mbit Top Boot Device
0x88C3 16-Mbit Bottom Boot Device
0x88C4 32-Mbit Top Boot Device
0x88C5 32-Mbit Bottom Boot Device
0x88CC 64-Mbit Top Boot Device
0x88CD 64-Mbit Bottom Boot Device
DQ0 = 0b0 Block is unlocked
DQ0 = 0b1 Block is locked
DQ1 = 0b0 Block is not locked-down
DQ1 = 0b1 Block is locked down
Register Data
Multiple reads required to read
the entire 128-bit Protection
Register.
offset (0x02), i.e.
4.1.3 CFI Query
The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read Query
Command (0x98). The CFI data structure contains information such as block size, density,
command set, and electrical specifications. Once in this mode, read cycles from addresses shown in
Appendix C, “Common Flash Interface,” retrieve the specified information. To return to read-array
mode, issue the Read Array command (0xFF).
4.1.4 Read Status Register
The status register indicates the status of device operations, and the success/failure of that
operation. The Read Status Register (0x70) command causes subsequent reads to output data from
the status register until another command is issued. To return to reading from the array, issue a
Read Array (0xFF) command.
The status-register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 0x00 when a
Read Status Register command is issued.
20 Datasheet
The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs
last) which prevents possible bus errors that might occur if Status Register contents change while
being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register
will not indicate completion of a Program or Erase operation.
When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits in the
status register indicate whether the WSM was successful in performing the preferred operation (see
Table 9, “Status Register Bit Definition” on page 26).
4.1.4.1 Clear Status Register
The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7; but, the WSM
cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error
conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By
allowing the system software to control the resetting of these bits, several operations may be
performed (such as cumulatively programming several addresses or erasing multiple blocks in
sequence) before reading the status register to determine if an error occurred during that series.
Clear the status register before beginning another command or sequence. The Read Array
command must be issued before data can be read from the memory array. Resetting the device also
clears the Status Register.
Intel£Advanced+ Boot Block Flash Memory (C3)
4.2 Program Mode
Programming is executed using a two-write cycle sequence. The Program Setup command (0x40)
is issued to the CUI followed by a second write which specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program preferred
bits of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If users attempt
to program “1”s, the memory cell contents do not change and no error occurs.
The Status Register indicates programming status. While the program sequence executes, status bit
7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the program-status bits should be checked. If the programming
operation was unsuccessful, bit SR[4] of the Status Register is set to indicate a program failure. If
SR[3] is set, then V
command. If SR[1] is set, a program operation was attempted on a locked block and the operation
was aborted.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent status-register reads, be
sure to reset the CUI to read-array mode.
4.2.1 12-Volt Production Programming
When VPPis between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC
pin. Note that if V
1.65 V to perform in-system flash modifications. When V
the device draws program and erase current directly from the VPP pin. This eliminates the need for
an external switching transistor to control V
flash power supplies can be configured for various usage models.
was not within acceptable limits, and the WSM did not execute the program
PP
is driven by a logic signal, VIHmin = 1.65 V. That is, VPPmust remain above
PP
PP
is connected to a 12 V power supply,
PP
. Figure 7 on page 31 shows examples of how the
Datasheet 21
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