INFINEON XC164-32F User Manual

Data Sheet, V1.0, June 2005

XC164-32F

16-Bit Single-Chip Microcontroller
with C166SV2 Core

Microcontrollers

Never stop thinking.

Edition 2005-06

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany

© Infineon Technologies AG 2005.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.

Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

Data Sheet, V1.0, June 2005

XC164-32F

16-Bit Single-Chip Microcontroller
with C166SV2 Core

Microcontrollers

Never stop thinking.

XC164

Revision History: 2005-06 V1.0

Previous Version: none

Page Subjects (major changes since last revision)

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Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15

XC164-32

Derivatives

Table of Contents

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.5 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.6 Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.7 The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.8 General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.9 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.10 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.11 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 40

3.12 High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 41

3.13 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.14 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.15 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.16 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.17 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.18 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.3 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.4 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.4.1 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.4.2 On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.4.3 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4.4 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.4.5 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.2 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data Sheet 3 V1.0, 2005-06

XC16416-Bit Single-Chip Microcontroller with C166SV2 Core

XC166 Family

1 Summary of Features

• High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 bytes On-Chip Special Function Register Area (C166 Family Compatible)

• 16-Priority-Level Interrupt System with 75 Sources, Sample-Rate down to 50 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space

• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)

• On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 4 Kbytes On-Chip Data SRAM (DSRAM)
– 6 Kbytes On-Chip Program/Data SRAM (PSRAM)
– 256 Kbytes On-Chip Program Memory (Flash Memory)

• On-Chip Peripheral Modules
– 14-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and

Conversion Time (down to 2.55 µs or 2.15 µs)
– Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects

(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
– On-Chip Real Time Clock

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

Data Sheet 4 V1.0, 2005-06

XC164-32

Derivatives

Summary of Features

• Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-bit or 8-bit Data Bus Width
– Four Programmable Chip-Select Signals

• Up to 79 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis

• On-Chip Bootstrap Loader

• Supported by a Large Range of Development Tools like C-Compilers, Macro­Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators,
Logic Analyzer Disassemblers, Programming Boards

• On-Chip Debug Support via JTAG Interface

• 100-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the XC164 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.

This document describes several derivatives of the XC164 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term XC164 throughout this document.

Data Sheet 5 V1.0, 2005-06

Table 1 XC164 Derivative Synopsis

Derivative

1)

Standard Devices

2)

Temp.
Range

Program
Memory

XC164-32

Derivatives

Summary of Features

On-Chip RAM Interfaces

SAK-XC164CS-32F40F
SAK-XC164CS-32F20F

SAF-XC164CS-32F40F
SAF-XC164CS-32F20F

SAK-XC164CL-32F40F
SAK-XC164CL-32F20F

SAF-XC164CL-32F40F
SAF-XC164CL-32F20F

SAK-XC164CR-32F40F
SAK-XC164CR-32F20F

SAF-XC164CR-32F40F
SAF-XC164CR-32F20F

SAK-XC164CB-32F40F
SAK-XC164CB-32F20F

SAF-XC164CB-32F40F
SAF-XC164CB-32F20F

Grade A Devices

2)

-40 °C to
125 °C

-40 °C to
85 °C

-40 °C to
125 °C

-40 °C to
85 °C

-40 °C to
125 °C

-40 °C to
85 °C

-40 °C to
125 °C

-40 °C to
85 °C

256 Kbytes
Flash

256 Kbytes
Flash

256 Kbytes
Flash

256 Kbytes
Flash

2 Kbytes DPRAM,
4 Kbytes DSRAM,
6 Kbytes PSRAM

2 Kbytes DPRAM,
4 Kbytes DSRAM,
6 Kbytes PSRAM

2 Kbytes DPRAM,
4 Kbytes DSRAM,
6 Kbytes PSRAM

2 Kbytes DPRAM,
4 Kbytes DSRAM,
6 Kbytes PSRAM

ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1,
CC6

ASC0, ASC1,
SSC0, SSC1,
CAN0

ASC0, ASC1,
SSC0, SSC1,
CAN0,
CC6

ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1

SAK-XC164CS-32F40F
SAK-XC164CS-32F20F

SAF-XC164CS-32F40F
SAF-XC164CS-32F20F

1) This Data Sheet is valid for devices starting with and including design step BA.

2) The Flash speed grading indicates the access time to the on-chip Flash module. According to this access time

Flash waitstates must be selected (bitfield WSFLASH in register IMBCTRL) according to the intended
operating frequency. For more details, please refer to Section 4.4.2.
Grade A devices are identified by “Grade A” in the fourth line of the chip marking.

Data Sheet 6 V1.0, 2005-06

-40 °C to
125 °C

-40 °C to
85 °C

256 Kbytes
Flash

2 Kbytes DPRAM,
4 Kbytes DSRAM,
6 Kbytes PSRAM

ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1,
CC6

XC164-32

Derivatives

General Device Information

2 General Device Information

2.1 Introduction

The XC164 derivatives are high-performance members of the Infineon XC166 Family of
full featured single-chip CMOS microcontrollers. These devices extend the functionality
and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and
speed. They combine high CPU performance (up to 40 million instructions per second)
with high peripheral functionality and enhanced IO-capabilities. They also provide clock
generation via PLL and various on-chip memory modules such as program Flash,
program RAM, and data RAM.

Port 20
5 bit

XTAL1

XTAL2

NMI

RSTIN

RSTOUT

EA

ALE

RD

V

AREF

V

AGND

XC164

V

DDI/P

V

SSI/P

PORT0
16 bit

PORT1
16 bit

Port 3
14 bit

Port 4
8 bit

WR/WRL

Port 5
14 bit

Port 9
6 bit

JTAGTRST Debug

via Port 3

MCA05554_XC 164

Figure 1 Logic Symbol

Data Sheet 7 V1.0, 2005-06

XC164-32

Derivatives

General Device Information

2.2 Pin Configuration and Definition

The pins of the XC164 are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) and C*) mark pins to be used as alternate external
interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them.

SSP
DDP

SSP
DDP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

P20.12/RSTOUT

RSTIN

NMI
P0H.0/AD8
P0H.1/AD9

P0H.2/AD10
P0H.3/AD11

V

V

P9.0/CC16IO/C*)
P9.1/CC17IO/C*)
P9.2/CC18IO/C*)
P9.3/CC19IO/C*)

P9.4/CC20IO
P9.5/CC21IO

V

V

P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4

P5.5/AN5
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD 25

SSIVDDI

V

P1H.7/A15/CC27IO/EX7IN

P1H.6/A14/CC26IO/EX6IN

P1H.5/A13/CC25IO/EX5IN

P1H.4/A12/CC24IO/EX4IN

P1H.3/A11/T7IN/SCLK1/EX3IN/E*)

XTAL1

XTAL2

9998979695949392919089888786858483828180797877

100

26272829303132333435363738394041424344

P1H.2/A10/C6P2/MTSR1/EX2IN

P1H.1/A9/C6P1/MRST1/EX1IN

P1H.0/A8/C6P0/CC23IO/EX0IN

XC164

V

SSPVDDP

P1L.7/A7/CTRAP/CC22IO

P1L.6/A6/COUT63

P1L.5/A5/COUT62

P1L.4/A4/CC62

P1L.3/A3/COUT61

P1L.2/A2/CC61

P1L.1/A1/COUT60

P1L.0/A0/CC60

45P3.7/T2IN/BRKIN46474849

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51 P3.13/SCLK0/E*)

50

P0H.4/AD12
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
P20.5/EA
P20.4/ALE
P20.1/WR/WRL
P20.0/RD

V

SSP

V

DDP

P4.7/A23/C*)
P4.6/A22/C*)
P4.5/A21/C*)
P4.4/A20/C*)
P4.3/A19/CS0
P4.2/A18/CS1
P4.1/A17/CS2
P4.0/A16/CS3
P3.15/CLKOUT/FOUT

SSI

DDI

SSP

TRST

DDP

V

V

P3.6/T3IN

P3.8/MRST0

P3.9/MTSR0

P3.10/TxD0/E*)

P3.2/CAPIN/TDI

P3.3/T3OUT/TDO

P3.4/T3EUD/TMS

P3.1/T6OUT/RxD1/TCK/E*)

P3.5/T4IN/TxD1/BRKOUT

P3.11/RxD0/E*)

P3.12/BHE/WRH/E*)

MCP06457

AREF

AGND

V

V

P5.6/AN6

P5.7/AN7

P5.12/AN12/T6IN

V

V

P5.13/AN13/T5IN

P5.14/AN14/T4EUD

P5.15/AN15/T2EUD

Figure 2 Pin Configuration (top view)

Data Sheet 8 V1.0, 2005-06

Table 2 Pin Definitions and Functions

XC164-32

Derivatives

General Device Information

Sym­bol

Pin
Num.

Input
Outp.

Function

RSTIN 1 I Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the XC164.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.

Note: The reset duration must be sufficient to let the

hardware configuration signals settle.
External circuitry must guarantee low level at the
RSTIN

pin at least until both power supply voltages

have reached the operating range.

P20.12 2 IO For details, please refer to the description of P20.

NMI

3 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164 into power down
mode. If NMI

is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI

should be pulled high externally.

P0H.0 ­P0H.3

4 … 7 IO For details, please refer to the description of PORT0.

Data Sheet 9 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

XC164-32

Derivatives

General Device Information

Sym­bol

P9

P9.0

P9.1

P9.2

P9.3

P9.4
P9.5

Pin
Num.

10

11

12

13

14
15

Input
Outp.

IO

I/O
I
I
I/O
O
I
I/O
I
I
I/O
O
I
I/O
I/O

Function

Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 9 is selectable (standard
or special).
The following Port 9 pins also serve for alternate functions:
CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN2_RxD CAN Node 2 Receive Data Input,
EX7IN Fast External Interrupt 7 Input (alternate pin B)
CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN2_TxD CAN Node 2 Transmit Data Output,
EX6IN Fast External Interrupt 6 Input (alternate pin B)
CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN Node 1 Receive Data Input,
EX7IN Fast External Interrupt 7 Input (alternate pin A)
CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN Node 1 Transmit Data Output,
EX6IN Fast External Interrupt 6 Input (alternate pin A)
CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp.
CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp.

1)

P5

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10
P5.11
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15

18
19
20
21
22
23
24
25
26
27
30
31
32
33

I

Port 5 is a 14-bit input-only port.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:

I
I
I
I
I
I
I
I
I
I
I
I
I
I

AN0
AN1
AN2
AN3
AN4
AN5
AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
AN6
AN7
AN12, T6IN GPT2 Timer T6 Count/Gate Input
AN13, T5IN GPT2 Timer T5 Count/Gate Input
AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

Data Sheet 10 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

XC164-32

Derivatives

General Device Information

Sym­bol

Pin
Num.

Input
Outp.

Function

TRST 36 I Test-System Reset Input. A high level at this pin activates

the XC164’s debug system. For normal system operation,

P3

IO

pin TRST

Port 3 is a 14-bit bidirectional I/O port. Each pin can be

should be held low.

programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 3 is selectable (standard
or special).
The following Port 3 pins also serve for alternate functions:

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6
P3.7

P3.8
P3.9
P3.10

P3.11

P3.12

P3.13

P3.15

39

40

41

42

43

44
45

46
47
48

49

50

51

52

O
I/O
I
I
I
I
O
O
I
I
I
O
O
I
I
I
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
O
O

T6OUT GPT2 Timer T6 Toggle Latch Output,
RxD1 ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN Fast External Interrupt 1 Input (alternate pin A),
TCK Debug System: JTAG Clock Input
CAPIN GPT2 Register CAPREL Capture Input,
TDI Debug System: JTAG Data In
T3OUT GPT1 Timer T3 Toggle Latch Output,
TDO Debug System: JTAG Data Out
T3EUD GPT1 Timer T3 External Up/Down Control Input,
TMS Debug System: JTAG Test Mode Selection
T4IN GPT1 Timer T4 Count/Gate/Reload/Capture In.,
TxD1 ASC0 Clock/Data Output (Async./Sync.),
BRKOUT

Debug System: Break Out
T3IN GPT1 Timer T3 Count/Gate Input
T2IN GPT1 Timer T2 Count/Gate/Reload/Capture In.,
BRKIN

Debug System: Break In
MRST0 SSC0 Master-Receive/Slave-Transmit In/Out.
MTSR0 SSC0 Master-Transmit/Slave-Receive Out/In.
TxD0 ASC0 Clock/Data Output (Async./Sync.),
EX2IN Fast External Interrupt 2 Input (alternate pin B)
RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN Fast External Interrupt 2 Input (alternate pin A)
BHE
WRH

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe,
EX3IN Fast External Interrupt 3 Input (alternate pin B)
SCLK0 SSC0 Master Clock Output / Slave Clock Input,
EX3IN Fast External Interrupt 3 Input (alternate pin A)
CLKOUT System Clock Output (= CPU Clock),
FOUT Programmable Frequency Output

Data Sheet 11 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

XC164-32

Derivatives

General Device Information

Sym­bol

P4

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

Pin
Num.

53

54

55

56

57

58

59

60

Input
Outp.

IO

O
O
O
O
O
O
O
O
O
I
I
O
I
I
O
O
I
O
I
O
I

Function

Port 4 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 4 is selectable (standard
or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:

1)

A16 Least Significant Segment Address Line,
CS3

Chip Select 3 Output
A17 Segment Address Line,
CS2

Chip Select 2 Output
A18 Segment Address Line,
CS1

Chip Select 1 Output
A19 Segment Address Line,
CS0

Chip Select 0 Output
A20 Segment Address Line,
CAN2_RxD CAN Node 2 Receive Data Input,
EX5IN Fast External Interrupt 5 Input (alternate pin B)
A21 Segment Address Line,
CAN1_RxD CAN Node 1 Receive Data Input,
EX4IN Fast External Interrupt 4 Input (alternate pin B)
A22 Segment Address Line,
CAN1_TxD CAN Node 1 Transmit Data Output,
EX5IN Fast External Interrupt 5 Input (alternate pin A)
A23 Most Significant Segment Address Line,
CAN1_RxD CAN Node 1 Receive Data Input,
CAN2_TxD CAN Node 2 Transmit Data Output,
EX4IN Fast External Interrupt 4 Input (alternate pin A)

Data Sheet 12 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

XC164-32

Derivatives

General Device Information

Sym­bol

P20

P20.0

P20.1

P20.4

P20.5

P20.12

Pin
Num.

63

64

65

66

2

Input
Outp.

IO

O

O

O

I

O

Function

Port 20 is a 5-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
RD

External Memory Read Strobe, activated for

every external instruction or data read access.
WR

/WRL External Memory Write Strobe.

In WR

-mode this pin is activated for every
external data write access.
In WRL

-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.

ALE Address Latch Enable Output.

Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.

EA

External Access Enable pin.
A low level at this pin during and after Reset
forces the XC164 to latch the configuration from
PORT0 and pin RD

, and to begin instruction

execution out of external memory.
A high level forces the XC164 to latch the
configuration from pins RD

, ALE, and WR, and
to begin instruction execution out of the internal
program memory. “ROMless” versions must
have this pin tied to ‘0’.

RSTOUT

Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.

Note: Port 20 pins may input configuration values (see EA

Data Sheet 13 V1.0, 2005-06

).

Table 2 Pin Definitions and Functions (cont’d)

XC164-32

Derivatives

General Device Information

Sym­bol

PORT0

P0L.0 ­P0L.7
P0H.0 ­P0H.3
P0H.4 ­P0H.7

PORT1

P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7

P1H

Pin
Num.

67 - 74

4 - 7

75 - 78

79
80
81
82
83
84
85
86

…

Input

Function

Outp.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.

Demultiplexed bus modes:

8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0

Multiplexed bus modes:

8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0
16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0

Note: At the end of an external reset (EA

= 0) PORT0 also

may input configuration values

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes (also after switching from a
demultiplexed to a multiplexed bus mode).

The following PORT1 pins also serve for alt. functions:
I/O
O
I/O
O
I/O
O
O
I

CC60 CAPCOM6: Input / Output of Channel 0

COUT60 CAPCOM6: Output of Channel 0

CC61 CAPCOM6: Input / Output of Channel 1

COUT61 CAPCOM6: Output of Channel 1

CC62 CAPCOM6: Input / Output of Channel 2

COUT62 CAPCOM6: Output of Channel 2

COUT63 Output of 10-bit Compare Channel

CTRAP

CTRAP

CAPCOM6: Trap Input

is an input pin with an internal pull-up resistor. A low
level on this pin switches the CAPCOM6 compare outputs to
the logic level defined by software (if enabled).

I/O

CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp.
…continued…

Data Sheet 14 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

XC164-32

Derivatives

General Device Information

Sym­bol

PORT1

(cont’d)
P1H.0

P1H.1

P1H.2

P1H.3

P1H.4

P1H.5

P1H.6

P1H.7

Pin
Num.

89

90

91

92

93

94

95

96

Input
Outp.

IO

I
I
I/O
I
I
I/O
I
I
I/O
I
I/O
I
I
I/O
I
I/O
I
I/O
I
I/O
I

Function

…continued…

CC6POS0

CAPCOM6: Position 0 Input,
EX0IN Fast External Interrupt 0 Input (default pin),
CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.
CC6POS1

CAPCOM6: Position 1 Input,
EX1IN Fast External Interrupt 1 Input (default pin),
MRST1 SSC1 Master-Receive/Slave-Transmit In/Out.
CC6POS2

CAPCOM6: Position 2 Input,
EX2IN Fast External Interrupt 2 Input (default pin),
MTSR1 SSC1 Master-Transmit/Slave-Receive Out/Inp.
T7IN CAPCOM2: Timer T7 Count Input,
SCLK1 SSC1 Master Clock Output / Slave Clock Input,
EX3IN Fast External Interrupt 3 Input (default pin),
EX0IN Fast External Interrupt 0 Input (alternate pin A)
CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp.,
EX4IN Fast External Interrupt 4 Input (default pin)
CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp.,
EX5IN Fast External Interrupt 5 Input (default pin)
CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp.,
EX6IN Fast External Interrupt 6 Input (default pin)
CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp.,
EX7IN Fast External Interrupt 7 Input (default pin)

XTAL2
XTAL1

99
100

O
I

XTAL2: Output of the oscillator amplifier circuit
XTAL1: Input to the oscillator amplifier and input to the

internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC.
Characteristics must be observed.

V

V

V

AREF

AGND

DDI

28 – Reference voltage for the A/D converter.

29 – Reference ground for the A/D converter.

35, 97 – Digital Core Supply Voltage (On-Chip Modules):

+2.5 V during normal operation and idle mode.
Please refer to the Operating Condition Parameters.

Data Sheet 15 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

XC164-32

Derivatives

General Device Information

Sym­bol

V

DDP

V

SSI

V

SSP

Pin
Num.

9, 17,
38, 61,
87

Input

Function

Outp.

– Digital Pad Supply Voltage (Pin Output Drivers):

+5 V during normal operation and idle mode.
Please refer to the Operating Condition Parameters.

34, 98 – Digital Ground

8, 16,
37, 62,
88

–

Connect decoupling capacitors to adjacent
as close as possible to the pins.
All

V

pins must be connected to the ground-line or ground-

SS

plane.

1) The CAN interface lines are assigned to ports P4 and P9 under software control.

V

DD/VSS

pin pairs

Data Sheet 16 V1.0, 2005-06

XC164-32

Derivatives

Functional Description

3 Functional Description

The architecture of the XC164 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).

The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3).

This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164.

The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164.

256 Kbytes

Debug Support

Osc / PLL

Clock Generator

XTAL

ADC

8-Bi t/

10-Bit
14 Ch

PSRAM

ProgMem

Flash

OCDS

GPT

T2

T3

T4

T5

T6

DPRAM

CPU

PMU

RTC WDT Interrupt & PEC

ASC0

USART

BRGen BRGen BRGen BRGen

ASC1

USART

C166SV2 - Core

SSC0

SPI

SSC1

CC1

SPI

T0

T1

DMU

Interr upt Bus

CC2

T7

T8

CC6

T12

T13

DSRAM

EBC

LXBus Control

Exter nal Bus

Control

LXB us

Twin

CAN

A B

Peripheral Data Bus

P 20 P 9 Port 5 Port 4 Port 3 PORT1 PORT 0

5 6

14

16148

16

MCB04323_X432

Figure 3 Block Diagram

Data Sheet 17 V1.0, 2005-06

XC164-32

Derivatives

Functional Description

3.1 Memory Subsystem and Organization

The memory space of the XC164 is configured in a Von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed bytewise or wordwise. Portions of the
on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly
bitaddressable.

The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.

The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.

The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.

Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXBus (such as TwinCAN). The system
bus allows concurrent two-way communication for maximum transfer performance.

256 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and three 64-Kbyte
sectors. Each sector can be separately write protected

1)

, erased and programmed (in
blocks of 128 bytes). The complete Flash area can be read-protected. A password
sequence temporarily unlocks protected areas. The Flash module combines very fast
64-bit one-cycle read accesses with protected and efficient writing algorithms for
programming and erasing. Thus, program execution out of the internal Flash results in
maximum performance. Dynamic error correction provides extremely high read data
security for all read accesses.
For timing characteristics, please refer to Section 4.4.2.

6 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.

4 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data. The DSRAM is accessed via the DMU and is therefore optimized for data
accesses.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, and general purpose register banks. A register
bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7,

1) Each two 8-Kbyte sectors are combined for write-protection purposes.

Data Sheet 18 V1.0, 2005-06

XC164-32

Derivatives

Functional Description

RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.

In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.

Table 3 XC164 Memory Map

1)

Address Area Start Loc. End Loc. Area Size

Flash register space FF’F000

Reserved (Acc. trap) FE’0000

Reserved for EPSRAM F8’1800

Emul. Program
SRAM

4)

F8’0000

Reserved for PSRAM E0’1800

Program SRAM E0’0000

Reserved for program

C4’0000

H

H

H

H

H

H

H

FF’FFFF

FF’EFFF

FD’FFFF

F8’17FF

F7’FFFF

E0’17FF

DF’FFFF

4 Kbytes

H

60 Kbytes –

H

378 Kbytes –

H

6 Kbytes 2nd way to PSRAM

H

< 1.5 Mbytes Minus PSRAM

H

6 Kbytes Maximum

H

< 2 Mbytes Minus Flash

H

memory

Program Flash C0’0000

Reserved BF’0000

External memory area 40’0000

External IO area

5)

20’0800

H

H

H

H

C3’FFFF

BF’FFFF

BE’FFFF

3F’FFFF

256 Kbytes –

H

64 Kbytes –

H

< 8 Mbytes Minus reserved

H

< 2 Mbytes Minus TwinCAN

H

2)

Notes

3)

segment

TwinCAN registers 20’0000

External memory area 01’0000

Data RAMs and SFRs 00’8000

External memory area 00’0000

1) Accesses to the shaded areas generate external bus accesses.

2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.

3) Not defined register locations return a trap code.

4) The Emulation PSRAM (EPSRAM) realizes a 2nd access path to the PSRAM with a different timing.

Data Sheet 19 V1.0, 2005-06

H

H

H

H

20’07FF

1F’FFFF

00’FFFF

00’7FFF

2 Kbytes –

H

< 2 Mbytes Minus segment 0

H

32 Kbytes Partly used

H

32 Kbytes –

H

XC164-32

Derivatives

Functional Description

5) Several pipeline optimizations are not active within the external IO area. This is necessary to control external

peripherals properly.

3.2 External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes
are as follows:

• 16 … 24-bit Addresses, 16-bit Data, Demultiplexed

• 16 … 24-bit Addresses, 16-bit Data, Multiplexed

• 16 … 24-bit Addresses, 8-bit Data, Multiplexed

• 16 … 24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output. The high order address (segment) lines
use Port 4. The number of active segment address lines is selectable, restricting the
external address space to 8 Mbytes … 64 Kbytes. This is required when interface lines
are assigned to Port 4.

1)

, which

Up to 4 external CS

signals (3 windows plus default) can be generated in order to save
external glue logic. External modules can directly be connected to the common
address/data bus and their individual select lines.

Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control the access to different resources with different bus
characteristics. These address windows are arranged hierarchically where window 4
overrides window 3, and window 2 overrides window 1. All accesses to locations not
covered by these 4 address windows are controlled by TCONCS0/FCONCS0. The
currently active window can generate a chip select signal.

Note: The chip select signal of address window 4 is not available on a pin.

The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.

The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.

The TwinCAN module is connected and accessed via the LXBus.

1) Bus modes are switched dynamically if several address windows with different mode settings are used.

Data Sheet 20 V1.0, 2005-06

XC164-32

Derivatives

Functional Description

3.3 Central Processing Unit (CPU)

The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.

CPU

Prefetch

Branch

Multiply

Unit

Unit

FIFO

IDX0
IDX1

QX0
QX1

+/-

Unit

+/-

CSP IP
CPUCON1

CPUCON2

Return

Stack

QR0
QR1

+/-

MRW

MCW

MSW

IFU

DPP0
DPP1
DPP2
DPP3

Division Unit
M ultip ly U n it

MDC
PSW

VECSEG

TFR

Injection/

Exception

Handler

SPSEG

SP
STKOV
STKUN

Bit-Mask-Gen.

Barrel-Shifter

+/-

ADU

PMU

2-Stage

5-Stage

R15
R14

GPRs

GPRs

RF

Prefetch

Pipeline

Pipeline

CP

R15

R15

R14

R14

GPRs

R1

R1

R0

R1

R0

R0

PSRAM

Flash/ROM

DPRAM

IPIP

R15
R14

GPRs

R1
R0

MAC

MAH

MAL

MDH

ZEROS

MDL

ONES

ALU

Buffer

DMU

WB

DSRAM

EBC

Peripherals

mca04917_x.vsd

Figure 4 CPU Block Diagram

Based on these hardware provisions, most of the XC164’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift

Data Sheet 21 V1.0, 2005-06

XC164-32

Derivatives

Functional Description

and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. Also multiplication and most MAC instructions execute
in one single cycle. All multiple-cycle instructions have been optimized so that they can
be executed very fast as well: for example, a division algorithm is performed in 18 to 21
CPU cycles, depending on the data and division type. Four cycles are always visible, the
rest runs in the background. Another pipeline optimization, the branch target prediction,
allows eliminating the execution time of branch instructions if the prediction was correct.

The CPU has a register context consisting of up to three register banks with 16 wordwide
GPRs each at its disposal. The global register bank is physically allocated within the on­chip DPRAM area. A Context Pointer (CP) register determines the base address of the
active global register bank to be accessed by the CPU at any time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter
passing, a register bank may overlap others.

A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC164 instruction set which includes
the following instruction classes:

• Standard Arithmetic Instructions

• DSP-Oriented Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.

Data Sheet 22 V1.0, 2005-06