INFINEON TLE 6361 G User Manual

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Multi-Voltage Processor Power Supply

Data Sheet

1Overview

1.1 Features

• High efficiency regulator system

• Wide input voltage range, up to 60V

• Stand-by mode with low current consumption

• Suitable for standard 12V, 24V and 42V PowerNets

• Step down converter as pre-regulator:

5.5V / 1.5A

• Step down slope control for lowest EME

• Switching loss minimization

• Three high current linear post-regulators with selectable output voltages: 5V / 800mA

3.3V or 2.6V / 500mA 5V or 3.3V / 350mA

• Six independent voltage trackers (followers): 5V / 17mA each

• Stand-by regulator with 1mA current capability

• Three independent undervoltage detection circuits (e.g. reset, early warning) for each linear post-regulator

• Power on reset functionality

• Window watchdog triggered by SPI

• Tracker control and diagnosis by SPI

• All outputs protected against short-circuit

• Power-DSO-36 package

TLE 6361 G

P-DSO-36-12

Type Ordering Code Package

TLE 6361 G Q 67007-A9466 P-DSO-36-12

SMD = Surface Mounted Device

Data Sheet, Rev. 1.31 1 2004-10-12

TLE 6361 G

1.2 Short functional description

The

TLE 6361 G is a multi voltage power supply system especially designed for

automotive applicati ons using a standard 12V or 24V battery as well as the new 42V powernet. The device is intended to supply 32 bit micro-controller systems which require different supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for external sensors are also provided.

The TLE 6361 G cascades a Buck converter block with a linea r regulator and tracker block on a single chi p to ac hieve lowest power dissipa tion thus being able to po we r the application even at very high ambient temperatures.

The step-down converter delivers a pre-regulated voltage of 5.5V with a minimum current capability of 1.5A.

Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V, or 2.6V of output voltages dep ending on the configuration of the device with current capabilities of 800mA, 500mA and 350mA.

In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to drive a current of 17mA each. The trackers can be turned on and off individually by a 16 bit serial peripheral interfac e (SPI). Throu gh t his inte rf ace als o the stat us i nform atio n of each tracker (i.e. short circuit) can be read out.

To monitor the outp ut voltage le vels of each of the linear reg ulators three i ndependent undervoltage detection circui ts are ava ila ble w hic h can be us ed to impl eme nt the reset or an early warning function. The supervision of the µC is managed by the SPI-triggered window watchdog.

For energy saving reasons while the motor is turned off, the TLE 6361 G offers a standby mode, where the quie scent current does not ex ceed 30µA ty pically. I n this stand -by mode just the stand-by regulator remains active.

The TLE 63 61 G is based on In fineon Power tech nology SPT  which allows bi polar , CMOS and Power DMOS circuitry to be integrated on the same monolithic circuitry.

Data Sheet, Rev. 1.31 2 2004-10-12

1.3 Pin configuration

TLE 6361 G

P-DSO-36-12

GND

CLK

ERR

Q_STB

Q_T1

Q_T2

Q_T3

Q_T4

GND

SLEW

WAKE

BOOST

Bootstrap

Q_LDO1

FB/L_IN

Q_T5

Q_T6

Q_LDO3

GND

FB/L_IN

Q_LDO2

SEL

CCP

C+

C-

GND

Figure 1 Pin Configuration (Top View), bottom heatslug and GND corner pins are connected

Data Sheet, Rev. 1.31 3 2004-10-12

TLE 6361 G

1.4 Pin definitions and functions

Pin No. Symbol Function

1,18,19,36GND Ground; to reduce thermal resistance place cooling areas on

PCB close to this pins. Those pins are connected internally to the heatslug at the bottom.

2CLKSPI Interface Clock input; clocks the shiftregister; CLK has an

internal active pull down and requires CMOS logic level inputs;see also chapter SPI

3CS

SPI Interface chip select input; CS is an active low input; serial communication is enabled by pulling the CS input should only be switched when CLK is low; CS

terminal low; CS

has an internal active pull up and requires CMOS logic level inputs ;see also chapter SPI

4DI SPI Interface Date input; receives serial data from the control

device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first; the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see also chapter SPI

5DOSPI Interface Data output; this tristate output transfers

diagnosis data to the controlling device; the output will remain 3stated unless the device is selected by a low on Chip-Select CS see also the chapter SPI

6ERR

Error output; push-pull output. Monitors failures in parallel to the SPI diagnosis word, reset via SPI. ERR

is a latched output.

;

7Q_STBStandby Regulator Output; the output is active even when the

buck regulator and all other circuitry is in off mode

8 Q_T1 Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

9 Q_T2 Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

10 Q_T3 Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

Data Sheet, Rev. 1.31 4 2004-10-12

TLE 6361 G

1.4 Pin definitions and functions (cont’d)

Pin No. Symbol Function

11 Q_T4 Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

12 Q_T5 Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

13 Q_T6 Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

14 Q_LDO3 Voltage Regulator Output 3; 5V or 3.3V output; ouput voltage

is selected by pin SEL (see also 3.4.2); For stability a ceramic capacitor of 470nF to GND is sufficient.

15 R3 Reset output 3, undervoltage detection for output Q_LDO3;

open collector output; an external pullup resistor of 10kΩ is

required

16 R2 Reset output 2, undervoltage detection for output Q_LDO2;

open collector output; an external pullup resistor of 10kΩ is

required

17 R1 Reset output 1, undervoltage detection for output Q_LDO1 and

watchdog failure reset; open collector output ; an external pullup

resistor of 10kΩ is required

20 C- Charge pump capacitor connection; Add the fly-capacitor of

100nF between C+ and C-

21 C+ Charge pump capacitor connection; Add the fly-capacitor of

100nF between C+ and C-

22 CCP Charge Pump Storage Capacitor Output; Add the storage

capacitor of 220nF between pin CCP and GND.

23 SEL Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3

(see also 2.2.2)

24 Q_LDO2 Voltage Regulator Output 2; 3.3V or 2.6V output; output

voltage is selected by pin SEL (see also 3.4.2); For stability a ceramic capacitor of 470nF to GND is sufficient.

25, 26 FB/L_IN Feedback and Linear Regulator Input; input connection for

the Buck converter output

Data Sheet, Rev. 1.31 5 2004-10-12

TLE 6361 G

1.4 Pin definitions and functions (cont’d)

Pin No. Symbol Function

27 Q_LDO1 Voltage Regulator Output 1; 5V output; acts as the reference

for the voltage trackers.The SPI and window watchdog logic is supplied from this voltage. For stability a ceramic capacitor of 470nF to GND is sufficient.

28 Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW

and pin Bootstrap, the capcitance value should be not lower than 2% of the Buck converter output capacitance

29, 31 SW Switch Output; connect both pins externally through short lines

directly to the cathode of the catch diode and the Buck circuit inductance.

30, 32 IN Supply Voltage Input; connect both pins externally through

short lines to the input filter/the input capacitors.

33 BOOST Boost Input; for switching loss minimization connect a diode

(cathode directly to boost pin) in series with a 100nF ceramic capacitor to the IN pin and from the anode of the diode to the

buck converter output a 22Ω resistor. Recommended for 42V

applications, in 12/24V applications connect boost directly to IN

34 WAKE Wake Up Input; a positive voltage applied to this pin turns on

the device

35 SLEW Slew control Input; a resistor to GND defines the current slope

in the buck switch for reduced EME

Data Sheet, Rev. 1.31 6 2004-10-12

1.5 Basic block diagram

Boost

Slew

OSZ PWM

Driver

TLE 6361

Standby

Regulator

2.5V

REGULATOR

Error-

Amplifier

Internal Reference

feedback

BUCK

Q_STB

Bootstrap

FB/L_IN

TLE 6361 G

Wake

CLK

ERR

Protection

Power Down Logic

Reset Logic

Window

Watchdog

SPI

16 bit

C+

CCP

Q_LDO1

Q_LDO2

Q_LDO3

Q_T1

Q_T2

Q_T3

Q_T4

Q_T5

Q_T6

SEL

C-

µ-controller /

memory

supply

Sensor

supplies

(off board

supplies)

Charge

Pump

Linear Reg. 1

Linear

Reg. 2

Linear Reg. 3

ref

Tracker

ref

Tracker

ref

Tracker

ref

Tracker

ref

Tracker

ref

Tracker

GND

Figure 2 Block Diagram

Data Sheet, Rev. 1.31 7 2004-10-12

TLE 6361 G

2 Detailed circuit description

In the following major buck regulator b locks, the linear vo ltage regul ators and track ers, the undervoltage reset function, the watchdog and the SPI are described in more detail.

For applications information e.g. choice of external components, please refer to section .

2.1 Buck Regulator

The diagram below shows the internal implemented circuit of the Buck converter, i. e. the internal DMOS devices, the regulation loop and the other major blocks.

5V 14V

Int. volta ge

regulator

FB/L_IN

C+

C-

Divider

Oscillator

1.4MHz

Voltage feedback amplifier

Vref=6V

from current sensing

Current

sense

amplifier

Lowpass

8 to 10V

CCP

Int. charge

pump

150µA

Slope compensation

Current

comparator

BOOTSTRAP

switchi ng frequency 330kHz

Gate off signal fr om overtem p or sleep command

Trigger for gate off

Trigger for gate on

PWM logic

Main switch ON/OFF

Slope logi c

Delay unit

Gate driver

Slope switc h charge signal

Slope switch discharg e signal

undervoltage lockout

Zero cross

detection

current sense

amplifi er

Main

DMOS

Slope

DMOS

BOOST

Slope

control

SLEW

exter nal comp onents

pins

Figure 3 Detailed Buck regulator diagram

The 1.5A Buck regulator consists of two internal DMOS power stages including a current mode regulation scheme to avoid external compensation components plus additional blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how

Data Sheet, Rev. 1.31 8 2004-10-12

TLE 6361 G

the gate driver supply is managed by the combination of internal charge pump, external charge pump and bootstrap capacitor.

2.1.1 Current mode control scheme

The regulation loop is located at the left lower corner in the schematic, there you find the voltage feedback amplifier which gives the actual information of the actual output voltage level and the current sense ampl ifier for the load current inform ation to form finally the regulation signal. To avoid subh armo nic osci llations at duty cycles highe r than 5 0% the slope compensation block is necessary. The control signal formed out of those three blocks is finally the input of the PWM regulator for the DMOS gate turn off command, which means this signal determines the duty cycle. The gate turn on signal is set by the o scillator periodical ly every 3µs which leads to a Buck converter switching frequency around 330kHz.

With decreasing input voltag e the de vic e ch anges to the so called pulse skipp ing mode which means basically that some of the oscillator gate turn off signals are ignored. When the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and its gate is supplied by the internal charge pump. Below typic al 4. 5V at the feedback pin the device is turned off.During normal switching operation the gate driver is supplied by the bootstrap capacitor.

2.1.2 Start-up procedure

To guarantee a device startup even under full load condition at the linear regulator outputs a special start up procedure is impleme nted. At first the bootstrap capa citor is charged by the internal charge pump. Afterwards the outpuput capacitor is charged where the driver supply in that case is maintained only by the bootstrap capacitor. Once the output capacitor of the buck converter is charged the external charge pump is activated being able to sup ply the linear regulators and fina lly the linear regulators are released to supply the loads.

2.1.3 Reduction of electromagnetic emission

In figure 3 it is recognized that two internal DMOS switches are used, a main switch and an auxiliary switch. The second imp lemented switc h is used to adjust the current slope of the switching current. The slope adjustment is done by a controlled charge and discharge of the gate of this DMOS. By choos ing the external slew re sistor a ppropriate the current transition time can be adjusted between 20ns and 100ns.

2.1.4 Reducing the switching losses

The second purpose of the slope DMOS is to minimise the switching losses. Once being in freewheeling mode of the buck regulato r the output volta ge level is sufficient to force the load current to flow, the in put voltage level is not needed in the first mo ment. By a feedback network consis ting of a resistor and a diode to th e boost pin (connectio n see

Data Sheet, Rev. 1.31 9 2004-10-12

TLE 6361 G

section ) the output volt age level is present at the drain of the switch. As soon as the voltage at the SW pin passes zero volts the handover to the main switch occurs and the traditional switching behaviour of the Buck switch can be observed.

2.2 Linear Voltage Regulators

The Linear regulators offer voltage rail s of 5V, 3.3 V and 2.6V whi ch can be det ermined by a hardware connection (see table at 2.2.2) for proper power up procedure. Being supplied by the output of the Buc k pre-regulator the power loss within the three linear regulators is minimized.

All voltage regulators are short circuit protected which means that each regulator provides a maximum cu rrent according to its current li mit when shorted. Together with the external charge p ump the NPN pass elemen ts of the regulators allow low dropout voltage operation. By u sing this structu re the linear regulat ors work stable even with a minimum of 470nF ceramic capacitors at their output.

Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmable output voltage of 3.3V or 2.6V and Q_LDO3 is programmable to 5V or 3.3V (see 2.2.2). All three regulators are on all the time, if one regulator is not needed a base load resistor in parallel to the output capacitance for controlled power down is recommended.

2.2.1 Startup Sequence Linear Regulators

When acting as 32 bit µC supply the so-called power sequencing (the dependency of the different voltage reails to each other) is important. Within the TLE 6361 G the following Startup-Sequence is defined (see also figure 4):

Q_LDO2

≤ V

Q_LDO1; VQ_LDO3

≤ V

Q_LDO1

with V

Q_LDO1

=5V, V

Q_LDO2

= 2.6V and V

Q_LDO3

= 3.3V and V

Q_LDO2

≤ V

Q_LDO1

with V

Q_LDO1

=5V, V

Q_LDO2

= 2.6V/3.3V and V

Q_LDO3

= 5V

The power sequencing refers to the regulator itself, externally voltages applied at Q_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lower than those outputs. That means for the power down se quencing if different output capa citors and different loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this behaviour three Schottky diodes have to be connected between the three outputs of the linear regulators in that way that the cathodes of the diodes are always connected to the higher nominal rail.

Data Sheet, Rev. 1.31 10 2004-10-12

Power Sequencing

FB/L_IN

LDO_EN

Q_LDO1

Rth5

3.3V

2.6V

(2.6V Mode)

Q_LDO2

TLE 6361 G

0.7V 5V LDO 5V LDO

5V LDO 5V LDO

+/- 50mV

0.7V

+/- 50mV

Q_LDO3

2.6V

3.3V

Rth2.6

Rth3.3

(3.3V Mode)

Figure 4 Power-up and -down sequencing of the regulators

2.2.2 Q_LDO2 and Q_LDO3 output voltage selection*

To determine the output voltage le vels of the three linear regulators, the se lection pin (SEL, pin 23) has to be connected according to the matrix given in the table below.

Definition of Output voltage Q_LDO2 and Q_LDO3 Select Pin SEL

connected to

Q_LDO2 output voltage

Q_LDO3 output voltage

GND 3.3 V 5 V Q_LDO1 2.6 V 3.3 V Q_LDO2 2.6 V 5 V

* for different output voltages ple as e ref er t o th e m ult i vo lta ge s upply TLE6368

Data Sheet, Rev. 1.31 11 2004-10-12

TLE 6361 G

2.3 Voltage Trackers

For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output current capability each are available. The output voltages match Q_LDO1 within +5 / -15mV. They can be individually turned on and off by the appropriate SPI command word sent by the microcontroller. A ceramic capacitor with the value of 1µF at the output of each tracker is sufficient for stable operation without oscillation.

The tracker outputs can be connected in parallel to obtain a higher output current capability, no matter if on ly two or up to all si x trackers are tied together. For uniform ly distributed current d ensity in eac h tracker interna l balance res istors at each output are foreseen internally. By connecting twice three trackers in parallel two sensors with more than 50mA each can be supplied, all six in parallel give more than 100mA.

The tracker outputs can withstand short circuits to GND or battery in a range from -5 to +60V. A short circuit to GND at is detected and indicated individually for each tracker in the SPI status word. Al so an open load conditio n mi ght be re cog nis ed and indicated as a failure condition in the SPI status word. A minimum load current of 2mA is required to avoid open load failure indica tion. In cas e of connecti ng several tra ckers to a comm on branch balancing currents can prevent proper operation of the failure indication.

2.4 Standby Regulator

The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output current which is on all the time. It is intended to supply the mic r oco ntrol ler in stop mode and requires then onl y a minimum of quiescent current (<30µA) to extend the battery lifetime.

2.5 Charge Pump

The 1.6 MHz charge pump with the two external capacitors will serve to supply the base of the NPN linear regulators Q_LDO1 and Q_LDO3 as well as the gate of the Buck DMOS transistor in 100% duty cycle operation at low battery condition. The charge pump voltage in the range of 8 to 10V can be measured at pin 22 (CCP) but is not intended to be used as a supply for additional circuitry.

2.6 Power On Reset

A power on reset is available for eac h linear voltage regu lator output. The reset out put lines R1, R2 and R3 ar e ac tiv e (lo w) d uring sta rt up a nd turn inactive with a rese t delay time after Q_LDO1, Q_LDO2 and Q_LDO3 have reached their reset threshold. The reset outputs are open collector, three pull up resistors of 10kΩ each have to be connected to the I/O rail (e.g. Q _LDO1) of the µC. All three reset output s can be link ed in parallel to obtain a wired-OR.

The reset delay time is 64 ms by default and can be set to lower values as 8 ms, 16 ms or 32 ms by SPI command. At each power up of the device when the output volta ge at

Data Sheet, Rev. 1.31 12 2004-10-12

TLE 6361 G

Q_LDO1 has decreased below 3.3V (max.) the default settings are valid, means the 64ms delay time. If th e voltage on Q_LDO1 during s leep or power off mode wa s kept above 3.3V the delay time set by the last SPI command is valid.

FB/L_IN

Q_LDOx

< t

RES

RTH,Q_LDOx

thermal

shutdown

under

voltage

over load

Figure 5 Undervoltage reset timing

2.7 RAM good flag

A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops below 2.3V. A second one wi ll be set if Q_LDO2 drops belo w typical 1.4V. Both RAM good flags can be read after power up to determine if a c old or warm start n eeds to be processed. Both RAM good flags will be reset after each SPI cycle.

2.8 ERR

An hardware error pin indicates any fault conditions on the chip. It should be connected to an interrupt input of the microcontroller. A low signal indicates an error condition. The microcontroller can read the root cause of the error by reading the SPI register.

2.9 Window Watchdog

The on board window watchdog for supervision of the µC works in combination with the SPI. The window watchdog logic is triggered when CS

is low and Bit WD-Trig in the SPI command word is set to “1”. The wa tchdog trigger is recognized with the low to high transition of the CS

signal. To allow reading the SPI at an y time without get ting a reset due to misinterpretation the WD-Trig bit has to be set to “0” to avoid false trigger conditions. To disable the window watchdog the WD-OFF bits need to be set to “010”.

Data Sheet, Rev. 1.31 13 2004-10-12

tCW=t

tOW=t

= tOW/2

(not the same scale)

TLE 6361 G

= t

WDR

RES

(not the same scale)

definition

closed window open window

ECW

reset delay time without trigger

reset start delay time after window

watchdog timeout

= end of open windowt

EOW

reset duration time after window

watchdog time-out

Example with:

=128ms

OSC=fOSCmax

worst cases

OSC=fOSCmin

EOW, w.c.

ECW, w.c.

= ( tCW+t

= t

(1+∆)

)(1-∆)

OWmin

= t

- ∆ * ( t

+ 2* tCW )Minimum open window time:

∆=25% (oscillator deviation)

= 128(1.25) = 160ms

ECW, w.c.

= (128+128)(0.75) = 192ms

EOW, w.c

= 32ms

owmin

Figure 6 Window watchdog timing definition

Figure 6 shows some guideline s for designing the watchdog trigger timing taking the oscillator deviation of different devices into account. Of importance is the maximum (w.c.) of the closed window and the minimum of the open window in which the trigger has to occur.

The length of the OW and CW can be modified by SPI command. If a change of the window length is desired during the Watchdog function is operating please send the SPI command with the new tim ing wit h a ’Watchd og tri gger Bit’ D1 5=1.In th is case the next CW will directly start with the new length.

A minimum time gap of > 1/48 of the actual OW/CW time between a ’Watchdog disable’ and ’Watchdog enable’ SPI-command should be maintained. This allows the internal Watchdog counters to be resetted. Thus after the enable command t he Watchdog will start properly with a full CW of the adjusted length.

Data Sheet, Rev. 1.31 14 2004-10-12

Perfect triggering after Power on Reset

Q_LDO1

Rth1

RES

TLE 6361 G

Watchdog

window

with WD-

trig=1

ERR

Incorrect triggering

Watchdog

window

CW OW

with WD-

trig=1

1) 2)

CW OW CW OW CW CW OW

1) Pretrigger

2) Missing trigger

Legend: OW = Open window

CW = Closed window

Figure 7 Window watchdog timing

Figure 7 gives some timing information about the window watchdog. Looking at the upper signals the perfect triggering of the watchdog is shown. When the 5V linear regulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before

Data Sheet, Rev. 1.31 15 2004-10-12

TLE 6361 G

the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect on the reset line a nd/or error pin is ob served. With the miss ing watchdog trigger sign al the error signal turns low immediately where the reset is asserted after another delay of half the closed window time .

Also shown in the figure are two typica l failure modes, one pretrigger an d one missing signal. In both cases the error s ignal will go low immedia tely the fai lure is detected with the reset following after the half closed window time.

2.10 Overtemperature Protection

At a chip temperature of more than 130° an error and temperature flag is set and can be read through the SPI. The device is switched off if the device reaches the overtemperature threshold of 170°C. The overtemperature shutdown has a hysteresis to avoid thermal pumping.

2.11 Power Down Mode

The TLE 6361 G is started by a st atic hig h signal at the wake input or a h igh p uls e w ith a minimum of 50 µs du ration a t the Wake i nput (p in 34). In ord er t o avoid instabi liti es of the device voltages applied to the Wake pin (pin 34) have to have a certain slope, i.e. 1V/3µs. Voltages in the range between the turn on and turn off thresholds for a few 100µs must be avoided!

By SPI command (“Sleep”-bit, D8, equals zero) all voltage regulators including the switching regulator except the standby regulator can be turned off completely only if the wake input is low. In the case the Wake input is permanently connected to battery the device cannot be turned off by SPI command, it will always turn on again. For stable “on” operation of the devi ce th e “Sleep ”-b it, D8 has to be set to high at ea ch SPI cycle!

When powering the device again after power down the status of the SPI controlled devices (e.g. trackers, watc hdog etc.) depends on th e output voltage on Q_LDO1. D id the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section) is set otherwise the last SPI command defines the status.

2.12 Serial Peripheral Interface

A standard 16bit SPI is available for control and diagnostics. It is capable to operate in a daisy chain. It can be written or read by a 16 bi t SPI interfac e as well as by an 8 bit SPI interface.

The 16-bit control word (write bit assignment, see figure 8) is read in via the data input DI, synchronous to the clock i npu t CLK s upp lied by th e µC . The d iagn osi s w ord ap pea rs in the same way synchronou sly at the data output DO (read bit assignme nt, see figure 9), so with the first bit shifted on the DI line the first bit appears on the DO line.

Data Sheet, Rev. 1.31 16 2004-10-12

TLE 6361 G

The transmission cycle begins when the TLE 6361 G is selected by the “not chip select” input CS at the DI line becomes the new control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to figures 10 to 13.

The SPI will be reset to d efault valu es given i n the follow ing table “write bit me aning” if the RAM good flag of Q_LDO1 indic ates a cold start (lower output voltage th an 3.3V). The reset will be active as long as the power on reset is present so during the reset delay time at power up no SPI commands are acceptable.

The register content of the SPI - including watchdog timings and reset delay timings - is maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not decrease below 3.3V).

2.12.1 Write mode

(H to L). After the CS input returns from L to H, the word that has been read in

The following tables s how the bit assignment to the different control functions, how to change settings with the right bit combination and also the default status at power up.

2.12.2 Write mode bit assignment

BIT

Name

Default

WD_OF

NOT

assigned

1 000000X 1 0100001

control

T1-

T2-

control

T6-

T4-

control

T5-

T6-

sleep WD-Trig

control

WD_OF

WD 2WD 1reset 2reset 1

D 15D8 D9 D10 D11 D12 D13 D1 4D7DO D1 D2 D3 D4 D5 D6

Figure 8 Write Bit assignment

Write Bit meaning Function Bit Combination Default

Not assigned D1 X X Tracker 1 to 6 - control:

turn on/off the individual trackers

D2 D3

0: OFF 1: ON

D4 D5 D6 D7

Power down: send device to sleep

Data Sheet, Rev. 1.31 17 2004-10-12

D8 0: SLEEP

1: NORMAL

TLE 6361 G

Write Bit meaning Function Bit Combination Default

Reset timing: Reset delay time t

valid at warm start

RES

Window watchdog timing: Open window time t closed window time t

and

valid at warm start

Window watchdog function: Enable /disable window watchdog

Window watchdog trigger: Enable / disable window watchdog trigger

2.12.3 Read mode

D10D11 00: 64ms

10: 32ms 01: 16ms 11: 8ms

D12D13 00: 128ms

10: 64ms 01: 32ms 11: 16ms

D0D9D14 010: OFF

1xx: ON x0x: ON xx1: ON

D15 0: not triggered

1: trigger ed

111

Below the status information word and the bit assignments for diagnosis are shown.

2.12.3.1Read mode bit assignment

BIT

Name

Default

warn

T1-

status

RAM

Good 1

temp_

ERROR

0 0000000 0 1000000

T6-

T5-

T4-

T3-

T2-

RAM

Good 2

Window

R-Error3R-Error2R-Error1

Error

D 15D8 D9 D10 D11 D12 D13 D14D7DO D1 D2 D3 D4 D5 D6

DC/DC

status

Figure 9 Read Bit assignment

Error bit D0: The error bit indicates fail function and turns high if the temperature prewarning, the

watchdog error is active, further if one RAM good ind icates a cold start or if a voltage tracker does not settle within 1ms when it is turned on. In addition to the error indication by software the ERR

pin atcs as a hardware error flag.

Data Sheet, Rev. 1.31 18 2004-10-12

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