INFINEON TLE 6263 User Manual

Final Datasheet, Version 2.08, 2004-06-07

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System Basis Chip
TLE 6263

Integrated
LS CAN, LDO and HS Switch

Automotive and
Industrial

Never stop thinking.

CAN-LDO-ASIC TLE 6263

Final Datasheet

1Features

• Standard fault tolerant differential CAN-transceiver

• Bus failure management

• Low power mode management

• Receive only mode for CAN

• CAN data transmission rate up to 125 kBaud

• Low-dropout voltage 5V regulator

• High side switch

• 2 wake-up inputs

• Power on and under-voltage reset generator

• Window watchdog

• Fail-safe output

• Early warning feature (V

• Sense comparator input (V

warning)

CC

INT

warning)

• Standard 8 bit SPI-interface

• Flash program mode

• Wide input voltage range

• Wide temperature range

• Enhanced power P-DSO-Package

P-DSO-28-18
Enhanced Power

Type Ordering Code Package

TLE 6263 G Q67007-A9465 P-DSO-28-18

2 Description

The TLE 6263 is a monolithic integrated circuit in an enhanced power P-DSO-28-18
package. The IC is optimized for use in advanced automotive electronic control units for
body and convenience applications.

To support this applications the TLE 6263 covers the main smart power functions such
as failure tolerant low speed CAN-transceiver for differential mode data transmission,
low dropout voltage regulator (LDO) for internal and external 5V supply as well as a SPI
(serial peripheral interface) to control and monitor the IC. Further there are integrated
additional features like a high side switch that can be used e.g. for cyclic supply of an
external wake-up circuitry, two wake-up inputs, a window watchdog circuit with fail safe
output as well as a reset and early warning feature.

The IC is designed to withstand the severe conditions of automotive applications.

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3 Pin Configuration

(top view)

Final Datasheet TLE 6263

TxD

RxD

WK2

WK1

GND GND

GND

GND GND

GND

1

2

(enhanced power package)

3

4

5

6

7

8

9

P-DSO-28-6

28

27

26

25

24

23

22

21

20

INT

RTH

CANHRO

RTL

CANL

GND

GND

DO

CLK

CSN

DI

OUTHS

10

11

12

13

14

19

18

17

16

15

V

CC

V

CI

FSO

SI

V

S

Figure 1: Pin Configuration TLE 6263 G (top view)

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Final Datasheet TLE 6263

4 Pin Definitions and Functions

Pin No. Symbol Function

1TxDTransmit data input; integrated pull up;

LOW: bus becomes dominant, HIGH: bus becomes recessive

2RxDReceive data output; push-pull output;

LOW: bus becomes dominant, HIGH: bus becomes recessive

3ROReset output; open drain output, integrated pull up, active low

4

WK2 Wake-Up input 2; for detection of external wake-up events, edge

sensitive, in sleep mode monitored by cyclic sense feature when
selected; weak pull up (2µA) to avoid unwanted wake ups

5

WK1 Wake-Up input 1; for detection of external wake-up events, edge

sensitive, in sleep mode monitored by cyclic sense feature when
selected; weak pull up (2µA) to avoid unwanted weak ups

6, 7, 8, 9,
20, 21,

GND Ground; to reduce thermal resistance place cooling areas on

PCB close to this pins.

22, 23

10 DO SPI data output; this tri-state output transfers diagnosis data to

the control device. Serial data transfered from DO is a 8 bit
diagnosis word with the Least Significant Bit (LSB) transmitted
first. The output will remain 3-stated unless the device is selected
by a LOW on Chip-Select-Not (CSN). DO will accept data on the
rising edge of CLK-signal; see table 4, 5, 6 for Diagnosis protocol

11 CLK SPI clock input; clocks the shiftregister; CLK has a pull down

input, active HIGH, and requires CMOS logic level inputs

12 CSN SPI chip select not input; CSN is a pull up input, active LOW,

serial communication is enabled by pulling the CSN terminal low;
CSN input should only be transitioned when CLK is low; CSN has
an internal active pull up and requires CMOS logic level inputs

13 DI SPI data input; receives serial data from the control device;

serial data transmitted to DI is a 8 bit control word with the Least
Significant Bit (LSB) being transferred first: the input has a pull
down input, active HIGH, and requires CMOS logic level inputs;
DI will accept data on the falling edge of CLK-signal; see table 3
for input data protocol

14 OUTHS High side switch output; controlled via SPI, in sleep mode

controlled by internal cyclic sense function when selected

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Final Datasheet TLE 6263

4 Pin Definitions and Functions (cont’d)

Pin No. Symbol Function

15 VS Power supply input; block to GND directly at the IC with ceramic

capacitor

16 SI Sense comparator input; for monitoring of external voltages, to

program the detection level connect external voltage divider

17 FSO Fail safe output; to supervise and control critical applications,

high when watchdog is correctly served, LOW at any reset
condition, open drain output, internal pull up, active LOW

18 V

19 V

CI

CC

Internal voltage supply; for stabilization of internal power
supply, block to GND with an external capacitor C

≥ 100 nF

VI

Voltage regulator output; for 5V supply, to stabilize block to
GND with an external capacitor C

≥ 100 nF

Q

24 CANL CAN-L bus line; LOW in dominant state

25 RTL CANL-Termination output; connect to CANL bus line via

termination resistor

26 CANH CAN-H bus line; HIGH in dominant state

27 RTH CANH-Termination input; connect to CANH bus line via

termination resistor

28

INT Interrupt output; to monitor wake-up events or valid sense input

condition; integrated pull up resistor; active LOW

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5 Functional Block Diagram

Final Datasheet TLE 6263

V

BAT

V

INT

RTL

CA NH

CA NL

RTH

CI

SI

Vcc

Vs

Vcc

Charge

Pump

Band

Gap

Early Warning

/ V

superv isor

S

H Output Stage

L Output Stage

Vcc

Driv e +

Protection

OUTHS

CSN

CLK

SPI

DI

DO

V

CC

-

+

Standby / Sleep Control

Dr iv er

Temp

Pr o t e c t

Time Bas e

Res et

Gene ra tor

+

Watchdog

CA N

Vcc

Vcc

Vcc

Vcc

Vcc

Vcc

RO

FSO

WK1

WK2

TxD

Filter

Re c ei v e r

Fail Management

Input
Stage

Rx D

CA N Fail De t ec t

GND

Figure 2: TLE 6263 G Functional Bloc Diagram

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Final Datasheet TLE 6263

6 Circuit Description

The TLE 6263 is a monolithic IC, which incorporates a failure tolerant low speed CAN­transceiver for differential mode data transmission, a low dropout voltage regulator for
internal and external 5V supply as well as a SPI (serial peripheral interface) to control
and monitor the IC. Further there are integrated a high side switch, two wake-up inputs,
a window watchdog circuit with fail safe output as well as a reset circuit and early warning
function. Figure 2 shows a schematic block diagram of the TLE 6263. Table 1 shows
the status of the different chip features during the four main operation modes.

Table 1: Truth table of the TLE 6263

Feature normal mode receive-only

mode

V

CC

Reset

Watchdog

Fail safe output

-Fail

2)

V

INT

Sense input

Wake-up 1 / 2

HS-switch

4)

HS-cyclic-sense

SPI

CAN transmit

CAN receive

RTL output

ON ON ON OFF

ON ON ON OFF

ON ON

ON ON

ON ON ON ON

ON ON ON OFF

3)

ON

ON ON ON OFF

4)

OFF OFF ON ON

ON ON ON OFF

ON OFF OFF OFF

ON ON OFF OFF

switched to Vcc switched to

ON

Vcc

3)

stand-by

V

bat

mode

1)

ON

5)

ON

ON ON

switched to
Vs

sleep

mode

OFF

OFF

switched to
Vs

RxD output

INT output

1)

at low VCC output current only active when watchdog undercurrent function is not activated

2)

can only be monitored in V

3)

no wake-up interrupt generated, logic level status monitored via SPI

4)

only active when selected via SPI

5)

if watchdog under-current function active, than FSO = low

L = bus dominant;
H = bus recessive

active low early
warning

-stand-by mode via SPI

bat

L = bus dominant;
H = bus recessive

active low early
warning for V
and V

CC

INT

active low wake-up
interrupt

active low early
warning

low

low

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Final Datasheet TLE 6263

6.1 Operation Modes

The TLE 6263 offers four different operation modes that are controlled via the SPI
interface (NSTB= SPI Input Bit3, ENT=SPI Input Bit2): the normal operation mode, the

receive-only mode, the V

stand-by mode and the sleep operation mode. Please see

bat

the state diagram (figure 3).

Normal and Receive only Mode

In the normal operation mode both is possible, receiving and transmitting of messages,
in the receive-only mode (RxD-only mode) the output stages are disabled which doesn’t
allow the CAN controller to send a message to the bus. In the state diagram (figure 3),

is the status of the voltage regulator.

V

CC

SPI Input Bits:
IBit2 = ENT
IBit3 = NSTB

2)

NSTB 0

Power

Down

Normal Mo de

NSTB

ENT

11

2)

ENT 0

NSTB

2)

RxD-Only

ENT

10

2)

NSTB

2)

ENT

Sleep Mode

Sleep

ENT

NSTB

01

HS switch = OFF

1)

after 64ms1) after 500µs

V

CC

ON

ENT 1

V

CC

ON

0
1

V

CC

OFF

2)

ENT11

2)

NSTB

or

V

CC

2)

NSTB 1

Start Up

Power Up

NSTB

0

V

RT

2)

NSTB
ENT

or

V

V

NSTB

00

RxD = LOW if a wake up
occured by WK1, WK2
or CAN message

Wake Up =

transition on

WK1 or WK 2

for t > t

WU

or

CAN message

2)

ENT 1

CC

Stand-By

bat

ENT

0
0

V

RT

1)

V
ON

after 500µs

CC

1)

after 64ms

V

Stand-By Mode

bat

HS cyclic

sense

ENT

NSTB

01

HS Switch = ON

V
ON

CC

HS cyclic

sense

ENT

NSTB

01

HS Switch = ON

V

OFF

CC

1)

automatic repeated transition only if
HS cycl sense feature is s elected
by SPI IBit 4

2)

NSTB and ENT are bot h SPI Input
Bits (IBits)

Figure 3: State Diagram

V

stand-by mode and sleep mode

bat

In the V

stand-by mode and sleep mode the RTL output voltage is switched to VS.

bat

Both modes are low power modes. In the sleep mode the whole application is switched

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Final Datasheet TLE 6263

off by disabling the voltage regulator. That allows the total current consumption to drop
down to less than 100 µA.

When a reset occurs, due to false watchdog triggering, the TLE6263 automatically
switches from normal mode or receive-only mode respectively, to the V
mode. If a watchdog reset occurs in the V

stand-by mode the IC remains in this mode.

bat

stand-by

bat

In sleep mode a wake-up at any of the wake-up inputs as well as via the bus lines
(CANH or CANL) automatically sets the TLE 6263 in V

stand-by mode. In the V

bat

bat

stand-by mode a wake-up is monitored by setting the output RxD low. This feature
works as a flag, to indicate a wake event to the microcontroller. To send and to receive
messages, the CAN-transceiver has to be set to normal operation mode by the
microcontroller.

In case the IC shall directly be set back to sleep mode after a wake-up, an internal wake­flip-flop has to be reseted via the SPI. Therefore IBIT1 has to be set high and then low
again by a second SPI transmission. A transition from the V

stand-by mode to the

bat

normal mode or receive-only mode respectively, automatically resets the wake-flip-flop.

6.2 Low Dropout Voltage Regulator

The integrated low dropout voltage regulator is able to drive the internal loads (e.g.
CAN-circuit) as well as external 5V loads. Its output voltage tolerance is better than ±
2%. The maximum output current is limited to 110 mA.

An external reverse current protection is recommended at the pin Vs to prevent the
output capacitor from being discharged by negative transients or low input voltage.

Stability of the output voltage is guaranteed for output capacitors C
nevertheless it is recommended to use capacitors C

≥ 10 µF to buffer the output

Q

≥ 100 nF,

Q

voltage and therefore improve the reset behavior at input voltage transients.

To stabilize the internal supply a capacitor C

≥ 100 nF directly connected to the pin V

VI

CI

is required.

6.3 CAN Transceiver

The TLE 6263 is optimized for low speed data transmission up to 125 kBaud in
automotive applications. Figure 4 shows the principle configuration of a CAN
network.Normally a differential signal is transmitted and received respectively. When a
bus wiring failure (see table 2) is detected the device automatically switches to a
dedicated CANH or CANL single-wire mode to maintain the communication if
necessary. Further a receive-only mode is implemented that allows a separate CAN
node diagnosis. During normal and RxD-only mode, RTL is switched to V
to GND. During V

stand-by and the cyclic wake mode, RTL is switched to VS and RTH

bat

and RTH

CC

to GND.

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Final Datasheet TLE 6263

Controller 1

RxD1

Transceiver1

TxD1

BUS Line

Controller 2

RxD2

Transceiver2

TxD2

Figure 4: CAN Network Example

Receive-only Mode

The receive only mode is designed for a special test procedure to check the bus
connections. Figure 5 shows a network consisting of 5 nodes. If the connection between
node 1 and node 3 shall be tested, the nodes 2,4 and 5 are switched into receive only
mode. Node 1 and node 3 are in normal mode. If node 1 sends a message, node 3 is the
only node which can acknowledge the message, the other nodes can only listen but
cannot send an acknowledge bit. If node 1 receives the acknowledge bit from node 3,
the connection is OK.

5

1

2

4

3

Figure 5: Testing the Bus Connection in Receive-only Mode

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Final Datasheet TLE 6263

Electromagnetic Emmision (EME)

To reduce radiated electromagnetic emission (EME), the dynamic slopes of the CANL
and CANH signals are both limited and symmetric. This allows the use of an unshielded
twisted or parallel pair of wires for the bus. During single-wire transmission (one of the
bus lines is affected by a bus line failure) the EME performance of the system is
degraded from the differential mode.

6.4 Bus Failure Management

There are 9 different CAN bus wiring failures defined by the ISO 11519-2/ISO 11898-3
standard. These failures are devided into 7 failure groups (see Table 2). The difference
between ISO11898-3 and ISO 11519-2 is also shown in Table 2. When a bus wiring
failure is detected the device automatically switches to a dedicated CANH or CANL
single-wire mode to maintain the communication if necessary. Therefore it is equipped
with one differential receiver and four single ended comparators (two for each bus line).

To avoid false triggering by external RF influences, the single wire modes are activated
after a certain delay time. As soon as the bus failure disappears the transceiver switches
back to differential mode after another time delay.

The differential receiver threshold is set to typ. -2.5V. This ensures correct reception in
the normal operation mode as well as in the failure cases 1, 2, 3a(6a) and 4(5) with a
noise margin as high as possible. When one of the bus failures 3(6), 5(4), 6(3), 6a(3a),
and 7 is detected, the defective bus wire is disabled by switching off the affected bus
termination and output stage. The failure cases in brackets() are the failure cases
according to ISO 11898-3. Simultaneously the multiplexing output of the receiver circuit
is switched to the unaffected single ended comparator

The bus failures are monitored via the diagnosis protocoll of the SPI. A general indication
of a CAN failure during normal mode at CANH or CANL is reported by OBIT 4 and 5. It
is also possible to distinguish 6 CAN bus failures or failure groups on the SPI output bits
3 to 7 in the RxOnly mode(see Table 2 and 5). The failures are reported until
transmission of the next CAN word begins.

In case the transmission data input TxD is permanently dominant, both, the CANH and
CANL transmitting stage are disabled after a certain delay time t

. This is necessary

TxD

to prevent the bus from being blocked by a defective protocol unit or short to GND at the
TxD input.

In order to protect the transceiver output stages from being damaged by shorts on the
bus lines, current limiting circuits are integrated. The CANL and CANH output stage
respectively are protected by an additional temperature sensor, that disables them as
soon as the junction temperature exceeds the maximum value. In the temperature shut­down condition of the CAN output stages receiving messages from the bus lines is still
possible.

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Table 2: CAN bus line failure cases

Final Datasheet TLE 6263

failure
#

failure description
according to ISO 11898-3

failure description
according to 11519-2

1 CANH line interrupted CANL line interrupted

2 CANL line interrupted CANH line interrupted

3 CANH shorted to Vbat CANL shorted to Vbat

3a CANH shorted to Vcc CANL shorted to Vcc

4 CANL shorted to GND CANH shorted to GND

5 CANH shorted to GND CANL shorted to GND

6 CANL shorted to Vbat CANH shorted to Vbat

6a CANL shorted to Vcc CANH shorted to Vcc

7 CANL shorted to CANH CANL shorted to CANH

6.5 SPI (serial peripheral interface)

The 8-bit wide programming word (input word, see table 3) is read in via the data input
DI, and this is synchronized with the clock input CLK supplied by the µC. The diagnostic
information depends on the operation mode. The internal latches for the V

-stand-by

bat

diagnosis are reseted when leaving this mode.

Table 3, Input Data Protocol Table 4, Diagnosis Data Protocol
all modes normal mode

IBIT OBIT

7 Watchdog Undercurrent

7 HS UV / Temp-Shut Down

Control

6Set V

-Fail + VCC Fail

INT

6HS Overcurrent

Flag

5 OUTHS ON 5 CANL bus fail

4 OUTHS Cyclic Sense 4 CANH bus fail

3 Not Standby 3 WK2 logic level

2 Enable Transmit 2 WK1 logic level

1 Reset Internal WK-FF 1 Window Watchdog Reset

0 Watchdog Trigger 0 Temperature Prewarning

H= ON
L= OFF

H= ON
L= OFF

Version 2.08 12 2004-06-07