INFINEON TLE 6262 G User Manual

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Fault Tolerant CAN - LDO TLE 6262 G

Final Data Sheet

1Overview

1.1 Features

• Standard fault tolerant differential CAN-transceiver (TLE6254 LS CAN cell)

• Bus failure management

• Low power mode management

• CAN data transmission rate up to 125 kBaud

• Low-dropout voltage regulator 5V ± 2%

• Two Low Side Switches

• Three High Side Switches

• Power on and under-voltage reset generator

• Vcc supervisor

• Window watchdog

• Programable time base

• Integrated fail-safe mechanism

• Standard 16 bit SPI-Interface

• Wide input voltage and temperature range

• Enhanced power P-DSO-Package

P-DSO-28-6 Enhanced Power

Type Ordering Code Package

TLE 6262 G on request P-DSO-28-6

Description

The TLE 6262 G is a monolithic integrated circuit in a P-DSO-28-6 package, which incorporates a failure tolerant low speed CAN-transceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a 16 bit SPI interface to control and monitor the IC. Further there are integrated three high side switches, two low side switches, a window watchdog circuit and a reset circuit. Both, the window watchdog and reset function are referring to a time base that is programmable via an external resistor.

The IC is designed to withstand the severe conditions of automotive applications.

1 version: 2.03 date: 2002-03-20

1.2 Pin Configuration

(top view)

Final Data TLE 6262 G

OSC

PWM

TxD

RxD

Vcc

GND

CANH

RTH

CANL

RTL

GND GND

GND

GND GND

GND

Figure 1

OUTH1

OUTL1

OUTL2

OUTH2

OUTH3

P-DSO-28-6

(enhanced power package)

CLK

CSN

2 version: 2.03 date: 2002-03-20

Final Data TLE 6262 G

1.3 Pin Definitions and Functions

Pin No. Symbol Function

1CANHCAN-H bus line; HIGH in dominant state

2RTHTermination input for CANH

3ROReset output; open drain output; integrated pull up; active low

4CANLCAN-L bus line; LOW in dominant state

5RTLTermination input for CANL

6, 7, 8, 9, 20, 21,

GND Ground; to reduce thermal resistance place cooling areas on

PCB close to this pins.

22, 23

10 OUTH1 High side output 1; controlled via PWM input and/or SPI input,

short circuit protected

OUTL1 Low side output 1; SPI controlled, with active zener

12 OUTL2 Low side output 2; SPI controlled, with active zener

13 OUTH2 High side output 2; SPI controlled

14 OUTH3 High side output 3; SPI controlled, in low power mode controlled

by internal autotiming function if selected

VS Power supply; block to GND directly at the IC with ceramic

capacitor

16 CSN SPI interface chip select not; CSN is an active low input; serial

communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs

17 DO SPI interface data out; this tristate output transfers diagnosis

data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see table 3 for diagnosis protocol

18 DI SPI interface data in; receives serial data from the control

device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see table 2 for input data protocol

19 CLK SPI interface clock input; clocks the shiftregister; CLK has an

internal active pull down and requires CMOS logic level inputs

3 version: 2.03 date: 2002-03-20

1.3 Pin Definitions and Functions (cont’d)

Pin No. Symbol Function

Final Data TLE 6262 G

24 V

Output voltage regulator; 5V logic supply, block to GND with an 100nF external ceramic capacitor directly at the IC + external capacitor C

³ 22 µF

25 RxD CAN Receive data output;

26 TxD CAN Transmit data input; integrated pull up

27 PWM Pulse width control; for high side switch 1

28 OSC Oscillator input; time base for power on reset, watchdog window

and stand by timer for HS3, to program connect external resistor to GND

4 version: 2.03 date: 2002-03-20

1.4 Functional Block Diagram

Final Data TLE 6262 G

OUTL1

PWM

RTL

CANH

CANL

RTH

Charge

Pump

UVLO

Band

Gap

Protection + Drive

POR

H Output Stage

L Output Stage

Drive

Switch

Fail Detect

SPI

Timer

Reset

Generator

Window

Watchdog

CAN

Standby / Sleep Control

Driver

Temp.

Protect

OUTL2

OUTH1

OUTH2

OUTH3

CSN

CLK

Vcc

OSC

TxD

Figure 2

Filter

Receiver

CAN Fail Detect

Input

Fail Management

Stage

GND

RxD

5 version: 2.03 date: 2002-03-20

Final Data TLE 6262 G

1.5 Circuit Description

The TLE 6262 G is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a SPI interface to control and monitor the IC. Further there are integrated three high side switches, two low side switches, a window watchdog circuit and a reset circuit. Both, the window watchdog and reset function are referring to a time base that is programmable via an external resistor.

Figure 2 shows a block schematic diagram of the TLE 6262 G

Table 1: mode truth table

Feature normal mode Receive-only

mode

ON ON ON

BAT

mode

stand-by

Reset ON ON ON

Watchdog ON

SPI ON ON ON

CAN transmit ON OFF OFF

CAN receive ON ON OFF

OUTHS 1

OUTHS 2

OUTHS 3

OUTHS3-auto timing

OUTLS 1

OUTLS 2

at low VCC output current only active when watchdog undercurrent function is not activated

a bus wake-up is monitored by setting the RxD output low

only active when selected via SPI

also active when driven via the PWM input

automatically disabled when a reset occurs

automatically disabled when a reset or watchdog reset respectively, occurs or the watchdog is disabled

by the undercurrent function

3) 4) 5)

3) 5)

3) 6)

3) 5)

ON ON ON

OFF ON ON

ON ON ON

6 version: 2.03 date: 2002-03-20

Final Data TLE 6262 G

CAN Transceiver

The TLE 6262 is optimized for low speed data transmission up to 125 kbaud in automotive applications. Normally a differential signal is transmitted or received respectively. When a bus wiring failure (see table 4) is detected the device automatically switches to a dedicated CANH or CANL single-wire mode to maintain the communication if necessary. Therefore it is equipped with one differential receiver and four single ended comparators (two for each bus line). To avoid false triggering by external RF influences the single wire modes are activated after a certain delay time. As soon as the bus failure disappears the transceiver switches back to differential mode after another time delay. The bus failures are monitored via the diagnosis protocol of the SPI. Therefore it is possible to distinguish 6 CAN bus failures or failure groups on the bits 8 to 13 (see table

3).

To reduce EMC caused by the transceiver the dynamic slopes of the CANL and CANH signals are both limited and symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the bus. During single-wire transmission (bus-failure) the EMC performance of the system is degraded from the differential mode.

The differential receiver threshold is set to typ. -2.8 V. This ensures correct reception in the normal operation mode as well as in the failure cases 1, 2, 3a and 4 with a noise margin as high as possible. When one of the bus failures 3, 5, 6, 6a, and 7 is detected, the defective bus wire is disabled by switching off the affected bus termination and output stage.

The CAN-transceiver offers three different operation modes that are controlled via the SPI: the normal operation mode, Receive-only mode and V see the state diagram (figure 3). In the V switched to V

stand-by mode the RTL output voltage is

bat

stand-by mode. Please

bat

In case of a wake-up via the bus lines or one of the bus lines respectively, the TLE 6262 automatically sets the RxD output LOW. To send respectively receive messages the CAN-transceiver can now be set in normal operation mode or receive-only mode by the microcontroller.

When a reset occurs the transceiver circuit is automatically switched to V

-stand-by

bat

mode because the SPI input bits are automatically set LOW for this event.

A thermal shutdown of the CAN-transceiver circuit is monitored via the SPI diagnosis bit 15.

7 version: 2.03 date: 2002-03-20

Normal Mode

Final Data TLE 6262 G

Start Up

Power Up

NSTB 0

NSTB

ENT

ENT 0 ENT 1

RxD-Only

NSTB

ENT

NSTB ENT

0 1

Go- To-Sleep

Mode

NSTB

ENT

NSTB V

NSTB

NSTB ENT

1 1

0 or V

ENT 1

NSTB ENT

Stand-By

bat

NSTB

ENT

0 0

Figure 3: State Diagram

Low Dropout Voltage Regulator

The TLE 6262 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance is less than ± 2%. In addition the regulator circuit drives the internal loads like the CANtransceiver circuit.

An external reverse current protection is recommended to prevent the output capacitor from being discharged by negative transients or low input voltage.

Stability of the output voltage is guaranteed for output capacitors C

³ 100 nF.

VCC

Nevertheless a lot of applications require a much larger output capacitance to buffer the output voltage in case of low input voltage or negative transients. Furthermore the due function of e.g. the reset and 3V-supervisor circuit are supported by a larger output capacitance because of their reaction times. Therefore a output capacitance C

³ 10 µF is recommended.

VCC

8 version: 2.03 date: 2002-03-20

Final Data TLE 6262 G

SPI (serial peripheral interface)

The 16-bit wide programming word or input word (see table 1) is read in via the data input DI, and this is synchronized with the clock input CLK supplied by the µC. The diagnosis word appears synchronously at the data output DO (see table 3).

The transmission cycle begins when the chip is selected by the chip select not input CSN (H to L). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tristate status at this point.

For details of the SPI timing please refer to figure 3 to 7.

Oscillator

All internal delay times are referring to the internal oscillator frequency, which is set by an external resistor from pin OSC to GND. The oscillator frequency and the resulting internal cycling time can be calculated by the equations:

´10 HzW[]

OSC

------------=

OSC

CYL

28 45,

-----------------------------------------=

Window Watchdog, Reset and 3V-Supervisor

When the output voltage V

exceeds the reset threshold voltage VRT the reset output

RO is switched HIGH after a delay time of 16 cycles. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an under-voltage condition of the output voltage (V LOW again. The LOW signal is guaranteed down to an output voltage V

< VRT) appears, the reset output RO is switched

³ 1V. Please

refer to fig.11, reset timing diagram.

Should the output voltage fall short of the 3V-supervisor threshold V

an internal flip-

flop is set LOW. The SPI diagnosis bit 7 monitors this. In normal operation this flip-flop has to be activated via the SPI input bit 7. This feature is useful e.g. to monitor that the RAM data of the microcontroller might be damaged or the application is connected to V the first time.

After the above described delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is started by opening a long open window of 32 cycles. Now the microcontroller has to service a watchdog trigger signal via the SPI interface (input bit 0). A watchdog trigger is detected as a falling edge by sampling for 2 cycles a HIGH followed by 2 cycles LOW of the SPI input bit 0. The long open window ensures a simple and fast

9 version: 2.03 date: 2002-03-20

Final Data TLE 6262 G

synchronization of the TLE 6262 watchdog timing to the watchdog services of the microcontroller.

After the first trigger the watchdog has to be serviced by meeting an open window of 20 cycles that follows a closed window of 12 cycles. A correct watchdog service immediately results in starting the next closed window. Please refer to fig. 10, watchdog timing diagram.

If the trigger signal does not meet the open window (trigger to early or to late) the reset output RO is set LOW for a period of 4 cycles. Afterwards a long open window is started again. In addition, the SPI diagnosis bit 2 is set HIGH to monitor a watchdog reset.

Both, the undervoltage reset and the watchdog reset are setting all SPI input bits LOW.

To avoid a cyclic wake-up of the microcontroller in low power mode (sleep mode) the watchdog circuit can be automatically disabled at low output currents (I

< I

CCWD

activate this feature the SPI input bit 8 has to be set HIGH. In this under-current mode the low side switches are switched off automatically by the TLE 6262 to guarantee failsave operation of the application. When the microcontroller returns back to normal mode

> I

CCWD

) the first closed window is transformed to an open window so that the total open window time is 32 cycles. This ensures a more simple and fast synchronization of the TLE 6262 watchdog timing to the watchdog services of the microcontroller.

). To

Flash program mode

To disable the watchdog feature a flash program mode is available. This mode is selected by applying a voltage of 6.8V < V

< 7.2V at pin PWM. This is useful e.g. if

PWM

the flash-memory of the micro has to be programmed and therefore a regular watchdog triggering is not possible. If the SPI is required in the flash program mode to change e.g. the mode of the TLE6262 the first input telegram has to be “00000000”.

High Side Switch 1

The high side output OUTH1 is able to switch loads up to 250 mA. Its on-resistance is

1.0 W typ. @ 25°C. This switch can be controlled either via the PWM input or the SPI input bit 1. When the input PWM is used it has to be enabled by setting the SPI input bit 11 HIGH. In case of both control inputs being active the PWM signal is masked by the SPI signal (see fig. 8, High Side Switch 1 Timing Diagram).

The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0 flags a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6262 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. Further OUTH1 is protected against short circuit and overload. The SPI diagnosis bit 1 indicates an overload of OUTH1. As soon as the under-voltage condition of the supply voltage is met (V V

UVOFF

), the switches are automatically disabled by the under-voltage lockout circuit.

10 version: 2.03 date: 2002-03-20

Final Data TLE 6262 G

This is flagged by the SPI diagnosis bit 3. Moreover the switches are disabled when a reset occurs.

High Side Switch 2

The high side output OUTH2 is able to switch loads up to 250 mA. Its on-resistance is

1.0 W typ. @ 25°C. This switch is controlled via the SPI input bit 2.

The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0 flags a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6262 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. As soon as the under-voltage condition of the supply voltage is met (V

< V

UVOFF

disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3. Moreover the switches are disabled when a reset occurs.

), the switches are automatically

High Side Switch 3

The high side output OUTH3 is able to switch loads up to 150 mA. Its on-resistance is

1.5 W typ. @ 25°C. This switch is controlled via the SPI input bits 3 and 4. To supply external wake-up circuits in low power mode (sleep mode or Vbat-stand-by mode), the output OUTH3 can be periodically activated by the internal oscillator circuit. For activating this feature the SPI input bits 3 and 4 have to be set HIGH. The autotiming period is 128 internal cycle times; the on-time is 2 cycles. In case of a watchdog reset the autotiming period may be shorter.

The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0 flags a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6262 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. As soon as the under-voltage condition of the supply voltage is met (V

< V

UVOFF

), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3. Moreover the switches are disabled when a reset occurs.

Low Side Switches 1/2

The two low side outputs OUTL1 and OUTL2 are able to switch loads up to 100 mA. Their on-resistance is 1.5 W (typ.) @ 25°C. This switches are controlled via the SPI input bits 5 and 6. In case of high inrush currents a built in zener circuit (typ. 37 V) activates the switches to protect them.

11 version: 2.03 date: 2002-03-20

Final Data TLE 6262 G

are giving a feedback about current status of OUTL1/OUTL2. As soon as the undervoltage condition of the supply voltage is met (V

< V

UVOFF

automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3. In addition the outputs OUTL1 and OUTL2 are also disabled when the watchdog is switched off in undercurrent state or when a reset occurs.

), the switches are

12 version: 2.03 date: 2002-03-20

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