INFINEON TDA5221 User Manual

Preliminary Specification, V 1.1, October 2004
TDA 5221
ASK/FSK Single Conversion Receiver Version 1.1
Wireless Control Components
Never stop thinking.
Edition 2004-10-20 Published by In fineon Technologies AG,
St.-Martin-Strasse 53, 81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
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circuits, descriptions and charts stated herein.
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Preliminary Specification, V 1.1, October 2004
TDA 5221
ASK/FSK Single Conversion Receiver Version 1.1
Wireless Control Components
Never stop thinking.
TDA 5221 Revision History: 2004-10-20 V 1.1
Previous Version: none Page Subjects (major changes since last revision)
We Listen to Your Comments
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TDA 5221
Table of Contents Page
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.2 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.5 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.9 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 ASK/FSK-Data Path Functional Description . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
T
4.1.3 AC/DC Characteristic s at
4.1.4 AC/DC Characteristics at T
4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3 Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
= 25°C . . . . . . . . . . . . . . . . . . . . . . . . . 33
AMB
= -40 to 105°C . . . . . . . . . . . . . . . . . . . . 39
AMB
Preliminary Specification 5 V 1.1, 2004-10-20
TDA 5221
Product Description

1 Product Description

1.1 Overview

The IC is a very low power consumption single chip FSK/ASK Superheterodyne Receiver (SHR) for the frequency band 300 to 340 MHz. The IC offers a high level of integration and n eeds only a few external components. The device c onta ins a l ow n ois e amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter w ith RSSI gene rator, a PLL FSK demod ulator , a data fil ter, an advanced data comparator (slicer) with selection between two threshold modes and a peak detector. Additionally there is a power down feature to save current and extend battery life, and two selectable alternatives of generating the data slicer threshold.

1.2 Features

Low supply current (Is = 6.4 mA typ. in FSK mode, Is = 5.6 mA typ. in ASK mode)
Supply voltage range 5V ±10%
Power down mode with very low supply current (50nA typ.)
FSK and ASK demodulation capability
Fully integrated VCO and PLL Synthesiser
ASK sensitivity better than -110 dBm over specified temperature range (- 40 to +105°C)
Selectable frequency ranges 300-320 MHz and 320-340 MHz
Switchable between two different frequency channels (see Section 2.4.3)
Limiter with RSSI generation, operating at 10.7MHz
2nd order low pass data filter with external capacitors
Data slicer with selection between two threshold modes (see Section 2.4.8)
FSK sensitivity better than -102 dBm over specified temperature range (- 40 to +105°C)

1.3 Application

Keyless Entry Systems
Remote Control Systems
Alarm Systems
Low Bitrate Communication Systems
Preliminary Specification 6 V 1.1, 2004-10-20
TDA 5221

2 Functional Description

2.1 Pin Configurat ion

VCC
LNI
LNO VCC
MI
MIX
IF O
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
TD A 5221
CRST1
TAGC
AGND
AGND
FSEL
DGND
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Functional Description
CRST2 PDW N PDO DATA 3VO UT THRES FFB OPP SLN SLP LIMX LIM SSEL MSEL
Figure 1 Pin Configuration
Preliminary Specification 7 V 1.1, 2004-10-20
TDA 5221
Functional Description

2.2 Pin Definition and Functions

Table 1 Pin Defintion and Function Pin
No.
1 CRST1 External Crystal
2 VCC 5V Supply 3 LNI LNA Input
Symbol Equivalent I/O Schematic Function
Connector 1
4.15V
1
50uA
57uA
3
500uA
4k
1k
Preliminary Specification 8 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
4TAGC AGC Time
4.3V
3uA
4
1k
1.4uA
1.7V
Constant Control
5 AGND Analogue
Ground Return
6 LNO LNA Output
5V
1k
6
7 VCC 5V Supply
Preliminary Specification 9 V 1.1, 2004-10-20
TDA 5221
.
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
8
9
MI
MIX
2k 2k
8
400uA
Mixer Input
1.7V
Complementary Mixer Input
9
10 AGND Analogue
Ground Return
11 FSEL Frequency
Selector
1
11
40k
12 IFO 10.7 MHz IF
Mixer Output
300uA
2.2V
12
60
4.5k
13 DGND Digital Ground
Return
Preliminary Specification 10 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
14 VDD 5V Supply (PLL
Counter Circuity)
15 MSEL ASK/FSK
Modulation Format Sector
1.2V
15
40k
16 SSEL Data Slicer
Reference Level Sector
1.2V
40k
Limiter Input
2.4V
17
16
LIM
18
LIMX
17
18
15k
330
15k
Complementary Limiter Input
75uA
Preliminary Specification 11 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
19 SLP Data Slicer
Positive Input
15uA
19
100
3k
80µA
20 SLN Data Slicer
Negative Input
5uA
20
10k
21 OPP OpAmp
Noninverting Input
5uA
21
200
22 FFB Data Filter
Feedback Pin
5uA
22
Preliminary Specification 12 V 1.1, 2004-10-20
100k
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
23 THRES AGC Threshold
Input
5uA
23
10k
24 3VOUT 3V Reference
Output
24
20k
3.1V
25 DATA Data Output
25
500
40k
26 PDO Peak Detector
Output
26
446k
Preliminary Specification 13 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
27 PDWN Power Down
27
220k
220k
Input
28 CRST2 External Crystal
Connector 2
4.15V
28
50uA
Preliminary Specification 14 V 1.1, 2004-10-20
TDA 5221

2.3 Functional Block Diagram

VCC
MI
68912 1718
LNI
3
TAGC
VCC
DGND
LNA
4
14
13
2,7 5,10
VCC AGND
RF
Figure 2 Block Diagram
IF
Filter
MIXLNO
IFO SLN
LIM LIMX
LIMITER
TDA 5221
OTA
: 128
: 2 VCO
Loop Filter
Φ
DET
: 129
11
FSEL

2.4 Functional Block Description

FSK
PLL Demod
: 2
MSEL
H=ASK
L=FSK
15
CRYSTAL
OSC
1
Crystal
-
+
­+
FFB
FSK ASK
28 27
Functional Description
OPP
SLP
22 21 19
20
16
SSEL
Logic
­25
CM
DATA
+
CP
+
-
+
DATA-
SLICER
OP
-
PEAK
PDO
DETECTOR
26
THRES
23
U
REF
AGC
Reference
Bandgap
Reference
PDWN
3VOUT
24

2.4.1 Low Noise Amplifier (LNA)

The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current consumption is 500µA. The gain can be reduce d by approxi mately 18 dB. The swit ching poi nt of this AGC ac tion can be determined externally b y applyi ng a thresh old volta ge at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 3.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scena rio to be expe cted du ring ope ration. The optim um ch oice of AGC time constant and the threshold voltage is described in Section 3.1.
Preliminary Specification 15 V 1.1, 2004-10-20
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