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Datasheet TDA5221 Datasheet (INFINEON)

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Preliminary Specification, V 1.1, October 2004
TDA 5221
ASK/FSK Single Conversion Receiver Version 1.1
Wireless Control Components
Never stop thinking.
Edition 2004-10-20 Published by In fineon Technologies AG,
St.-Martin-Strasse 53, 81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on tec hnology, del ivery terms and cond itions and prices please contact your nearest Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon T echnologies Representatives worldwide (www.infineon.com).
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Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon T echnologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Preliminary Specification, V 1.1, October 2004
TDA 5221
ASK/FSK Single Conversion Receiver Version 1.1
Wireless Control Components
Never stop thinking.
TDA 5221 Revision History: 2004-10-20 V 1.1
Previous Version: none Page Subjects (major changes since last revision)
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:
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TDA 5221
Table of Contents Page
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.2 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.5 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.9 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 ASK/FSK-Data Path Functional Description . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
T
4.1.3 AC/DC Characteristic s at
4.1.4 AC/DC Characteristics at T
4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3 Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
= 25°C . . . . . . . . . . . . . . . . . . . . . . . . . 33
AMB
= -40 to 105°C . . . . . . . . . . . . . . . . . . . . 39
AMB
Preliminary Specification 5 V 1.1, 2004-10-20
TDA 5221
Product Description

1 Product Description

1.1 Overview

The IC is a very low power consumption single chip FSK/ASK Superheterodyne Receiver (SHR) for the frequency band 300 to 340 MHz. The IC offers a high level of integration and n eeds only a few external components. The device c onta ins a l ow n ois e amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter w ith RSSI gene rator, a PLL FSK demod ulator , a data fil ter, an advanced data comparator (slicer) with selection between two threshold modes and a peak detector. Additionally there is a power down feature to save current and extend battery life, and two selectable alternatives of generating the data slicer threshold.

1.2 Features

• Low supply current (Is = 6.4 mA typ. in FSK mode, Is = 5.6 mA typ. in ASK mode)
• Supply voltage range 5V ±10%
• Power down mode with very low supply current (50nA typ.)
• FSK and ASK demodulation capability
• Fully integrated VCO and PLL Synthesiser
• ASK sensitivity better than -110 dBm over specified temperature range (- 40 to +105°C)
• Selectable frequency ranges 300-320 MHz and 320-340 MHz
• Switchable between two different frequency channels (see Section 2.4.3)
• Limiter with RSSI generation, operating at 10.7MHz
• 2nd order low pass data filter with external capacitors
• Data slicer with selection between two threshold modes (see Section 2.4.8)
• FSK sensitivity better than -102 dBm over specified temperature range (- 40 to +105°C)

1.3 Application

• Keyless Entry Systems
• Remote Control Systems
• Alarm Systems
• Low Bitrate Communication Systems
Preliminary Specification 6 V 1.1, 2004-10-20
TDA 5221

2 Functional Description

2.1 Pin Configurat ion

VCC
LNI
LNO VCC
MI
MIX
IF O
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
TD A 5221
CRST1
TAGC
AGND
AGND
FSEL
DGND
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Functional Description
CRST2 PDW N PDO DATA 3VO UT THRES FFB OPP SLN SLP LIMX LIM SSEL MSEL
Figure 1 Pin Configuration
Preliminary Specification 7 V 1.1, 2004-10-20
TDA 5221
Functional Description

2.2 Pin Definition and Functions

Table 1 Pin Defintion and Function Pin
No.
1 CRST1 External Crystal
2 VCC 5V Supply 3 LNI LNA Input
Symbol Equivalent I/O Schematic Function
Connector 1
4.15V
1
50uA
57uA
3
500uA
4k
1k
Preliminary Specification 8 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
4TAGC AGC Time
4.3V
3uA
4
1k
1.4uA
1.7V
Constant Control
5 AGND Analogue
Ground Return
6 LNO LNA Output
5V
1k
6
7 VCC 5V Supply
Preliminary Specification 9 V 1.1, 2004-10-20
TDA 5221
.
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
8
9
MI
MIX
2k 2k
8
400uA
Mixer Input
1.7V
Complementary Mixer Input
9
10 AGND Analogue
Ground Return
11 FSEL Frequency
Selector
1
11
40k
12 IFO 10.7 MHz IF
Mixer Output
300uA
2.2V
12
60
4.5k
13 DGND Digital Ground
Return
Preliminary Specification 10 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
14 VDD 5V Supply (PLL
Counter Circuity)
15 MSEL ASK/FSK
Modulation Format Sector
1.2V
15
40k
16 SSEL Data Slicer
Reference Level Sector
1.2V
40k
Limiter Input
2.4V
17
16
LIM
18
LIMX
17
18
15k
330
15k
Complementary Limiter Input
75uA
Preliminary Specification 11 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
19 SLP Data Slicer
Positive Input
15uA
19
100
3k
80µA
20 SLN Data Slicer
Negative Input
5uA
20
10k
21 OPP OpAmp
Noninverting Input
5uA
21
200
22 FFB Data Filter
Feedback Pin
5uA
22
Preliminary Specification 12 V 1.1, 2004-10-20
100k
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
23 THRES AGC Threshold
Input
5uA
23
10k
24 3VOUT 3V Reference
Output
24
20k
Ω
3.1V
25 DATA Data Output
25
500
40k
26 PDO Peak Detector
Output
26
446k
Preliminary Specification 13 V 1.1, 2004-10-20
TDA 5221
Pin
Symbol Equivalent I/O Schematic Function
Functional Description
No.
27 PDWN Power Down
27
220k
220k
Input
28 CRST2 External Crystal
Connector 2
4.15V
28
50uA
Preliminary Specification 14 V 1.1, 2004-10-20
TDA 5221

2.3 Functional Block Diagram

VCC
MI
68912 1718
LNI
3
TAGC
VCC
DGND
LNA
4
14
13
2,7 5,10
VCC AGND
RF
Figure 2 Block Diagram
IF
Filter
MIXLNO
IFO SLN
LIM LIMX
LIMITER
TDA 5221
OTA
: 128
: 2 VCO
Loop Filter
Φ
DET
: 129
11
FSEL

2.4 Functional Block Description

FSK
PLL Demod
: 2
MSEL
H=ASK
L=FSK
15
CRYSTAL
OSC
1
Crystal
-
+
­+
FFB
FSK ASK
28 27
Functional Description
OPP
SLP
22 21 19
20
16
SSEL
Logic
­25
CM
DATA
+
CP
+
-
+
DATA-
SLICER
OP
-
PEAK
PDO
DETECTOR
26
THRES
23
U
REF
AGC
Reference
Bandgap
Reference
PDWN
3VOUT
24

2.4.1 Low Noise Amplifier (LNA)

The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current consumption is 500µA. The gain can be reduce d by approxi mately 18 dB. The swit ching poi nt of this AGC ac tion can be determined externally b y applyi ng a thresh old volta ge at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 3.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scena rio to be expe cted du ring ope ration. The optim um ch oice of AGC time constant and the threshold voltage is described in Section 3.1.
Preliminary Specification 15 V 1.1, 2004-10-20
TDA 5221
Functional Description

2.4.2 Mixer

The Double Balanced Mixer down conve rts the i nput fre quenc y (RF) in th e range o f 31 0­350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-tage gain of approximately 21dB by utilising either high- or low-side injection of the local oscillator signal. In case the mixer is interfaced only single-ended, the unused mixer input has to be tied to ground vi a a c ap aci tor. The mixer is followed by a low pass filter w it h a c orn er frequency of 20MHz in order to su ppress RF s ignals to appe ar at the IF output (IFO pin). The IF output is internal ly c on si sti ng o f an em itte r fol lower that has a source impedance of approximately 330Ω to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry.

2.4.3 PLL Synthesizer

The Phase Locked Loo p syn thesi zer co nsist s of a VCO, an asy nchro nous d ivide r chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including sp iral ind uctors and vara ctor di odes. T he tu ning ran ge of the VCO was designed to guaran tee over produ ction spread and the specified tem peratu re range a receive frequency range between 300 and 340 MHz depending on whether high- or low-side injection of the local oscillator is used. The oscillator signal is fed both to the synthesiser divider chain and to a divider that is dividing the signal by 2 before it is applied to the downconverting mixer. Local oscillator high side injection has to be used for receive frequencies between approximately 300 and 320 MHz, low side injection for receive frequencies between 320 and 340MHz - see also Section 3.4. To be able to switch between two different freq uency cha nnels a divi der ratio of either 32 or 32 .25 can be selected via the FSEL-Pin.
Table 2 Dependence of PLL overall division ratio on FSEL FSEL Ratio r=(f
Open 32 GND 32.25
L0/fQU
)

2.4.4 Crystal Oscillator

The calculation of the value of the necessary crystal load capacitance is shown in Section 3.3, the crystal frequency calculation is explained in Section 3.4.

2.4.5 Limiter

The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It has a typical input impedance of 330 Ω to allow for easy interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator
Preliminary Specification 16 V 1.1, 2004-10-20
TDA 5221
(RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4. This signal is used to demodulate ASK­modulated receive signals in the subsequent baseband circuitry. The RSSI output is applied to the modulation format switch, to the Peak Detector input and to the AGC circuitry.
In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state as described in the next chapter.
Functional Description

2.4.6 FSK Demodulator

To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is contained fully on chip. The Limiter output differential signal is fed to the linear phase detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain is typically 200µV/kHz. The passive loop fil ter output that is com prised fully on chip is fed to both the VCO and the modulation format switch described in more detail below. This signal is representing the demodulated signal with low frequencies applied to the demodulator demodulated to logic ones and high frequencies demodulated to logic zeroes. How ever th is is on ly vali d in cas e the loca l osci llator is low- side in ject ed to the mixer which is applicable to receive frequencies above 320MHz. In case of receive frequencies below 320MHz (e.g.315MHz) high frequencies are demodulated as logical ones due to a sign inversion in the downconversion mixing process. See also Section
3.4.
The modulation forma t switch i s actually a switchabl e amplifier wi th an AC gain o f 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was chosen to facilitate d etec tio n in the sub se que nt c irc uit s. Th e DC gai n is 1 i n ord er no t to saturate the subsequent Data Filter wih the DC offset produced by the demodulator in case of large frequency offsets of the IF signal. The resulting frequency characteristic and details on the principle of operation of the switch are described in Section 3.6.
Table 3 MSEL Pin Operating States MSEL Modulation Format
Open ASK Shorted to ground FSK
The demodulator circuit is switched off in c a se of reception of ASK signals.

2.4.7 Data Filter

The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100kΩ on-chip resistors. Along with two external capac itors a 2nd order
Preliminary Specification 17 V 1.1, 2004-10-20
TDA 5221
Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 3.2.
Functional Description

2.4.8 Data Slicer

The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data r ate of up to 10 0kBaud . The maxim um achiev able da ta rate als o depends on the IF F ilt er b andwidth and the local oscillator to le ranc e val ue s. Both in puts are accessible. The output delivers a digital data signal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RC­term. In ASK-mode alte rnatively a sc aled value of t he voltage at th e PDO-output (approx . 87%) can be used as the s licer-th reshol d as sh own in Tab le 4. The data slicer threshol d generation alternatives are described in more detail in Section 3.5.
Table 4 SSEL Pin Operating States SSEL MSEL Selected Slicing Level (SL)
X Low external SL on Pin 20 (RC-term, e.g.) High High external SL on Pin 20 (RC-term, e.g.) Low High 87% of PDO-output (approx.)

2.4.9 Peak Detector

The peak detecto r gene rates a DC v oltage which is p roportio nal to the pe ak v alue o f the receive data sign al. A capa citor is n ecessary . The inpu t is conn ected to th e out put of th e RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This ou tput can be used as an indicator for the received signal strength to use in wake-up circuits and as a reference for the data slicer in ASK mode. Note that the RSSI leve l is also output in case of FSK mode.

2.4.10 Bandgap Reference Circuitry

A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pi n ( Pin 2 7) as sh own in the fo ll o win g t ab le. T h e s u pply current dra w n in this case is typically 50nA.
Table 5 PDWN Pin Operating States PDWN Operating State
Open or tied to ground Powerdown Mode Tied to Vs Receiver On
Preliminary Specification 18 V 1.1, 2004-10-20
TDA 5221

3 Applications

3.1 Application Circuit

3VO UT
24 23
20kΩ
RSSI > U
RSSI < U
threshold
threshold
: I
load
: I
load
=4.2µA = -1.5µA
TAGC
+ 3 .1 V
C5
R4
THRES
I
load
4
U
U
C
U U
U
C18
R5
U
threshold
OTA
G ain control
voltage
:< 2.6V : G ain high
c
:> 2 .6V : G a in low
c
= VCC - 0.7 V
cma x
= 1.67V
cmin
Applications
R S S I (0.8 - 2 .8V )
VCC
LNA
Figure 3 LNA Automatic Gain Control Circuity
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold voltage U
. As shown in the
thres
following figure th e threshold volt age can have any value between approximately 0.8 and
2.8V to provide a switching point within the receive signal dynamic range. This voltage U
is applied to the THRES pin (Pin 23 ) The thresh old voltage ca n be
thres
generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin. If the RSSI level g enerated by the L imiter is h igher than U
, the OTA generates a positi ve current I
thres
. This yields a voltage ris e on th e
load
TAGC pin (Pin 4). Otherwi se, the OTA generates a negative current. These currents do not have the same values in order to achiev e a fast-attack an d slow-release ac tion of the
Preliminary Specification 19 V 1.1, 2004-10-20
TDA 5221
Applications
AGC and are used to charge an extern al capac itor wh ich fin ally ge nerates the LNA gain control voltage.
in high gain mode
3
2.5
2
1.5
Voltage Range
THRES
U
1
0.5
0
-120 -110 -100 -90 -80 -70 -60 -50 -40
RSSI Level
Input Level at LNA Input [dBm]
LNA always
RSSI Level Range
in low gain mode
LNA always
-30
Figure 4 RSSI Level and Permissive AGC Threshold Levels
The switching poi nt should be chosen accordin g to the in tended operating scenario . The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8V is apparently a via ble choice. It shoul d be noted that the output of th e 3VOUT pin is capable of driving up to 50µA, but that the THRES pin input current is only in the reg ion of 40nA. As the curren t drawn out of the 3VOUT pin is directly related to the receiver power con sumptio n, the pow er divider resi stor s shoul d have hig h impedance values. The sum of R1 and R2 has to be 600kΩ in order to yield 3V at the 3VOUT pin. R1 can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT output current of 5µA
1)
and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain mode operati on THRES has t o be connected to GND.
As stated above the capacitor connected to the TAGC pin is gen erating the gain control voltage of the LNA due to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As the charging and discharging currents are not equal two differen t time constan ts will res ult. The time cons tant corr espondin g to the charging process of the capacitor shall be chosen according to the data rate. According to measuremen ts performed at Infine on the capacitor valu e should be greater than 47nF.
1) note the 20kΩ resistor in series with the 3.1V internal voltage source
Preliminary Specification 20 V 1.1, 2004-10-20
TDA 5221
Applications

3.2 Data Filter Design

Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas
C14 C12
22 21 19
R
F1 int
100k 100k
R
F2 int
Figure 5 Data Filter Design
with R
F1int=RF2int
=R
2
=
C
14
fR
2
π
1)
.
SLPOPPFFB
bQ
C
12
dB
3
b
=
fQR
4
π
dB
3
with
b
Q =
a
Q is the qualify factor of the poles where, in case of a Bessel filter a=1.3617, b=0.618 and thus Q=0.577
and in case of a Butter worth filter a=1.414, b=1 and thus Q=0.71
Example: Butter worth filter with f
=5kHz and R=100kΩ:
3dB
C14=450pF, C12=225pF
1) taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Preliminary Specification 21 V 1.1, 2004-10-20
TDA 5221
Applications

3.3 Crystal Load Capacitance Calculation

The value of the capacit or neces sary to ac hieve that the cry stal os cilla tor is opera ting at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circu it as shown in Section 4.1.3 and by the crystal specificati ons giv en by the crystal manufacturer.
C
S
CRST2
Xf
L
28
TDA521X
1
CRST1
can be
L
Crystal
Input
impedance
Z
1-28
Figure 6 Determination of Series Capacitance Vale for the Quartz Oscillator
The required series capacitor for a crystal with specified load capacitance C calculated as
C
S
1
=
1
π
2
+
C
L
CL is the nominal load capacitance specified by the crystal manufacturer.
Example:
10.18 MHz: C
= 12 pF XL=870 Ω CS = 7.2 pF
L
This value may be obtained by putting two capacitors in series to the crystal, such as 18pF and 12pF in the 10.2MHz case.
But please note that the calculated C
-value includes all parasitic.
S

3.4 Crystal Frequency Calculation

As described in Section 2.4.3 the operating range of the on-chi p VCO is wi de enoug h to guarantee a receive frequency range between 300 and 340MHz. The VCO signal is divided by 2 before applied to the mixer . This local oscillator signal can be used to downconvert the RF signals both with high- or low-side injection at the mixer. High-side
Preliminary Specification 22 V 1.1, 2004-10-20
TDA 5221
r
Applications
injection of the local oscillator has to be used for receive frequencies between 300 and 320 MHz. In this case the local oscillator frequency is calculated by adding the IF frequency (10.7 MHz) to the RF frequency. In this case the higher frequency of a FSK­modulated signal is demodulated as a logical one (high).
Low-side injection has to be used for receive frequencies between 320 and 340 MHz. The local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF frequency then. Please note that in this case sign-inversion occurs and the higher frequency of a FSK-mod ulated signa l is de modul ated as a logi cal ze ro (low). Th e overall division ratios i n th e PLL are 32 or 3 2.2 5 d epe ndi ng on whether the FSEL-pin is left open or tied to ground.
Therefore the crystal frequency may be calculated by using the following formula:
with ƒ
f
=
QU
receive frequency
RF
local oscillator (PLL) frequency (ƒ
ƒ
LO
f
RF
7.10±
RF
± 10.7)
ƒQU quartz crystal oscillator frequency r ratio of local oscillator (PLL) frequency and crystal frequency as
shown in the subsequent table
Table 6 Dependence of PLL Overall Division Ratio on FSEL FSEL Ratio r=(fLO/fQU)
open 32 GND 32.25
This yields the following exa mples : FSEL is „Low“:
MHzMHz
7.1055.318
f
=
QU
+
25.32
=
MHz
209375.10
FSEL is „High“:
MHzMHz
7.10316
f
=
QU
+
32
=
MHz
209375.10

3.5 Data Slicer Threshold Generation

The threshold of the data slicer can be generated using an external R-C integrator as shown in Figure 7.
Preliminary Specification 23 V 1.1, 2004-10-20
TDA 5221
The time constant TA of this circuit including also the internal resistors R
Applications
and R
F3int
F4int
(see Figure 9) has to be significantly larger than the longest period of no signal change
within the data sequence.
T
L
In order to keep distortion low, the minimum value for R is 20kΩ.
has to be calculated as
T
A
=
+⋅
T
A
1
)(1
RRR
FF
int4int3
++
RRR
FF
int4int3
⋅+=⋅
FF
int4int3
...13)(113
ASKforCRRIIRC
and
CM
RRIIR
+
v
25
)(1
FF
int4int3
⋅
FSKforC
...13
T
A
R1, R
=
F3 int
int4
1
, R
++
and C13 see also Figure 7 and .Figure 9
F4 int
data filter
C
RRR
FF
13
int4int3
=⋅
2019
U
threshold
data slicer
RR
1
⋅
F
Figure 7 Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use the peak detector in connection with an internal resistive divider and one capacitor as shown in the following Figure 8. For selecting the peak detector as reference for the slicing level a logic low as to be applied on the SSEL pin.
In case of MSEL is high (or open), which means that ASK-Mode is selected, a logic low on the SSEL pin yields a logic high on the AND-output and thus the peak-detector is selected (see Figure 9).
In case of FSK the MSEL-pin and furthermore the one input of the AND-gate is low, so the peak detector can not be selected.
The capacitor value is depending on the coding scheme and the protocol used.
Preliminary Specification 24 V 1.1, 2004-10-20
TDA 5221
C
Pins:
peak detector
26
56k
U
390k
data slicer
threshold
25
CP
Applications
Figure 8 Data Slicer Threshold Generation Utilising the Peak Detector

3.6 ASK/FSK-Data Path Functional Description

The TDA5221 is containing an ASK/FSK switch which can be controlled via Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offse t generated es pecially in case of the FSK PLL demodu lator there is a feedback connec tion between the thresho ld voltage of the bit slic er comparator (Pin 20) to the negative input of the FSK switch amplifier.
In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87% of the peak-detector output-vo lta ge at Pin 26 (PDO) can be used as the s li cer -reference level.
The slicing reference level is generated by an internal voltage divider (R
T1int
, R
T2int
which is applied on the peak detector output. The selection between these modes is controlled by Pin 16 (SSEL), as described in
Section 3.5. This is shown in the following Figure 9.
Preliminary Specification 25 V 1.1, 2004-10-20
),
TDA 5221
F
R
56k
T1 int
R
390k
T2
H=CP L=CM
SSEL
Applications
PDO
26
25
C15 100n
DATA Out
from RSSI Gen
(ASK signal)
FSK PLL Demodulator
0.18 mV/kHz
typ. 2 V
1.5 V ......2.5 V
MSEL
15
H=ASK L=FSK
ASK/FSK Switch
Data F ilter
-
+
ASK FSK
+
-
AC DC
R
300k
R
F4 int
30k
ASK mode: v=1 FSK mode: v=11
F3 int
R
F1 int
100k 100k
R
F2 int
v = 1
192122 20
SLPOOPFFB SLN
C12
C14
PEAK
DETECTOR
Comp
-
+
CP CM
+
-
1
16
R1
C13
Figure 9 ASK/FSK mode datapath

3.7 FSK Mode

The FSK datapath has a bandpass characterisi tc due to the feedback shown above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by the external RC-combination. The upper cutoff frequency f3 is determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 200µV/kHz. This gain is increased by the g ai n v o f th e FSK switch, which is 11. Therefore the resulting dynamic gain of this circ uit is 2 .2mV/kHz within the bandpas s. The g ain for th e DC conte nt of FSK signal remains at 200µV/kHz. The cu t-off frequencies of the bandpas s have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount.
In case that the use r data is co ntaini ng long se quences of l ogica l zeroes th e effect of th e drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at the negative input of the slicer comparator (Pin20) is used. The comparator has no hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the comparator (i.e. 20nA) running over the external resistor R. This voltage raises the voltage appearing a t p in 20 (e.g . 1 mV with R = 100kΩ). In order to obtain benefit of this
Preliminary Specification 26 V 1.1, 2004-10-20
TDA 5221
Applications
asymmetrical offset for the demodulation of long zeros the lower of the two FSK frequencies should be chosen in the transmitter as the zero-symbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v
v-3dB
20dB/dec -40dB/dec
3dB
0dB
DC
f1 f2 f3
0.18mV/kHz
2mV/kHz
f
Figure 10 Frequency characteristic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f
=
1
2
π
is the 3dB cutoff frequency of the data filter - see Section 3.2.
f
3
1
3301
kR
Ω×
13
C
×
3301
kR
Ω+
11 ffvf ×=×=
112
ff33=
dB
Example: R1 = 100kΩ, C13 = 47nF This leads tof
Preliminary Specification 27 V 1.1, 2004-10-20
= 44Hz and f2 = 485Hz
1
TDA 5221
Applications

3.8 ASK Mode

In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff frequency is determined by the external capacitors C
and C14 and the internal 100k resistors as
12
described in Section 3.2
0dB
-3dB
-40dB/dec
f3dB
f
Figure 11 Frequency characteristic in case of ASK mode

3.9 Principle of the Precharge Circuit

In case the data slicer threshold shall be generated with an external RC network as described in Section 3.5 it is necessary to use large values for the capacitor C attached to the SLN pin (pin 2 0) in orde r to achie ve long tim e constants . This re sults al so from th e fact that the choice of the value for R1 connected between the SLP and SLN pins (pins 19 and 20) is lim ite d by the 330kΩ resistor appearing in paral le l t o R 1 as c an b e s ee n i n Figure 9. Apart from this a resis tor va lue of 10 0kΩ lead s to a vol tage o ffset of 1mv at th e comparator input. The resulting startup time constant τ
()
τ
1
can be calculated with:
1
13330||1
CkR ×Ω=
In case R1 is chosen to be 100kΩ and C13 is chosen as 47nF this leads to
()
τ
1
msnFknFkk 6.3477747330||100
=×Ω=×ΩΩ=
When the device is turned on this time constant dominates the time necessary for the device to be able to demodulate data properly. In the powerdown mode the capacitor is only discharged by leakage currents.
Preliminary Specification 28 V 1.1, 2004-10-20
TDA 5221
Applications
In order to reduce the turn-on time in the presence of large values of C a precharge circuit was included in the TDA5221 as shown in the following figure.
C18
20k
24
R4+R5=600k
R4
U2
+3.1V
U
23
Uc>Us
R5
threshold
OTA
-
Uc<Us
0 / 240uA
+
20
I
load
-
+
U2<2.4V : I=240uA U2>2.4V : I=0
+2.4V
C13
R1
19
Uc
Data Filter
Us
ASK/FSK Switch
Figure 12 Principle of the precharge circuit
This circuit charg es the c apaci tor C13 w ith an inrus h curren t I duration of T
until the vol tag e Uc appearing on the capacitor is equal to the voltage U
2
of typically 220µA for a
load
at the input of the data filter. This voltage is limited to 2.5V. As soon as these voltages are equal or the duration T
is exceeded the precharge circuit is disabled.
2
τ2 is the time constant of the charging process of C18 which can be calculated as
s
220
τ
2
as the sum of R4 and R5 is sufficiently large and thus can be neglected. T
Ck ×Ω≈
can then be
2
calculated according to the following formula:
 
T
Preliminary Specification 29 V 1.1, 2004-10-20
ln
=
1
−
 
 
1
4.2
V
 
3
V
6.1
×≈
ττ
222
TDA 5221
The voltage transient during the charging of C2 is shown in the following figure:
Applications
U2
3V
2.4V
2
Figure 13 Voltage appearing on C18 during precharging process
The voltage appe aring on the c apacitor C13 co nnected to pin 20 is shown in the followin g figure. It can be seen that due to the fact that it is charged by a constant current source it exhibits is a lin ear inc rease in v olt age whi ch is lim ited to U approximate operating point of the data filter input. The time constant appearing in this case can be denoted as T3, which can be calculated with:
T2
= 2.5V which is also the
Smax
13
CU
×
max
S
T
=
3
220
A
Preliminary Specification 30 V 1.1, 2004-10-20
220
5.2
V
13
C
×=
A
µµ
TDA 5221
Uc
Us
T3
Figure 14 Voltage transient on capacitor C13 attached to pin 20
As an example the choice of C18 = 22nF and C13 = 47nF yields
= 0.44ms
τ
2
T2 = 0.71ms T3 = 0.53ms
Applications
This means that in this case the inrush current could flow for a duration of 0.64ms but stops already after 0.49m s when the U chosen to be shorter than T
.
2
limit has been reac hed. T3 should always be
Smax
It has to be noted finally that during the turn-on duration T2 the overall device power consumption is increased by the 220µA needed to charge C13.
The precharge circuit may be disabled if C18 is not equipped. This yields a T zero. Note th at the sum of R
and R5 has to be 600kΩ in order to produce 3V at the
4
close to
2
THRES pin as this voltage is internally used also as the reference for the FSK demodulator.
Preliminary Specification 31 V 1.1, 2004-10-20
TDA 5221
Reference

4 Reference

4.1 Electrical Data

4.1.1 Absolute Maximum Ratings

Attention: The maximum ratings may not be exceeded under any circumstances,
not even momentarily a nd in divi dual ly, a s p erma nent dam age to th e IC may result. The AC/DC characteristic limits are not guaranteed.
Table 7 Absolute Maximum Ratings, T
#
Parameter Symbol Limit Values Unit Remarks
min. max.
1 Supply Voltage V 2 Junction Temperature T 3 Storage Temperature T 4 Thermal Resistance R 5 ESD integrity, all pins
excl. Pins 1,3, 6, 28 ESD integrity Pins 1,3,6,28
s
j
s
thJA
V
ESD
= -40 °C … +105 °C
amb
-0.3 5.5 V
-40 +125 °C
-40 +150 °C 114 K/W
+2
+1.5
kVkVHBM according to
MIL STD 883D,
method 3015.7

4.1.2 Operating Range

Within the operational range the IC operates as explained in the circuit description. Currents flowing into the device are denoted as positive currents and vice versa. The device parameters marked with ■ are not part of the production test, but either verified by design or measured in the Infineon Evalboard as described in Section 4.2.
Supply voltage: VCC = 4.5V .. 5.5V
T
Table 8 Operating Range,
#
Parameter Symbol Limit Values Unit Test Conditions/
1 Supply Current I
2 Receiver Input Level
ASK FSK, frequ. dev. ± 50kHz
3 LNI Input Frequency f
Preliminary Specification 32 V 1.1, 2004-10-20
SF
I
SA
RF
RF
= -40 °C … +105 °C
amb
min. max.
4.1
3.5
in
-110
-102 300 340 MHz
8.1
7.3mAmA
-13
dBm
-13
dBm
L
Notes
■
TDA 5221
#
Parameter Symbol Limit Values Unit Test Conditions/
min. max.
4 MI/X Input Frequency f 5 3dB IF Frequency Range
ASK
FSK 6 Powerdown Mode On PWDN 7 Powerdown Mode Off PWDN 8 Gain Control Voltage,
LNA high gain state 9 Gain Control Voltage,
LNA low gain state
■ Not part of the production test - either verified by design or measured in an Infineon Ev alboard described in
Section 4.2.
MI
f
IF -3dB
V
THRES
V
THRES
4.1.3 AC/DC Characteristics at T
300 340 MHz
5
10.42311 2VSV
ON
00.8V
OFF
2.8 V
00.7V
AMB
S
= 25°C
MHz
V
Notes
Reference
L
■
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. Currents flowing into the device are denoted as po-sitive currents and vice versa. The device performan ce parameters marked with
■ are not part of the pro ductio n
test, but either verif ied by design or measured in the Infineon Evalboard as desc rib ed i n Section 4.2.
Table 9 AC/DC Characteristics with TA 25°C, V
#
Parameter Symbol Limit Values Unit Test Conditions/
min. typ. max.
=4.5 ... 5.5 V
VCC
L
Notes
SUPPLY
Supply Current
1 Supply current,
standby mode 2 Supply current,
device operating in
FSK mode 3 Supply current,
device operating in
ASK mode
Preliminary Specification 33 V 1.1, 2004-10-20
I
S PDWN
I
SF
I
SA
50 100 nA Pin 27 (PDWN)
open or tied to 0 V
5.1 6.2 7.1 mA Pin 11 (FSEL) open, Pin 15 (MSEL) tied to GND
4.5 5.5 6.3 mA Pin 11 (FSEL) open, Pin 15 (MSEL) open
TDA 5221
#
Parameter Symbol Limit Values Unit Test Conditions/
min. typ. max.
Notes
LNA
Signal Input LNI (PIN 3), V
1 Average Power Level
at BER = 2E-3 (Sensitivity)
2 Average Power Level
at BER = 2E-3 (Sensitivity) FSK
3 Input impedance,
= 315 MHz
f
RF
4 Input level @ 1dB
C.P.
=315 MHz
f
RF
rd
5 Input 3
order intercept point f 315 MHz
RF
=
6 LO signal feedthrough
at antenna port
Signal Output LNO (PIN 6), V
1 Gain f
= 315 MHz S
RF
2 Output impedance,
= 315 MHz
f
RF
3 Voltage Gain Antenna
to MI f
= 315 MHz
RF
4 Noise Figure NF
Signal Input LNI, V
THRES
1 Input impedance,
= 315 MHz
f
RF
2 Input level @ 1dB C.
= 315 MHz
P. f
RF
>2.8V, high ga i n mode
THRES
RF
in
RF
in
S
11 LNA
P1dB
IIP3
LO
LNI
THRES
21 LNA
S
22 LNA
G
0.895 / -25.5 deg ■
LNA
LNA
>2.8V, high gain mode
1.577 / 150.3 deg ■
0.897 / -10.3 deg ■
AntMI
LNA
=GND, lwo gain mode
S
11 LNA
P1dB
0.918 / -25.2 deg ■
LNA
-113 dBm Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
-105 dBm Manchester enc. datarate 4kBit, 280kHz IF Bandw., ± 50kHz pk. dev.
-14 dBm ■
-10 dBm fin = 315 & 317MHz ■
-119 dBm ■
21 dB ■
2 dB excluding matching
network loss - see Appendix
-7 dBm matched input ■
Reference
L
■
■
■
Preliminary Specification 34 V 1.1, 2004-10-20
TDA 5221
#
Parameter Symbol Limit Values Unit Test Conditions/
Notes
3 Input 3rd order
intercept point f 315 MHz
Signal Output LNO, V
1 Gain f
= 315 MHz S
RF
RF
=
THRES
2 Output impedance,
= 315 MHz
f
RF
3 Voltage Gain Antenna
to MI f
= 315 MHz
RF
Signal 3VOUT (PIN 24)
1 Output voltage V 2 Current out I
Signal THRES (PIN 23)
1 Input Voltage range V 2 LNA low gain mode V 3 LNA high gain mode V 4 Current in I
Signal TAGC (PIN 4)
1 Current out,
LNA low gain state
2 Current in,
LNA high gain state
min. typ. max.
IIP3
LNA
=GND, lwo gain mode
21 LNA
S
22 LNA
G
AntMI
3VOUT
3VOUT
THRES
THRES
THRES
THRES_in
I
TAGC_out
I
TAGC_in
-13 dBm fin = 315 & 317MHz ■
0.193 / 153.7 deg ■
0.907 / -10.5 deg ■
2dB ■
2.9 3.1 3.3 V 3VOUT Pin open
-3 -5 -10 µA see Section 4.1
0V 0V 3V
5nA ■
-3.6 -4.2 -5.5 µA RSSI > V
11.62.2µARSSI < V
-1 V see Section 4.1
S
-1 V or shorted to Pin 24
S
Reference
L
THRES
THRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1 Input impedance,
= 315 MHz
f
RF
rd
2 Input 3
order
intercept point
Signal Output IFO (PIN 12)
1 Output impedance Z 2 Conversion Voltage
Gain f
= 315 MHz
RF
3 Noise Figure, SSB
(
~DSB NF+3dB)
Preliminary Specification 35 V 1.1, 2004-10-20
S
11 MIX
IIP3
IFO
G
MIX
NF
MIX
MIX
0.954 / -10.9 deg ■
-25 dBm ■
330 Ω ■ 21 dB ■
13 dB ■
TDA 5221
#
Parameter Symbol Limit Values Unit Test Conditions/
Notes
4 RF to IF isolation A
RF-IF
min. typ. max.
46 dB ■
LIMITER
Signal Input LIM/X (PINS 17/18)
1 Input Impedance Z 2 RSSI dynamic range DR 3 RSSI linearity LIN 4 Operating frequency
(3dB points)
f
LIM
LIM
264 330 396 Ω ■
RSSI
RSSI
70 dB
±1dB ■
5 10.7 23 MHz ■
DATA FILTER
1 Useable bandwidth BW
FILT
2 RSSI Level at Data
RSSI
Filter Output SLP,
=-103dBm
RF
IN
3 RSSI Level at Data
RSSI
Filter Output SLP,
=-30dBm
RF
IN
BB
low
high
100 kHz ■
1.1 V LNA in high gain mode
2.65 V LNA in high gain mode
Reference
L
SLICER
Signal Output DATA (PIN 25)
1 Maximum Datarate DR
2 LOW output voltage V 3 HIGH output voltage V
max
SLIC_L SLIC_HVS
00.1V
1.3
-
100 kBps NRZ, 20pF
VS-1 VS-
V output
0.7
capacitive loading
■
current=200µA
Slicer, SLN (PIN 20)
1 Precharge Current
Out
I
PCH_SLN
-100 -220 -300 µA see Section 3.9
PEAK DETECTOR
Signal Output PDO (PIN 26)
Preliminary Specification 36 V 1.1, 2004-10-20
TDA 5221
#
Parameter Symbol Limit Values Unit Test Conditions/
min. typ. max.
1 Load current I
2 Internal resistive load R 357 446 535 kΩ
load
-500 µA static load current
Notes
must not exceed ­500µA
CRYSTAL OSCILLATOR
Signals CRSTL 1, CRSTL 2 (PINS 1/28)
1 Operating frequency f
2 Input Impedance
@
~10MHz
3 Serial Capacity
~10MHz
@
CRSTL
Z
1-28
C
S10
5 11 MHz fundamental mode,
series resonance
-700 +
j 865
=C1 7.2 pF ■
Ω ■
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1 ASK Mode V 2 FSK Mode V 3 Input Bias Current
MSEL
MSEL MSEL
I
MSEL
1.4 4 V or open 0 0.2 V or tied to ground
-11 -19 µA MSEL tied to GND
Reference
L
FSK DEMODULATOR
1 Demodulation Gain G
2 Useable IF Bandwidth BW
FMDEM
IFPLL
200 µV/k
Hz
10.2 10.7 11. 2 MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1 Powerdown Mode On PWDN 2 Powerdown Mode Off PWDN 3 Input bias current
PDWN
Preliminary Specification 37 V 1.1, 2004-10-20
I
PDWN
2.8 V
ON
00.8V
Off
19 µA Power On Mode
V
S
TDA 5221
#
Parameter Symbol Limit Values Unit Test Conditions/
Notes
used crystal
4 Start-up Time until
valid IF signal is detected
min. typ. max.
T
SU
1 ms depends on the
PLL DIVIDER
Signal FSEL (PIN 11)
1 Overal divison ratio 32V
2 Overal division ratio
32.25
3 Input bias current
FSEL
FSEL
V
FSEL
I
FSEL
1.4 4 V or open
0 0 .2 V or tied to GND
-11 -19 µA FSEL tied to GND
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1 Slicer-Reference is
voltage at Pin 20 (SLN)
2 Slicer-Reference is
approx. 87% of the voltage at Pin 26 (PDO)
3 Input bias current
SSEL
V
SSEL
V
SSEL
I
SSEL
1.4 4 V or open
00.2V
-11 -19 µ A SSEL tied to GND
Reference
L
■
Not part of the production test - either verified by design or measured in the Infineon
■
Evalboard as described in Section 4.2.
Preliminary Specification 38 V 1.1, 2004-10-20
TDA 5221
4.1.4 AC/DC Characteristics at T
= -40 to 105°C
AMB
Reference
Currents flowing into the device are denoted as positive currents and vice versa.
Table 10 AC/DC Characteristics with T
#
Parameter S ym bol Limit Values Unit Test Conditions/
min. typ. max.
= -40°C ...+105°C, V
AMB
Notes
=4.5 ... 5.5 V
VCC
SUPPLY
Supply Current
1 Supply current,
standby mode
2 Supply current,
device operating in FSK mode
3 Supply current,
device operating in ASK mode
Signal Input 3VOUT (PIN 24)
1 Output voltage V 2 Current out I
Signal THRES (PIN 23)
1 Input Voltage range V 2 LNA low gain mode V 3 LNA high gain mode V 4 Current in I
Signal TAGC (PIN 4)
1 Current out,
LNA low gain state
2 Current in, LNA high
gain state
I
S PDWN
I
SF
I
SA
3VOUT
3VOUT
THRES THRES THRES
THRES_in
I
TAGC_out
V
TAGC_in
50 400 nA Pin 27 (PDWN) open
or tied to 0 V
4.1 6.2 8.1 mA Pin 11 (FSEL) open, Pin 15 (MSEL) tied to GND
3.5 5.5 7.3 mA Pin 11 (FSEL) open, Pin 15 (MSEL) open
2.9 3.1 3.3 V 3VOUT Pin open
-3 -5 -10 µA see Section 4.1
0V
-1 V see Section 4.1
S
0V 3V
-1 V or shorted to Pin 24
S
5nA
-1 -4.2 -8 µA RSSI > V
0.5 1 .5 5 µA RSS I < V
THRES
THRES
L
■
MIXER
1 Conversion Voltage
Gain f
= 315 MHz
RF
G
MIX
+19 dB
LIMITER
Preliminary Specification 39 V 1.1, 2004-10-20
TDA 5221
#
Parameter S ym bol Limit Values Unit Test Conditions/
min. typ. max.
Notes
Signal Input LIM/X (PINS 17/18)
1 RSSI dynamic range DR 2 RSSI Level at Data
RSSI Filter Output SLP, RF
= -103dBm
IN
3 RSSI Level at Data
RSSI Filter Output SLP,
= -30dBm
RF
IN
RSSI
low
high
70 dB
1.1 V LNA in high gain mode
2.65 V LNA in high gain mode
DATA FILTER
Slicer, Signal Output DATA (PIN 25)
1 Maximum Datarate DR
2 LOW output voltage V 3 HIGH output voltage V
SLIC_L SLIC_HVS
Slicer, Negative Input (PIN 20)
1 Precharge Current
Out
I
PCH_SLN
max
00.1V
-
1.5
-100 -220 -300 µA see Section 3.9
100 kBps NRZ, 20pF capacitive
loading
VS-1 VS-
V output current=200µ A
0.5
Reference
L
■
PEAK DETECTOR
Signal Output PDO (PIN 26)
1 Load current I
load
-400 µA static load current must not exceed -500µA
2 Internal resistive load R 356 446 575 kΩ
CRYSTAL OSCILLATOR
Signals CRSTL 1, CRSTL 2 (PINS 1/28)
1 Operating frequency f
CRSTL
5 11 MHz fundamental mode,
series resonance
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1 ASK Mode V
MSEL
Preliminary Specification 40 V 1.1, 2004-10-20
1.4 4 V or open
TDA 5221
#
Parameter S ym bol Limit Values Unit Test Conditions/
Notes
2 FSK Mode V 3 Input bias current
MSEL
MSEL
I
MSEL
min. typ. max.
00.2V
-11 -20 µA MS EL tied to GND
FSK DEMODULATOR
1 Demodulation Gain G
2 Useable IF
Bandwidth
FMDEM
BW
IFPLL
200 µV/k
Hz
10.4 10.7 11 M Hz
POWER DOWN MODE
Signal PDWN (PIN 27)
1 Powerdown Mode On PWDN 2 Powerdown Mode Off PWDN 3 Start-up Time until
valid signal is
T
SU
2.8 V
ON
00.8V
Off
V
S
1 ms depends on the used
crystal
detected at IF
PLL DIVIDER
Reference
L
■
Signal FSEL (PIN 11)
1 Overal divison ratio 32V
2 Overal division ratio
32.25
3 Input bias current
FSEL
FSEL
V
FSEL
I
FSEL
1.4 4 V or open
0 0.2 V or tied to GND
-11 -20 µA FSEL tied to GND
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1 Slicer-Reference is
voltage at Pin 20 (SLN)
Preliminary Specification 41 V 1.1, 2004-10-20
V
SSEL
1.4 4 V or open
TDA 5221
#
Parameter S ym bol Limit Values Unit Test Conditions/
min. typ. max.
2 Slicer-Reference is
approx. 87% of the voltage at Pin 26 (PDO)
3 Input bias current
SSEL
Not part of the production test - either verified by design or measured in the Infineon
■
V
SSEL
I
SSEL
00.2V
-11 -20 µA SSEL tied to GND
Notes
Reference
Evalboard as described in Section 4.2.

4.2 Test Circuit

The device performance parameters marked with ■ in Section 4.1 wer e ei th er ve rif ied by design or measured on an Infineon evaluation board. This evaluation board can be obtained together with evaluation boards of the accompanying transmitter device TDK5110 in an evaluation kit that may be ordered on the INFINEON Webpage www.infineon.com/Products More information on the kit is available on request.
L
Figure 15 Schematic of the Evaluation Board
Preliminary Specification 42 V 1.1, 2004-10-20
TDA 5221

4.3 Test Board Layouts

Figure 16 Top Side of the Evaluation Board
Reference
Figure 17 Bottom Side of the Evaluation Board
Preliminary Specification 43 V 1.1, 2004-10-20
TDA 5221
Figure 18 Component Placement on the Evaluation Board

4.4 Bill of Materials

The following components are necessary for evaluation of the TDA5221.
Table 11 Bill of Materials (cont’d)
Reference
Ref. Value Specification 315MHz
C1 3.3pF 0805, COG, +/-0.1pF C2 10pF 0805, COG, +/-0.1pF C3 6.8pF 0805, COG, +/-0.1pF C4 100pF 0805, COG, +/-5% C5 47nF 1206, X7R , +/-10% C6 15nH Toko, PTL2012-F15N0G C7 100pF 0805, COG, +/-5% C8 33pF 0805, COG, +/-5%
C9 100pF 0805, COG, +/-5% C10 10nF 0805, X7R, +/-10% C11 10nF 0805, X7R, +/-10% C12 220pF 0805, COG, +/-5%
Preliminary Specification 44 V 1.1, 2004-10-20
TDA 5221
Reference
Ref. Value Specification 315MHz
C13 47nF 0805, X7R, +/-10% C14 470pF 0805, COG, +/-5% C15 47nF 0805, COG, +/-5% C16 12pF 0805, COG, +/-1% C17 22pF 0805, COG, +/-1% C18 22nF 0805, X7R, +/-5% C21 100nF 1206, X7R, +/-10%
IC1 TDA5221 Infineon
L1 15nH Toko, PTL2012-F15N0G
L2 12pF 0805, COG, +/-1% Q1 10,209375 MHz 1053-925 Q2 SFE_10.7MA5-A Murata R1 100kΩ 0805, +/-5% R4 240kΩ 0805, +/-5% R5 360kΩ 0805, +/-5% R6 10kΩ 0805, +/-5%
S1 STL_2POL 2-pole pin connector S2 SOL_JUMP SOL_JUMP S3 SOL_JUMP SOL_JUMP S6 SOL_JUMP SOL_JUMP X1 STL_2POL 2-pole pin connector X2 A107-900A (1.6mm gold plated) INPUT OUTPUT ENTERPRISE CORP X3 A107-900A (1.6mm gold plated) INPUT OUTPUT ENTERPRISE CORP
Please note that a capacitor has to be soldered in place L2 and an inductor in place C6.
Preliminary Specification 45 V 1.1, 2004-10-20
TDA 5221

5 Package Outlines

Package Outlines
P_TSSOP_28.eps
Figure 19 <Dev_Package1>
Table 12 Order Information Type Ordering Code Package
TDA 5221 Q67100-H2051 <Dev_Package1>
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
Preliminary Specification 46 V 1.1, 2004-10-20
Dimensions in mm
TDA 5221
List of Tables Page
Table 1 Pin Defintion and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2 Dependence of PLL overall division ratio on FSEL . . . . . . . . . . . . . . . 16
Table 3 MSEL Pin Operating States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4 SSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6 Dependence of PLL Overall Division Ratio on FSEL. . . . . . . . . . . . . . 23
T
Table 7 Absolute Maximum Ratings, Table 8 Operating Range,
T
= -40 °C … +105 °C . . . . . . . . . . . . . . . . . . . . 32
amb
Table 9 AC/DC Characteristics with T Table 10 AC/DC Characteristics with T
Table 11 Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12 Order Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
= -40 °C … +105 °C. . . . . . . . . . . . 32
amb
25°C, V
A
= -40°C ...+105°C, V
AMB
=4.5 ... 5.5 V / . . . . . . . . . . 33
VCC
=5.5V . . . . 39
VCC
Preliminary Specification 47 V 1.1, 2004-10-20
TDA 5221
List of Figures Page
Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3 LNA Automatic Gain Control Circuity. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4 RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . 20
Figure 5 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6 Determination of Series Capacitance Vale for the Quartz Oscillator . . 22
Figure 7 Data Slicer Threshold Generation with External R-C Integrator . . . . . 24
Figure 8 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . 25
Figure 9 ASK/FSK mode datapath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10 Frequency characteristic in case of FSK mode . . . . . . . . . . . . . . . . . . 27
Figure 11 Frequency characteristic in case of ASK mode . . . . . . . . . . . . . . . . . . 28
Figure 12 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13 Voltage appearing on C18 during precharging process. . . . . . . . . . . . 30
Figure 14 Voltage transient on capacitor C13 attached to pin 20 . . . . . . . . . . . . 31
Figure 15 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 16 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17 Bottom Side of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18 Component Placement on the Evaluation Board. . . . . . . . . . . . . . . . . 44
Figure 19 P-TSSOP-28-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Preliminary Specification 48 V 1.1, 2004-10-20
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