Integrated Device Technology Inc IDT71321LA20J, IDT71321LA20PF, IDT71321LA25J, IDT71321LA25PF, IDT71321LA25TF Datasheet

Integrated Device Technology, Inc.

HIGH-SPEED 2K x 8
DUAL-PORT STATIC RAM
WITH INTERRUPTS

IDT71321SA/LA
IDT71421SA/LA

FEATURES:

• High-speed access
—Commercial: 20/25/35/45/55ns (max.)

• Low-power operation
—IDT71321/IDT71421SA

—Active: 550mW (typ.)
—Standby: 5mW (typ.)

—IDT71321/421LA

—Active: 550mW (typ.)
—Standby: 1mW (typ.)

• Two

• MASTER IDT71321 easily expands data bus width to 16-

• On-chip port arbitration logic (IDT71321 only)

•

• Fully asynchronous operation from either port

• Battery backup operation —2V data retention (LA Only)

• TTL-compatible, single 5V ±10% power supply

• Available in popular hermetic and plastic packages

• Industrial temperature range (–40°C to +85°C) is avail-

INT

flags for port-to-port communications

or-more-bits using SLAVE IDT71421

BUSY

output flag on IDT71321;

BUSY

input on IDT71421

able, tested to military electrical specifications

DESCRIPTION:

The IDT71321/IDT71421 are high-speed 2K x 8 Dual­Port Static RAMs with internal interrupt logic for interproces­sor communications. The IDT71321 is designed to be used
as a stand-alone 8-bit Dual-Port RAM or as a "MASTER"
Dual-Port RAM together with the IDT71421 "SLAVE" Dual­Port in 16-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-or-more­bit memory system applications results in full speed, error­free operation without the need for additional discrete logic.

Both devices provide two independent ports with sepa­rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by

CE

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance technol­ogy, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum­ing 200µW from a 2V battery.

The IDT71321/IDT71421 devices are packaged in a 52­pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.

FUNCTIONAL BLOCK DIAGRAM

OE

L

CE

L
L

R/

W

I/O0L- I/O

7L

(1,2) (1,2)

BUSY

L

A

10L

A

0L

NOTES:

1. IDT71321 (MASTER):
is open drain output and
requires pullup resistor of 270Ω.

IDT71421 (SLAVE):

2. Open drain output: requires pullup
resistor of 270Ω.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

BUSY

BUSY

is input.

INT

(2)

L

Address
Decoder

OE

R

CE

R

R/

W

R

I/O0R-I/O

BUSY

A

10R

A

0R

INT

7R

R

(2)

R

I/O

Control

MEMORY

ARRAY

11

ARBITRATION

CE

L

OE

L

R/

W

L

and

INTERRUPT

LOGIC

I/O

Control

Address
Decoder

11

CE

R

OE

R

R/

W

R

2691 drw 01

COMMERCIAL TEMPERATURE RANGE OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2691/6

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.03

1

IDT71321SA/LA AND IDT71421SA/LA

INDEX

IDT71321/421

PN64-1 / PP64-1

64-PIN TQFP

64-PIN STQFP

TOP VIEW

(3)

8

9
10
11
12
13
14
15

16

1

2

3

4

5

6

7

46
45
44
43
42
41
40
39
38
37
36
35
34

47

48

33

I/O

6R

N/C

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

OE

R

N/C
N/C

I/O

2L

A

0L

OE

L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

N/C

N/C

BUSY

L

CE

L

INT

L

2691 drw 03

R/

W

L

17

18

19

20

32

31

30

29

28

27

26

25

24

23

22

21

49

50

51

52

63

62

61

605958

57

56

55

54

53

64

GND

4L

I/O

5L

I/O

6L

I/O

7L

I/O

I/O

0R

I/O

1R

I/O

2R

I/O

3R

I/O

4R

I/O

5R

I/O

3L

N/C

N/C

GND

N/C

N/C

A

10R

V

CC

CE

R

R/

W

R

BUSY

R

N/C

N/C

A

10L

V

CC

N/C

INT

R

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

L

L

0L

NDEX

I/O
I/O
I/O
I/O

A

1L

8

A

2L

9

A

3L

10

A

4L

11

A

5L

12

A

6L

13

A

7L

14

A

8L

15

A

9L

16

0L

17

1L

18

2L

19
20

3L

OE

A

4L5L6L

I/O

I/O

10L

A

I/O

INT

7L

I/O

(1,2)

L

L

R/W

BUSY

CELVCCCE

234567474849505152

1

IDT71321/421

J52-1

PLCC

TOP VIEW

27262524232221 333231302928

0R1R2R3R4R6R5R

NC

GND

I/O

I/O

R

R

R/W

I/O

R

INT

BUSY

I/O

I/O

46
45

44
43
42
41
40
39
38
37
36
35
34

10R

A

I/O

OE
A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

NC
I/O

2691 drw 02

R

(3)

I/O

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

R

7R

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 V

with Respect to

GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

I

OUT DC Output 50 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a

any other conditions above those indicated in the operational sections
of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to
Vcc + 0.5V.

stress rating only and functional operation of the device at these or

Current

< 20mA for the period of VTERM >

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

CC

Commercial 0°C to +70°C 0V 5.0V ± 10%

2691 tbl 02

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

(2)

(2)

V

2691 tbl 03

Max. Unit

2691 tbl 04

V

2691 tbl 01

IH Input High Voltage 2.2 — 6.0

V

IL Input Low Voltage –0.5 — 0.8 V

(1)

NOTES:

IL (min.) = -1.5V for pulse width less than 10ns.

1. V

2. VTERM must not exceed Vcc + 0.5V.

CAPACITANCE

(1,3)

(TA = +25°C, f = 1.0MHz) TQFP ONLY

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output Capacitance VIN = 3dV 10 pF

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

3. 11pF max. for other packages.

6.03 2

IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE

(1,4)

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

71321X20 71321X25 71321X35 71321X55 71321X100

71421X25 71421X35 71421X55 71421X100

Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit

I

CC Dynamic Operating

Current (Both Ports Outputs open, LA — — 110 220 80 170 65 140 65 140
Active) f = f

I

SB1 Standby Current

(Both Ports - TTL f = f
Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55

I

SB2 Standby Current

(One Port - TTL
Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110

I

SB3 Full Standby CurrentCEL and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA

(Both Ports - All
CMOS Level Inputs V

SB4 Full Standby Current

I

(One Port - All
CMOS Level Inputs) V

NOTES: 2689 tbl 05

1. 'X' in part numbers indicates power rating (SA or LA).

2. At f = f

3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

4. Vcc = 5V, T

5. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”

of input levels of GND to 3V.

A=+25°C for Typ. and is not production tested. Vcc DC = 100mA (Typ)

CE

L and CER = VIL, MIL. SA — — 110 280 80 230 65 190 65 190 mA

(2)

MAX

COM'L. SA 110 250 110 220 80 165 65 155 65 155

LA 110 200 110 170 80 120 65 110 65 110

CE

L and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA

(2)

MAX

LA — — 30 60 25 60 20 45 20 45

LA 30 45 30 45 25 45 20 35 20 35

CE

"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA

CE

"B" = VIH

Open, f = f

CE

R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10

IN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V,f = 0

CE

"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA

CE

"B" > VCC -0.2V

IN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95

V

IN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70

(5)

MAX

LA — — 65 125 50 115 40 90 40 90

(2)

(3)

(5)

LA 65 125 65 115 50 90 40 75 40 75

LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4

LA — — 60 115 45 105 40 85 40 80

Active Port Outputs
Open, f = f

MAX

(2)

(VCC = 5.0V ± 10%)

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT71321SA

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

Ll| Input Leakage VCC = 5.5V, — 10 — 5 µA

|l

|lLO| Output Leakage

Current

Current

(1)

(1)

VIN = 0V to VCCVIN = GND to VCC

CE

= VIH, VOUT = 0V to VCC —10 — 5 µA

VCC = 5.5V

C-=S

= VIH, VOUT = GND to VCC

VOL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

(l/O

0-l/O7) lOL= 16mA

OL Open Drain Output Low lOL = 16mA — 0.5 — 0.5 V

V
Voltage (

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

NOTE: 1. At Vcc < 2.0V leakages are undefined. Supply CurrentVIN > VCC -0.2V or < 0.

BUSY,INT

)

6.03 3

IDT71421SA

(VCC = 5.0V ± 10%)

lDT71321LA
lDT71421LA

2691 tbl 06

IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE

DATA RETENTION CHARACTERISTICS (LA Version Only)

71321LA/71421LA

Symbol Parameter Test Conditions Min. Typ.

V

DR VCC for Data Retention 2.0 — 0 V

CCDR Data Retention Current VCC = 2.0V,

I

(3)

t

CDR

Chip Deselect to Data VIN > VCC - 0.2V or VIN≤ 0.2V 0 — — ns

CE

> VCC - 0.2V COM'L. — 100 1500 µA

Retention Time

(3)

R

t

Operation Recovery tRC

(2)

Time

NOTES:

1. V

CC = 2V, TA = +25°C, and is not production tested.

RC = Read Cycle Time

2. t

3. This parameter is guaranteed by device characterization but not production tested.

(1)

Max. Unit

—— ns

2691 tbl 07

DATA RETENTION WAVEFORM

DATA RETENTION MODE

V

CE

CC

4.5V 4.5V

t

CDR

V

IH

DATA

V

DR

≥

2.0V

V

DR

5V

OUT

775Ω

Figure 1. AC Output Test Load

AC TEST CONDITIONS

t

R

V

IH

2691 drw 04

1250Ω

30pF

100pF for 55 and 100ns versions

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1, 2, and 3

5V

1250Ω

DATA

OUT

775Ω

Figure 2. Output Test Load

HZ, tLZ, tWZ, and tOW)

(for t

* Including scope and jig.

5pF

2691 tbl 08

BUSY

or

INT

Figure 3.

AC Output Test Load

5V

270Ω

30pF

100pF for 55 and 100ns versions

BUSYBUSY

BUSY

BUSYBUSY

and I

NTNT

NT

NTNT

2691 drw 05

6.03 4