Integrated Device Technology Inc IDT70825L35GB, IDT70825L35PF, IDT70825L35PFB, IDT70825L45G, IDT70825L45GB Datasheet

Integrated Device Technology, Inc.

HIGH-SPEED 8K x 16
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)

IDT70825S/L

FEATURES:

• 8K x 16 Sequential Access Random Access Memory
(SARAM™)

- Sequential Access from one port and standard Random

Access from the other port

- Separate upper-byte and lower-byte control of the

Random Access Port

• High-speed operation

- 20ns tAA for random access port

- 20ns tCD for sequential port

- 25ns clock cycle time

• Architecture based on Dual-Port RAM cells

• Electrostatic discharge > 2001V, Class II

• Compatible with Intel BMIC and 82430 PCI Set

• Width and Depth Expandable

• Sequential side

- Address based flags for buffer control

- Pointer logic supports two internal buffers

• Battery backup operation—2V data retention

• TTL-compatible, single 5V (±10%) power supply

• Available in 80-pin TQFP and 84-pin PGA

• Military product compliant to MIL-STD-883.

• Industrial temperature range (–40°C to +85°C) is available,
tested to military electrical specifications.

DESCRIPTION:

The IDT70825 is a high-speed 8K x 16-bit Sequential
Access Random Access Memory (SARAM). The SARAM
offers a single-chip solution to buffer data sequentially on one
port, and be accessed randomly (asynchronously) through
the other port. The device has a Dual-Port RAM based
architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with
counter sequencing for the sequential (synchronous) access
port.

Fabricated using CMOS high-performance technology,
this memory device typically operates on less than 900mW of
power at maximum high-speed clock-to-data and Random
Access. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.

The IDT70825 is packaged in a 80-pin Thin Plastic Quad
Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

13

A

0-12

Random

R/

I/O0-15

LSB

MSB

Access

Port

Controls

16

13

Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2

Flow Control Buffer

Flag Status

SCLK

Sequential

Access

Port

Controls

8K X 16
Memory

Array

Data

Addr

R

R

Data

L

13

Addr

L

13

13

13

16

13

COMPARATOR

Reg.

13

Pointer/
Counter

16

RST

1
2

SR/

SI/O0-15

1

2

3016 drw 01

The IDT logo is a registered trademark and SARAM is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-3016/6

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.31 1

IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

(1,2)

INDEX

SI/O
SI/O

GND

N/C

SCE

SR/

RST

SLD

SSTRT

SSTRT

GND
GND

CNTEN

SOE

SCLK

GND

EOB

EOB

V
I/O

2

SI/O

80 79 78 77 76 75 74 73 72 71

1

1

0

2
3
4
5

W

6
7
8

2

9

1

10
11
12
13
14
15
16

2

17

1

18

CC

19

0

20

21 22 36 37 38 39 40

1

I/O

GND

5

3

4

CC

V

SI/O

SI/O

SI/O

23 24 25 26 27 28 29 30 31 32 33 34 35

4

2

3

CC

V

I/O

I/O

I/O

6

SI/O

5

I/O

7

SI/O

6

I/O

GND

8

10

9

SI/O

SI/O

SI/O

70 69 68 67 66 65

IDT70825

PN80-1

TQFP

TOP

(3)

VIEW

7

8

I/O

I/O

GND

11

SI/O

9

I/O

10

I/O

CC

V

11

I/O

12

SI/O

CC

V

13

SI/O

12

I/O

14

SI/O

13

I/O

15

SI/O

6364

14

I/O

GND

N/C

62 61

15

I/O

12

A

60

59
58
57
56
55
54
53
52

51
50

49

48
47
46
45

44
43
42

41

3016 drw 02

GND

11

A
A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

V

CC

V

CC

A

1

A

0

CMD

CE

LB

UB

R/

W

OE

63 61 60 58 55 54

V

CC

646562

NC

GND

68

V

CC

71

EOB1GND

0

I/O

73

66

67

69

72

I/O

I/O

I/O

I/O

1

2

3

4

I/O7I/O6GND SI/O

75

I/O

9

76

I/O

10

79

I/O

12

818283

70

77

80

I/O

I/O

I/O

74

5

I/O

8

78

V

CC

11

13

I/O14NC V

125

OE

GND

I/O

15

8434 6915131618

NC

R/

W

UB

CNTEN

GND

59 56 49

EOB2SOE

RST

57 53

SCLK GND

IDT70825

G84-3

84-PIN PGA

TOP VIEW

7

CMD

811101214 17 20

LB

CE

CC

A

0

CC

V

A

5

1

A

48 46 45

51

SSTRT

50

SLD

52

SSTRT

2

1

NC

SR/W GND NC

47 44

SCE

SI/O

33 35

32 31

SI/O

(3)

28 29

SI/O

2

A

A

7

4

A

A

3

A

A

6

12

10

A

8

ABCDEFGHJKL

INDEX

43

SI/O

0

41

SI/O

38

SI/O4SI/O

8

SI/O

9

SI/O

V

CC

26

SI/O

23

NC SI/O

22 24

A

12

19 21

A9A

10

14

1

2

7

42

40

SI/O

39

V

37

34

GND

36

SI/O

30

SI/O

27

SI/O

25

GND

CC

3

5

6

11

13

15

11

3016 drw 03

11

10

09

08

07

06

05

04

03

02

01

NOTES:

1. All V

CC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. This text does not indicate orientation of the actual part-marking.

6.31 2

IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS: RANDOM ACCESS PORT

SYMBOL NAME I/O

A

0-A12 Address Lines I Address inputs to access the 8192-word (16 bit) memory array.

I/

O0-I/O15 Inputs/Outputs I Random access data inputs/outputs for 16-bit wide data.

CE

CMD

Chip Enable I When CE is LOW, the random access port is enabled. When CE is HIGH, the random access

Control Register I When
Enable access the control register, the flag register, and the start and end of buffer registers.

R/

W

OE

LB,UB

Read/Write Enable I If CE is LOW and

Output Enable I When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O

Lower Byte, Upper I When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/
Byte Enables I/

V

CC Power Supply Seven +5V power supply pins. All Vcc pins must be connected to the same +5V VCC supply.

GND Ground Ten Ground pins. All Ground pins must be connected to the same Ground supply.

(1)

DESCRIPTION

port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All
data is retained during

CE

= VIH, unless it is altered by the sequential port. CE and

CMD

be LOW at the same time.

CMD

is LOW, Address lines A

0-A2, R/

W

, and inputs/outputs I/O0-I/O11, are used to

CMD

CE

may not be LOW at the same time.

CMD

is HIGH, data is written into the array when R/W is LOW and read out of the
array when R/W is HIGH. If CE is HIGH and
mand registers. CE and

CMD

may not be LOW at the same time.

CMD

is LOW, R/W is used to access the buffer com-

outputs are in the high-impedance state.

O7 are tri-stated and blocked during read and write operations.

I/

O15 in the same manner and is asynchronous from

LB

.

UB

controls access for I/O8-

may not

and

O0-

3016 tbl 01

PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT

SYMBOL NAME I/O

SI/O0-15 Inputs I/O Sequential data inputs/outputs for 16-bit wide data.
SCLK Clock I SI/

SCE

CNTEN

SR/

SLD

Chip Enable I When

Counter Enable I When

W

Read/Write Enable I When SR/W and

Address Pointer I When
Load Control changes. When

SSTRT

1, Load Start of I When

SSTRT

2 Address Register address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in

EOB

1, End of Buffer Flag O

EOB

2 stored in the end of buffer registers. The flags can be cleared by either asserting

SOE

RST

NOTE:

1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.

Output Enable I

Reset I When

(1)

O0-SI/O15,

SCE

, SR/W, and

DESCRIPTION

SLD

are registered on the LOW-to-HIGH transition of SCLK.
Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH
transition of SCLK when

SCE

is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of

SCLK. When

SCE

CNTEN

is LOW.

is HIGH, the sequential access port is disabled into powered-down mode on
the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All
data is retained, unless altered by the random access port.

CNTEN

is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.

This function is independant of

SCE

are LOW, a write cycle is initiated on the LOW-to-HIGH transition of

SCLK. When SR/W is HIGH, and

SCE

.

SCE

and

SOE

are LOW, a read cycle is initiated on the
LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High
transistion of SCLK if SR/W or

SLD

is sampled LOW, there is an internal delay of one cycle before the address pointer

SLD

is LOW, data on the inputs SI/
on the LOW-to-HIGH transition of SCLK. On the cycle following
changes to the address location contained in the data-in register.
not be LOW while

SSTRT

internal registers.
following

EOB

1 or

SLD

EOB

SLD

is LOW or during the cycle following

1 or

SSTRT

SSTRT

.

2 is output LOW when the address pointer is incremented to match the address

by writing zero into bit 0 and/or bit 1 of the control register at address 101.

SCE

is High.

O0-SI/O11 is loaded into a data-in register

SLD

, the address pointer

SSTRT

1 and

SSTRT

2 may

SLD

.

2 is LOW, the start of address register #1 or #2 is loaded into the

1 and

SSTRT

2 may not be LOW while

SLD

is LOW or during the cycle

RST

EOB

1 and

LOW or

EOB

dependent on separate internal registers, and therefore separate match addresses.

SOE

controls the data outputs and is independent of SCLK. When
and the sequentially addressed data is output. When
the high-impedance state.

RST

is LOW, all internal registers are set to their default state, the address pointer is set

to zero and the

EOB

1 and

SOE

is asynchronous to SCLK.

EOB

2 flags are set HIGH.

SOE

RST

is HIGH, the SI/O output bus is in

is asynchronous to SCLK.

SOE

is LOW, output buffers

2 are

3016 tbl 02

6.31 3

IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

T

A Operating 0 to +70 –55 to +125 ° C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

T

STG Storage –55 to +125 –65 to +150 °C

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES: 3016 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time

2. V
or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND VCC

Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

3016 tbl 04

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.2 — 6.0

V

IL Input Low Voltage –0.5

NOTES: 3016 tbl 05

1. VIL > –1.5V for pulse width less than 10ns.

TERM must not exceed Vcc + 0.5V.

2. V

CAPACITANCE

(1)

(1)

— 0.8 V

(TA = +25°C, F = 1.0MHz)TQFP ONLY

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output VOUT = 3dV 10 pF

Capacitance

NOTES: 3016 tbl 06

1. This parameter is determined by device characterization, but is not
production tested.

2. 3dV references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

(2)

(2)

V

Max. Unit

DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE (V

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I
|I

LO| Output Leakage Current VCC = Max.

VOL Output Low Voltage IOL = 4mA, VCC = Min. — 0.4 — 0.4 V
V

OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — V

NOTE:

1. At Vcc ≤ 2.0V input leakages are undefined.

(1)

CC = 5.0V ± 10%)

IDT70825S IDT70825L

VCC = Max. VIN = GND to VCC — 5.0 — 1.0 µA

CE

and

SCE

= VIH — 5.0 — 1.0 µA

V

OUT = GND to VCC

3016 tbl 07

6.31 4

IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE

(1)

AND SUPPLY VOLTAGE RANGE

Symbol Parameter Condition Version Typ.

I

CC Dynamic Operating

Current Open,
(Both Ports Active) f = f

SB1 Standby Current

I

(Both Ports - TTL Level
Inputs) f = f

I

SB2 Standby Current

(One Port - TTL Level Active Port Outputs L —— — — 95 250 90 250
Input) Open, f = f

I

SB3 Full Standby Current Both Ports

(Both Ports - CMOS
Level Inputs) V

I

SB4 Full Standby Current One Port

(One Port - CMOS
Level Inputs) Outputs Open

NOTES:

1. "X" in part number indicates power rating (S or L).

2. V

CC = 5V, Ta = +25°C; guaranteed by device characterization but not production tested.

3. At f = f

4. f = 0 means no address or control lines change.

5.

6.

7. If one port is enabled (either CE or

MAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.

SCE

may transition, but is Low (

SCE

may be ≤ 0.2V, after it is clocked in, since SCLK=V

< 0.2V, and TTL High = VIH and Low = VIL.

Low

CE

= VIL, Outputs MIL. S — — — — 160 400 155 400 mA

MAX

SCE

and CE > VIH

CMD

= V

MAX

CE

or

SCE

≥ V

IN ≥ VCC - 0.2V or COM’L.S 1.0 15 1.0 15 1.0 15 1.0 15

V

IN ≤ 0.2V, f = 0

SCE

≥ V

(Active port), f
V

IN ≥ VCC - 0.2V or

V

IN ≤ 0.2V L 110 200 100 190 90 180 85 180

IL) when clocked in by SCLK.

SCE

=V

SCE

= Low) then the other port is disabled (

(VCC = 5.0V ± 10%)

70825X20 70825X25 70825X35 70825X45

Test Com'l. Only Com'l. Only

SCE

(3)

= V

IL

COM’L. S 180 380 170 360 160 340 155 340

L — — — — 160 340 155 340

(5)

L 180 330 170 310 160 290 155 290

(7)

MIL. S — — — — 20 85 16 85 mA

IH L— — — — 20 6516 65

(3)

COM’L. S 25 70 25 70 20 70 16 70

L25502550 20501650

SCE

= VIH MIL. S — — — — 95 290 90 290 mA

(3)

MAX

COM’L. S 115 260 105 250 95 240 90 240

L 115 230 105 220 95 210 90 210

CE

and MIL. S — — — — 1.0 30 1.0 30 mA

CC - 0.2V

CE

CC - 0.2V

(6,7)

(4)

L — — — — 0.2 10 0.2 10

L 0.2 5 0.2 5 0.2 5 0.2 5

or MIL. S — — — — 90 260 85 260 mA

(6)

(3)

= fMAX

COM’L. S 110 240 100 230 90 220 85 220

IH must be clocked in prior to powerdown.

L — — — — 90 215 85 215

(2)

Max. Typ.

SCE

or CE = High, respectively). CMOS High

(2)

Max. Typ.

(2)

Max. Typ.

(2)

> Vcc - 0.2V and

Max. Unit

3016 tbl 08

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY)

Symbol Parameter Test Condition Min. Typ.

V

DR VCC for Data Retention VCC = 2V 2.0 — — V

I

CCDR Data Retention Current

(3)

t

CDR

(3)

t

R

NOTES :

1. T

A = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.

RC = Read Cycle Time

2. t

3. This parameter is guaranteed by device characterization, but is not production tested.

4. To initiate data retention,

Chip Deselect to Data Retention Time
Operation Recovery Time

(VLC < 0.2V, VHC > VCC - 0.2V)

IH must be clocked in.

SCE

= V

(1)

Max. Unit

CE

= VHC MIL. — 100 4000 µA

V

IN = VHC or = VLC COM’L. — 100 1500

SCE
CMD

(4)

= VHC

= VHC tRC

when SCLK= 0 — — ns

(2)

6.31 5

——ns

3016 tbl 09

IDT70825S/L

1

2

3

4

5

6

7

8

20 40 60 80 100 120 140 160 180

200

CAPACITANCE (pF)

10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
capacitance.

3016 drw 07

tAA/tCD/tEB
(Typical, ns)

-1

-2

-3

HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION AND POWER DOWN/UP WAVEFORM (RANDOM AND SEQUENTIAL PORT)

(1,2)

DATA RETENTION MODE

V

CC

CE

4.5V

t

CDR

V

IH

≥

V

DR

2V

V

DR

4.5V
t

R

V

IH

SCLK

SCE

t

I

CC

NOTES :

1.

SCE

is synchronized to the sequential clock input.

CMD

> VCC - 0.2V.

2.

PD

I

SB

t

PU

I

SB

3016 drw 04

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns Max.
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load Figures 1, 2, and 3

DATA

OUT

Figure 1. AC Output Test Load

5V

893Ω

30pF347Ω

3016 drw 05

5V

893Ω

DATA

OUT

5pF347Ω

3016 drw 06

Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ,

3016 tbl 10

Figure 3. Lumped Capacitance Load Typical Derating Curve

6.31 6

t

BHZ, tOHZ, tWHZ, tCKHZ, and tCKLZ)

Including scope and jig.

IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I – RANDOM ACCESS READ AND WRITE

(1,2)

Inputs/Outputs MODE

CECE

CE

CECE

CMDCMD

CMD

CMDCMD

R/

WW

OEOE

LBLB

W

OE

WW

OEOE

LB

LBLB

UBUB

UB

UBUB

I/O

0-I/O7 I/O8-I/O-

L H H L L L DATAOUT DATAOUT Read both Bytes.
L H H L L H DATA
L H H L H L High-Z DATA
LH LH
LH LH
LH LH

(3)

L L DATAIN DATAIN Write to both Bytes.

(3)

L H DATAIN High-Z Write to lower Byte only.

(3)

H L High-Z DATAIN Write to upper Byte only.

OUT High-Z Read lower Byte only.

OUT Read upper Byte only.

H H X X X X High-Z High-Z Both Bytes deselected and powered down.

L H H H X X High-Z High-Z Outputs disabled but not powered down.

L H X X H H High-Z High-Z Both Bytes deselected but not powered down.
HL LH
HL HLL

NOTES:

1. H = V

2.

3. If OE = V

4. Byte operations to control register using UB and LB separately are also allowed.

IH, L = VIL, X = Don't Care, and High-Z = High-impedance.

RST, SCE, CNTEN

operation.

IL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.

TRUTH TABLE II – SEQUENTIAL READ

(3)L(4)L(4)

, SR/W,

SLD, SSTRT

(4)L(4)

DATAIN DATAIN Write I/O0-I/O12 to the Buffer Command Register.

DATAOUT DATAOUT Read contents of the Buffer Command Register via I/O0-I/O12.

1,

SSTRT

2, SCLK, SI/O

(1,2,3,6,8)

0-SI/O15,

EOB

1,

EOB

2, and

SOE

are unrelated to the random access port control and

Inputs/Outputs MODE

SCLK

SCE

SCESCE

CNTENCNTEN

CNTEN

CNTENCNTEN

SR/

W

WW

WW

EOB1EOB1

EOB1

EOB1EOB1

EOB2EOB2

EOB2

EOB2EOB2

SOESOE

SOE

SOESOE

SI/O

SCESCE

L L H LOW LAST L [EOB1] Counter Advanced Sequential Read with
L H H LAST LAST L [EOB1 - 1] Non-Counter Advanced Sequential Read, without
L L H LAST LOW L [EOB2] Counter Advanced Sequential Read with
L H H LAST LAST L [EOB2 - 1] Non-Counter Advanced Sequential Read without
L L H LOW LOW H HIGH-Z Counter Advanced Sequential Non-Read with

reached.

TRUTH TABLE III – SEQUENTIAL WRITE

(1,2,3,4,5,6,7,8)

Inputs/Outputs MODE

SCESCE

SCLK

CNTENCNTEN

SCE

CNTEN

SCESCE

CNTENCNTEN

L H L LAST LAST H SI/O
L L L LOW LOW H SI/O

SR/

WW

W

WW

EOB1EOB1

EOB1

EOB1EOB1

EOB2EOB2

EOB2

EOB2EOB2

SOESOE

SOE

SOESOE

SI/O

IN Non-Counter Advanced Sequential Write, without
IN Counter Advanced Sequential Write with

EOB

1 and
H H X LAST LAST X High-Z No Write or Read due to Sequential port Deselect. No counter advance.
H L X NEXT NEXT X High-Z No Write or Read due to Sequential port Deselect. Conter does advance.

NOTES:

1. H = V

2.

3.CE, OE, R/W,

4.

5. SI/

6. "LAST" refers to the previous value still being output, no change.

7. Termination of a write is done on the Low-to-High transition of SCLK if SR/W or

8. When

IH, L = VIL, X = Don't Care, and High-Z = High-impedance. LOW = VOL.

RST, SLD, SSTRT

with the sequential port operation (due to the counter and register control).

SOE

must be HIGH (

edge of the clock during the cycle in which SR/W = V

OIN refers to SI/O0-SI/O15 inputs.

CLKEN

Enable Cycle after Reset, Read (and write) Cycle".

1,

SSTRT

2 are continuously HIGH during a sequential write access, other than pointer access operations.

CMD, LB, UB

SOE

=V

=Low, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter

0-I/O15 are unrelated to the sequential port control and operation except for

, and I/O

IH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising

IL.

CMD

should be HIGH (

SCE

is High.

CMD

CMD

which must not be used concurrently

IH) during sequential port access.

= V

EOB

EOB

EOB

EOB

1 reached.

EOB

2 reached.

EOB

2 reached.

EOB

1 and

1 or

EOB

2 reached.

3016 tbl 11

1 reached.

EOB

2

3016 tbl 12

2 reached

3016 tbl 13

6.31 7