Integrated Device Technology Inc IDT707288L20G, IDT707288L20PF, IDT707288L25G, IDT707288L25PF, IDT707288S20G Datasheet
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HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
FEATURES:
• 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
- Four independent 16K x 16 banks
- 1 Megabit of memory on chip
• Fast asynchronous address-to-data access time: 20ns
• User-controlled input pins included for bank selects
• Independent port controls with asynchronous address &
data busses
• Four 16-bit mailboxes available to each port for interprocessor communications; interrupt option
• Interrupt flags with programmable masking
• Dual Chip Enables allow for depth expansion without
external logic
•UB and LB are available for bus matching to x8 or x16
busses; also support very fast banking
• TTL-compatible, single 5V (±10%) power supply
• Available in a 100-pin Thin Quad Plastic Flatpack (TQFP)
and a 108-pin ceramic Pin Grid Array (PGA)
ADVANCED
IDT707288S/L
The IDT logo is a registered trademark of Integrated Device Technology
COMMERCIAL TEMPERATURE RANGE OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-3592/-
1
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
6.29
DESCRIPTION:
The IDT707288 is a high-speed 64K x 16 (1M bit) BankSwitchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports
with separate controls, addresses, and I/O pins for each port,
allowing each port to asynchronously access any 16K x 16
memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank
select pin inputs under the user's control. Mailboxes are
provided to allow inter-processor communications. Interrupts
are provided to indicate mailbox writes have occurred. An
automatic power down feature controlled by the chip enables
(
CE
0 and CE1) permits the on-chip circuitry of each port to
enter a very low standby power mode and allows fast depth
expansion.
The IDT707288 offers a maximum address-to-data access
time as fast as 20ns, while typically operating on only 900mW
of power, and is available in a 100-pin Thin Quad Plastic
Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
MUX
R/
L
0L
CE
1L
L
L
L
I/O
8L-15L
I/O
0L-7L
A
13L
A
0L
(1)
A
5L
(1)
A
0L
(1)
L/L
L
R/
L
L
MAILBOX
INTERRUPT
LOGIC
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
MUX
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
MUX
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
R/
R
0R
CE
1R
R
R
R
I/O
8R-15R
I/O
0R-7R
A
13R
A
0R
(1)
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
A
5R
(1)
A
0R
(1)
R/R
R
R/
R
R
3592 drw 01
R
R
L
L
BKSEL
3
(2)
BKSEL
0
(2)
BANK
SELECT
BA
1R
BA
0R
BA
1L
BA
0L
FUNCTIONAL BLOCK DIAGRAM
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL
= VIH, the pins serve as memory address inputs. When
MBSEL
= VIL, the pins
serve as mailbox address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS COMMERCIAL TEMPERATURE RANGE
6.29 2
PIN NAMES
A0 - A13
(1,6)
Address Inputs
BA
0 - BA1
(1)
Bank Address Inputs
MBSEL
(1)
Mailbox Access Control Gate
BKSEL
(2)
Bank Select Inputs
R/
W
(1)
Read/Write Enable
OE
(1)
Output Enable
CE0
, CE1
(1)
Chip Enables
UB, LB
(1)
I/O Byte Enables
I/O
0 – I/O15
(1)
Bidirectional Data Input/Output
INT
(1)
Interrupt Flag (Output)
(3)
VCC
(4)
+5V Power
GND
(5)
Ground
FUNCTIONALITY:
The IDT707288 is a high-speed asynchronous 64K x 16
Bank-Switchable Dual-Ported SRAM, organized in four 16K x
16 banks. The two ports are permitted independent, simultaneous access into separate banks within the shared array.
There are four user-controlled Bank Select input pins , and
each of these pins is associated with a specific bank within the
memory array. Access to a specific bank is gained by placing
the associated Bank Select pin in the appropriate state: VIH
assigns the bank to the left port, and VIL assigns the bank to
the right port (See Truth Table I). Once a bank is assigned to
a particular port, the port has full access to read and write
within that bank. Each port can be assigned as many banks
within the array as needed, up to and including all four banks.
The IDT707288 provides mailboxes to allow inter-processor communications. Each port has four 16-bit mailbox
registers available to which it can write and read and which the
opposite port can read only. These mailboxes are external to
the common SRAM array, and are accessed by setting
MBSEL
= VIL while setting CE = VIH. Each mailbox has an
associated interrupt: a port can generate an interrupt to the
opposite port by writing to the upper byte of any one of its four
16-bit mailboxes. The interrupted port can clear the interrupt
by reading the upper byte. This read will not alter the contents
of the mailbox.
If desired, any source of interrupt can be independently
masked via software. Two registers are provided to permit
interpretation of interrupts: the Interrupt Cause Register and
the Interrupt Status Register. The Interrupt Cause Register
gives the user a snapshot of what has caused the interrupt to
be generated - the specific mailbox written to. The information
in this register provides post-mask signals: Interrupt sources
that have been masked will not be updated. The Interrupt
Status Register gives the user the status of all bits that could
potentially cause an interrupt regardless of whether they have
been masked. Truth Table II gives a detailed explanation of
the use of these registers.
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
NOTES:
NOTES:
1. Duplicated per port.
2. Each bank has an input pin assigned that allows the user to toggle the
assignment of that bank between the two ports. Refer to Table I for more
details.
3. Generated upon mailbox access.
4. All Vcc pins must be connected to power supply.
5. All GND pins must be connected to ground supply.
6. The first six address pins for each port serve dual functions. When
MBSEL
= VIH, the pins serve as bank address or memory address inputs. When
MBSEL
= VIL, the pins serve as mailbox address inputs.
PIN CONFIGURATIONS
(1,2)
3592 tbl 01
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT707288
PN100-1
100-PIN
TQFP
TOP VIEW
(3)
GND
OE
R
R/
W
R
MBSEL
R
CE
1R
CE
0R
BKSEL
3
NC
GND
A
9R
A
10R
A
8R
A
7R
A
6R
A
11R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
UB
R
LB
R
3592 drw 02
I/O
15L
GND
OE
L
R/
W
L
MBSEL
L
CE
1L
CE
0L
Vcc
BKSEL
0
A
11L
A
10L
NC
A
9L
A
8L
A
7L
A
6L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
UB
L
LB
L
GND
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
0R
I/O
0L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7
L
I/O
3L
I/O
1R
I/O
7R
I/O
8R
I/O
9R
I/O
8L
I/O
9L
I/O
6R
A
4R
A
5L
A
4L
A
3R
A
0R
A
12R
INT
R
INT
L
BKSEL
1
A
3L
A
5R
GND
Vcc
I/O1
L
Vcc
GND
A
13R
NC
BA
0RBA1R
A1RA
2R
BKSEL
2
GND
NC
A
0L
A
12L
BA0LBA
1L
A1LA
2L
A
13L
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