High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Description
The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. The IDT7027 is
packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 108-pin ceramic
Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-PRF-38535 QML, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Pin Configurations
815754
A
10R
12
A
11
A
10
A
09
INT
08
GND
07
BUSY
06
A
05
A
04
A
03
107
A
02
108
A
01
(1,2,3)
(con't.)
807774726968656360
A
A
11R
8378767370676461598456
A
8R
7R
8687
8279757166625850
A
5R
4R
85
8890
A
3R
1R
89
9192
R
A
0R
93
9495
BUSY
S
M/
98
9796
L
INT
L
102
10099
A
0L
2L
5L
8L
9L
1L
106
103101
A
4L
105104
1
A
6L
2
5
A
A
11L
3 6 9 111415182023
12L
A
A
A
A
A
A
14R
NC
10L
14L
NCA
13R
9R
6R
2R
3L
7L
NC
NC
A
12R
R
4
8
A
13L
7
10
NC
LB
L
UB
LB
UB
CE
R
R
NC
NC
0L
SEM
CE
CE
IDT7027G
G108-1
108-Pin P GA
Top View
12
CE
13
SEM
L
Vcc
GND
R/
OE
(4)
17
GND
16
OE
R/
GND
W
GND
R
R
I/O
(5)
21
I/O
19
GND
L
W
L
15R
14L
I/O
I/O
25
I/O
22
I/O
I/O
NC
14R
11R
10L
13L
15L
R
1R
0R
1L
L
I/O
13R
I/O
12R
5551
NC
5249
NC
4846
I/O
6R
4443
I/O
2R
3940
I/O
1L
3537
I/O
4L
3134
Vcc
28
NC
24
I/O
11L
I/O
12L
I/O
10R
I/O
9R
I/O
8R
VccA
I/O4RI/O
I/O
1R
I/O
0L
2L
I/O
5L
32
I/O7L
2930
NC
2627
I/O
9L
NC
53
NC
I/O
47
I/O
45
42
I/O
41
GND
38
GNDI/O
36
I/O
33
I/O
I/O
NCNC
7R
5R
3R
0R
3L
6L
8L
ABCDEFGHJK LM
INDEX
NOTES:
CC pins must be connected to power supply.
1. All V
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
3
3199 drw 03
Pin Names
Left PortRight PortNames
CE
0L
, CE
W
L
R/
OE
L
14L
A0L - A
I/O0L - I/O
SEM
L
UB
L
LB
L
INT
L
BUSY
L
1L
15L
CE
R/
OE
A0R - A
I/O0R - I/O
SEM
UB
LB
INT
BUSY
S
M/
CC
V
0R
, CE
W
R
R
14R
R
R
R
R
R
GNDGround
1R
15R
Chip Enables
Read /Write En able
Output Enable
Address
Dat a In p ut/ O ut p ut
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interr up t Flag
Busy Flag
Master or Slave Select
Power
3199 tbl 01
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Truth Table I Chip Enable
CECE
CE
0
1
Mode
IL
V
L
0.2V>VCC -0.2VPort Selected (CMOS Active)
<
IH
V
XV
H
VCC -0. 2VXP o rt De s e le cte d (C MO S Inac tiv e )
>
X<
NOTES:
1. Chip Enable references are shown above with the actual CE
2. Port "A" and "B" references are located where CE is used.
3. "H" = V
IH and "L" = VIL.
IH
V
Port Se lected (TTL Active)
XPort Deselected (TTL Inactive)
IL
Port Deselected (TTL Inactive)
0.2VPort Deselected (CMOS Inactive)
0 and CE1 levels, CE is a reference only.
Truth Table II Non-Contention Read/Write Control
(1)
Inputs
CE
(2)
R/W
OEUBLBSEM
HXXXXHHigh-ZHigh-ZDeselected: Power-Down
XXXHHHHigh-ZHigh-ZBoth By tes Des ele cted
LLXLHHDATAINHigh-ZWrite to Upper Byte Only
LLXHLHHigh-ZDAT A
I/O
Outputs
8-15
I/O
0-7
IN
Wri te to Lo we r B y te O nly
Mode
3199 tbl 02
LLXLLHDATAINDAT AINWri te to Bo th By te s
LHLLHHDATA
LHLHLHHigh-ZDATA
LHLLLHDATA
OUT
OUT
High-ZRead Upper Byte Only
OUT
Re ad Lo we r By te Only
OUT
DAT A
Read Both Bytes
XXHXXXHigh-ZHigh-ZOutputs Disabled
NOTES:
0L— A14L≠ A0R— A14R.
1. A
2. Refer to Chip Enable Truth Table.
Truth Table III Semaphore Read/Write Control
(1)
Inputs
CE
(2)
R/
W
OEU BLBSEM
HHLXXLDATA
XHLHHLDATA
H
X
↑
↑
XXXLDATAINDAT AINWrite I/O0 into Semaphore Flag
XHHLDATAINDAT AINWrite I/O0 into Semaphore Flag
LXXLXL
LXXXLL
NOTES:
1. There are eight semaphore flags written to via I/O
2. Refer to Chip Enable Truth Table.
0
and read from all the I/Os (I/O0 __I/O15). These eight semaphore flags are addressed by A0-A2.
6.42
4
Outputs
8-15
I/O
OUT
OUT
____________
____________
I/O
DAT A
DAT A
0-7
OUT
Read Data in Semaphore Flag
OUT
Read Data in Semaphore Flag
No t All o we d
No t All o we d
3199 t bl 03
Mode
3199 tbl 04
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
SymbolRatingCommercial
(2)
V
TERM
Te rminal Vol tage
with Res pe c t
to GND
T
BIAS
T emperature
Und e r B ia s
STG
T
Storage
T emperature
I
OUT
DC Output
Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
2. Industrial temperature: for other speeds packages and powers, contact your
sales office.
Capacitance
(TA = +25°C, f = 1.0mhz) TQFP ONLY
SymbolParameterConditions
IN
C
Inp ut Cap a ci tanc eVIN = 3dV9pF
Output
OUT
C
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
CapacitanceV
Ambient
TemperatureGNDVcc
O
C to +70OC0V5.0V + 10%
A. This is the "instant on" case temperature.
(1)
(2)
Max.Unit
OUT
= 3dV10pF
3199 tbl 06
3199 tbl 08
GNDGround000V
V
Input Hi g h Vol tag e2.2
IH
V
Inp ut Lo w Vol tag e-0.5
IL
NOTES:
IL > -1.5V for pulse width less than 10ns.
1. V
TERM must not exceed Vcc + 10%.
2. V
____
(1)
____
(2)
6.0
0.8V
3199 tbl 07
V
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
SymbolParameterTest Conditions
|ILI|Input Le akag e Curre nt
LO
|I
|Outp ut Le akag e Curre nt
OL
V
V
NOTE:
1. At Vcc
Outpu t Low Voltag eIOL = 4mA
OH
Output High VoltageIOH = -4mA2.4
< 2.0V, input leakages are undefined.
(1)
VCC = 5.5V, VIN = 0V to V
IH
OUT
, V
CE
= V
= 0V to V
6.42
(VCC = 5.0V ± 10%)
CC
CC
5
7027S7027L
___
___
___
10
10
0.4
___
2.4
UnitMin.Max.Min.Max.
___
___
___
5µA
5µA
0.4V
___
V
3199 t bl 09
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
S
L
S
L
S
L
S
L
S
L
(1,6,7)
7027X20
Com'l Only
(2)
185
____
____
____
____
120
____
____
0.2
____
____
115
____
____
(VCC = 5.0V ± 10%)
7027X25
Com'l, Ind
& Military
Max.Typ.
325
180
285
170
____
170
____
170
404085
70
____
4040100803030100802020100
____
215
105
185
105
____
105
____
105
1551.0
0.2
____
1.0
____
0.23010
190
100
160
100
____
100
____
100
Temperature and Supply Voltage Range
SymbolParam eterTest ConditionVersionTyp.
Dynam ic Op e rati ng
I
CC
Current
(Both Ports Active)
I
Standby Current
SB1
(Both Po rts - TTL Lev e l
Inputs)
I
Standby Current
SB2
(On e Po rt - TTL Lev e l
Inputs)
I
Full Standb y Current
SB3
(Both Po rts - Al l CMO S
Le v e l In p uts )
I
Full Standb y Current
SB4
(On e Po rt - A ll CMOS
Le v e l In p uts )
CE
, Outputs Disabled
= V
IL
SEM
= V
IH
(3)
f = f
MAX
CE
CE
=
= V
L
R
SEM
R
f = f
MAX
CE
"A"
Active Port Outputs Disabled,
f=f
MAX
SEM
R
Bo th P o rts
CE
> VCC - 0.2V
R
V
> VCC - 0.2V o r
IN
V
< 0.2V, f = 0
IN
SEM
R
CE
"A"
CE
"B"
SEM
R
V
> VCC - 0.2V o r
IN
V
< 0.2V, Ac tiv e P o rt Outp uts
IN
Disable d , f = f
IH
SEM
=
= V
L
(3)
= VIL and
(3)
SEM
=
= V
L
CE
and
L
SEM
=
> VCC - 0.2V
L
< 0.2V a nd
> VCC - 0.2V
SEM
=
> VCC - 0.2V
L
MAX
CE
(4)
IH
= V
"B"
IH
(5)
(3)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
2. V
3. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
COM'LSL185
MIL &
IND
COM'LSL555590
MIL &
IND
(5)
COM'LSL120
IH
MIL &
IND
COM'LSL1.0
MIL &
IND
COM'LSL115
MIL &
IND
(2)
Max.Typ.
305
160
265
160
345
160
305
160
60
200
1709595
230
2009595
1551.0
170
1459090
200
1759090
7027X35
Com 'l &
Military
(2)
Max.Typ.
295
255
335
295
30
30
215
0.2
1.0
0.23010
85
60
185
1558585
1858585
15
5
160
1358080
190
1658080
7027X55
Com 'l &
Military
(2)
Max.Unit
150
270
150
230
150
310
150
270
20
20
165
135
195
165
1.0
0.2
1.0
0.23010
135
110
175
150
mA
8560mA
80
mA
155mA
mA
3199 tbl 1 0
6.42
6
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