IDT IDT54FCT821A, IDT54FCT821B, IDT54FCT821C, IDT54FCT823A, IDT54FCT823B User Manual

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

Integrated Device Technology, Inc.

HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS

IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C

FEATURES:

• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full tem­perature and voltage supply extremes

• IDT54/74FCT821A/823A/824A/825A equivalent to
FAST speed

• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST

• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST

• Buffered common Clock Enable (EN) and asynchronous

Clear input (

•I

OL = 48mA (commercial) and 32mA (military)

• Clamp diodes on all inputs for ringing suppression

• CMOS power levels (1mW typ. static)

• TTL input and output compatibility

• CMOS output level compatible

• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)

• Product available in Radiation Tolerant and Radiation
Enhanced versions

• Military product compliant to MIL-STD-883, Class B

CLR

)

DESCRIPTION:

The IDT54/74FCT800 series is built using an advanced

dual metal CMOS technology.

The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (

CLR

) – ideal for parity bus interfacing in high-perform­ance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring HIGH IOL/IOH.

family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.

OE

1, OE2, OE3) to allow multiuser control of the

All of the IDT54/74FCT800 high-performance interface

FUNCTIONAL BLOCK DIAGRAMS

IDT54/74FCT821/823/825

D0 DN

EN

CLR

CL

D

Q

CP

Q

CP

OE

Y0 YN

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

D

CL

CP

Q

Q

2608 cnv* 01

IDT54/74FCT824

EN

CLR

CP

OE

D0 DN

CL

D

Q

CP

Q

Y0 YN

D

CP

CL

Q

Q

2608 cnv* 02

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992

1992 Integrated Device Technology, Inc. 7.19 DSC-4618/2

1

IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS LOGIC SYMBOLS

IDT54/74FCT821 10-BIT REGISTER

INDEX

V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
CP

CC
0
1
2
3
4
5
6
7
8
9

D
D
D

NC

D
D
D

0

1

D

OE

D

32

4

2

5

3

6

4

7
8

5

9

6

10

7

11

L28-1

1213

9

8

D

D

GND

1

NC

NC

CC

V

CP

0

1

Y

Y

CP

OE

10

D

D

QY

10

CP

262728

Y
Y
Y
NC
Y
Y
Y

2
3
4

5
6
7

25
24
23
22
21
20
19

1817161514

9

8

Y

Y

LCC

TOP VIEW

2608 cnv* 03

OE

D
D
D
D
D
D
D
D
D
D

GND

1

0

2

1

3
4
5
6
7

SO24-2

8
9
10

11

P24-1
D24-1
E24-1

2
3
4
5
6
7
8
9

12

24
23
22
21
20
19

&

18
17
16
15
14
13

DIP/SOIC/CERPACK

TOP VIEW

IDT54/74FCT823/824 9-BIT REGISTERS

24
23
22
21
20
19
18
17
16
15
14
13

VCC1
Y
Y1
Y2
Y3
Y4
Y
Y6
Y7
Y
EN
CP

0

5

8

OE

D
D1
D2
D3
D4
D5
D6
D7
D

CLR

GND

2

0

3
4

P24-1
D24-1

5

SO24-2

6

&

7

E24-1

8
9
10

8

11
12

DIP/SOIC/CERPACK

TOP VIEW

IDT54/74FCT825 8-BIT REGISTER

24

V
23
22
21
20
19
18
17
16
15
14
13

OE

Y

Y

Y

Y

Y

Y

Y

Y

EN

CP

CC

0
1
2
3
4
5
6
7

OE
OE

CLR
GND

1

1

2

2

3

D

0

4
5
6
7
8
9
10

P24-1
D24-1
E24-1

SO24-2

D

1

D

2

D

3

D

4

D

5

D

6

D

7

11
12

DIP/SOIC/CERPACK

TOP VIEW

&

3

INDEX

INDEX

D2
D
D4

NC

D
D6
D7

NC

CC

1

NC

NC

V

CP

Y0

262728

1817161514

EN

Y1

25
24
23
22
21
20
19

8

Y

Y2
Y3
Y4
NC
Y
Y6
Y7

9

D

D

CP CLR

QY

EN

9

CP
EN

5

CLR

OE

D0

OE

D1

32

4
5
6

3

7
8
9

5

L28-1

10
11

1213

D8

CLR

GND

LCC

TOP VIEW

CC

OE2

D0

OE1

NC

32

D

1

5

2

6

D

7

D

3

8
9

D

4

D

5

10
11

D

6

4

1

L28-1

1213

D7

CLR

GND

NC

V

CP

OE3

262728

1817161514

EN

Y0

25
24
23
22
21
20
19

7

Y

Y
Y
Y
NC
Y
Y
Y

8

D

1

CP

2

EN

3

D

CP CLR

QY

EN

CLR

4

OE
OE
OE

1
2
3

5
6

2608 cnv* 04

8

LCC

TOP VIEW

2608 cnv* 05

7.19 2

IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRODUCT SELECTOR GUIDE

Device

10-Bit 9-Bit 8-Bit

Non-inverting 54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
Inverting 54/74FCT824A/B/C

2608 tbl 01

PIN DESCRIPTION

Name I/O Description

DI I The D flip-flop data inputs.

CLR

CP I Clock Pulse for the Register; enters

YI , YI

EN

OE

I For both inverting and non-inverting

registers, when the clear input is LOW
and OE is LOW, the Q

I outputs are

LOW. When the clear input is HIGH,
data can be entered into the register.

data into the register on the LOW-to­HIGH transition.

O The register three-state outputs.

I Clock Enable. When the clock enable

is LOW, data on the D
transferred to the Q

I input is

I output on the

LOW-to-HIGH clock transition. When
the clock enable is HIGH, the Q
outputs do not change state,
regardless of the data or clock input
transitions.

I Output Control. When the OE input is

HIGH, the Y

I outputs are in the high

impedance state. When the OE input is
LOW, the TRUE register data is
present at the Y

I outputs.

2608 tbl 10

FUNCTION TABLE

(1)

IDT54/74FCT821/823/825

↑
↑

↑
↑
↑
↑

Internal/
Outputs

L

Z

H

Z

L

Z

L

L
NC
NCZNC

L

Z

H

H

Z

L

L

H

Inputs

OEOECLR

CLRENEN

H

H

H

H

H

H

H
H

NOTE: 2608 tbl 02

1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-HIGH
Transition, Z = High Impedance

L

L

L

H

L

H
H
H

L

H

L

H

FUNCTION TABLE

DI CP QI YI

L

L

L

H

X

X

X

X

X

X

H

X

X

H

X

X

L

L

L

H

L

L

L

H

(1)

IDT54/74FCT824

↑
↑

↑
↑
↑
↑

Internal/
Outputs

H

Z

L

Z

L

Z

L

L
NC
NCZNC

H

H

Z

L

Z

H

L

L

Inputs

OEOECLR

CLRENEN

H

I

NOTE:

1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-

H

H

H

H

H

H
H

HIGH Transition, Z = High Impedance

L

L

L

H

L

H
H
H

L

H

L

H

DI CP QI YI

L

L

L

H

X

X

X

X

X

X

H

X

X

H

X

X

L

L

L

H

L

L

L

H

Function

High Z

Clear

Hold

Load

Function

High Z

Clear

Hold

Load

2608 tbl 03

7.19 3

IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

CC

(1)

–0.5 to V

CC

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

Capacitance

V

COUT Output

Capacitance

NOTE: 2608 tbl 05

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 6 10 pF

VOUT = 0V 8 12 pF

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Military Unit

V

TERM

V

TERM

T

A

(2)

Terminal Voltage
with Respect to
GND

(3)

Terminal Voltage
with Respect to
GND

Operating

–0.5 to +7.0 –0.5 to +7.0 V

–0.5 to V

0 to +70 –55 to +125°C

Temperature

T

BIAS

Temperature

–55 to +125 –65 to +135°C

Under Bias

T

STG

Storage

–55 to +125 –65 to +150°C

Temperature

P
I

OUT

T

Power Dissipation 0.5 0.5 W
DC Output

120 120 mA

Current

NOTES: 2608 tbl 04

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V

2. Input and V

3. Outputs and I/O terminals only.

CC by +0.5V unless otherwise noted.

CC terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current VCC = Max. VI = VCC —— 5µA

VI = 2.7V — — 5

II L Input LOW Current VI = 0.5V — — –5

VI = GND — — –5

IOZH Off State (High Impedance) VCC = Max. VO = VCC ——10µA

Output Current VO = 2.7V — — 10

IOZL VO = 0.5V — — –10

VO = GND — — –10
VIK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.

(3)

, VO = GND –75 –120 — mA

VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V

VCC = Min. IOH = –300µAVHC VCC —
VIN = VIH or VIL IOH = –15mA MIL. 2.4 4.3 —

IOH = –24mA COM'L. 2.4 4.3 —
VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V

VCC = Min. IOL = 300µA — GND VLC
VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5

IOL = 48mA COM'L. — 0.3 0.5

NOTES: 2608 tbl 06

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

CC = 5.0V, +25°C ambient and maximum loading.

(2)

Max. Unit

(4)

(4)

(4)

(4)

(4)

7.19 4

IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC = 0.2V; VHC = VCC – 0.2V

Symbol Parameter Test Conditions

ICC

∆ICC
ICCD Dynamic Power Supply

Quiescent Power Supply Current VCC = Max.

V

IN ≥ VHC; V IN ≤ VLC

Quiescent Power Supply Current
TTL Inputs HIGH

VCC = Max.
V

IN = 3.4V

VCC = Max.

(4)

Current

Outputs Open

OE

= EN = GND

(3)

(1)

V

IN ≥ VHC

V

IN ≤ VLC

Min. Typ.

— 0.2 1.5 mA

— 0.5 2.0 mA
— 0.15 0.25 mA/

One Input Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open
f

CP = 10MHz

V

IN ≥ VHC

V

IN ≤ VLC

(FCT)

— 1.7 4.0 mA

50% Duty Cycle

OE

= EN = GND
One Bit Toggling
at f

i = 5MHz

V

IN = 3.4V

V

IN = GND

— 2.2 6.0

50% Duty Cycle
VCC = Max.
Outputs Open
f

CP = 10MHz

V

IN ≥ VHC

V

IN ≤ VLC

(FCT)

— 4.0 7.8

50% Duty Cycle

OE

= EN = GND
Eight Bits Toggling
at f

i = 2.5MHz

V

IN = 3.4V

V

IN = GND

— 6.2 16.8

50% Duty Cycle

NOTES: 2608 tbl 07

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

CC = Quiescent Current

I
∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

H = Duty Cycle for TTL Inputs High

D

T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f
f

i = Input Frequency

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V); all other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

7.19 5

IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Test

Parameter Description Conditions

tPLH
tPHL

Propagation Delay
CP to Y

I (

OE

= LOW)

CL = 50pF

R

L = 500Ω

CL = 300pF

RL = 500Ω

tSU Set-up Time HIGH or LOW

D

i to CP

CL = 50pF

L = 500Ω

R

tH Hold Time HIGH or LOW

D

I to CP

tSU Set-up Time HIGH or LOW

EN

to CP

tH Hold Time HIGH or LOW

EN

to CP

tPHL Propagation Delay,

Y

I

tREM Recovery Time

CLR

to

CLR

to CP 6.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns

tW CP Pulse Width

HIGH or LOW

tW

CLR

Pulse Width

LOW

tPZH
tPZL

Output Enable Time OE

I

to Y

CL = 50pF

L = 500Ω

R

CL = 300pF

RL = 500Ω
tPHZ
tPLZ

Output Disable Time
to Y

I

OE

CL = 5pF

RL = 500Ω

CL = 50pF

L = 500Ω

R

IDT54/74FCT821A/

823A/824A/825A

Com'l. Mil. Com'l. Mil. Com'l. Mil.

Min.

(2)

Max. Min.

(1)

(2)

Max. Min.

— 10.0 — 11.5 — 7.5 — 8.5 — 6.0 — 7.0 ns

(3)

— 20.0 — 20.0 — 15.0 — 16.0 — 12.5 — 13.5

4.0 — 4.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns

4.0 — 4.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

2.0 — 2.0 — 0 — 0 — 0 — 0 — ns

— 14.0 — 15.0 — 9.0 — 9.5 — 8.0 — 8.5 ns

7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns

6.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns

— 12.0 — 13.0 — 8.0 — 9.0 — 7.0 — 8.0 ns

(3)

— 23.0 — 25.0 — 15.0 — 16.0 — 12.5 — 13.5

(3)

— 7.0 — 8.0 — 6.5 — 7.0 — 6.2 — 6.2 ns

— 8.0 — 9.0 — 7.5 — 8.0 — 6.5 — 6.5

IDT54/74FCT821B/

823B/824B/825B

(2)

Max. Min.

(2)

Max. Min.

IDT54/74FCT821C/

823C/824C/825C

(2)

Max. Min.

(2)

Max.

Unit

NOTES: 2608 tbl* 08

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. This parameter is guaranteed but not tested.

7.19 6

IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

VCC

500Ω

Pulse

Generator

VIN

D.U.T.

RT

VOUT

50pF

CL

500Ω

7.0V

SWITCH POSITION

Test Switch

Open Drain

Disable Low Closed

Enable Low

All Other Tests Open

DEFINITIONS: 2608 tbl 09

CL = Load capacitance: includes jig and probe capacitance.

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLOCK ENABLE

CLEAR

ETC.

t

tSU

SU

t

REM

t

t

H

H

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

LOW-HIGH-LOW

HIGH-LOW-HIGH

PULSE

PULSE

1.5V

t

W

1.5V

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

t

PLH

PLH

t

t

PHL

PHL

3V

1.5V
0V

V

OH

1.5V
V

OL

3V

1.5V
0V

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

t

PHZ

t

PLZ

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

t

PZL

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

NOTES 2608 drw 01

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z
t

R ≤ 2.5ns.

O ≤ 50Ω; tF ≤ 2.5ns;

0.3V

0.3V

1.5V
0V

3.5V

V

OL

V

OH

0V

7.19 7

IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
2523 cnv* 11

XX

Temp. Range

FCTIDT

XXXX

Device TypeXPackage

X

Process

Blank
B

P
D
E
L
SO

821A
821B
821C
823A
823B
823C
824A
824B
824C
825A
825B
825C

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

10-Bit Non-Inverting Register
Fast 10-Bit Non-Inverting Register
Super Fast 10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
Super Fast 9-Bit Non-Inverting Register
9-Bit Inverting Register
Fast 9-Bit Inverting Register
Super Fast 9-Bit Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
Super Fast 8-Bit Non-Inverting Register

°

C to +125°C

–55

°

C to +70°C

0

2608 cnv* 11

7.19 8