Integrated Device Technology Inc. IDT54FCT240, IDT54FCT240A, IDT54FCT240C, IDT54FCT241, IDT54FCT241A User Manual
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查询IDT54FCT2373AT供应商
FAST CMOS OCTAL
TRANSPARENT
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT373T/FCT533T/FCT573T:
– Std., A, C and D speed grades
– High drive outputs (-15mA I
– Power off disable outputs permit “live insertion”
• Features for FCT2373T/FCT2573T:
– Std., A and C speed grades
– Resistor output (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
LATCHES
OH, 48mA IOL)
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT
IDT54/74FCT533T/AT/CT
IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
– Reduced system switching noise
DESCRIPTION:
The FCT373T/FCT2373T, FCT533T and FCT573T/
FCT2573T are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches
have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high- impedance state.
The FCT2373T and FCT2573T have balanced drive outputs with current limiting resistors. This offers low ground
bounce, minimal undershoot and controlled output fall timesreducing the need for external series terminating resistors.
The FCT2xxxT parts are plug-in replacements for FCTxxxT
parts.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T
D0
D
LE
OE
D1
D
O
G
O
0
D2
D
O
G
O
1
D3
D
O
G
O
2
D4
D
O
G
O
3
D5
D
O
G
O
4
D6
D
O
G
O
5
D7
D
O
G
O
6
O
G
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T
D0
D
LE
D1
D
O
G
D2
D
O
G
D3
D
O
G
D4
D
O
G
D5
D
O
G
D6
D
O
G
D7
D
O
G
O
G
O
7
2564 cnv* 01
OE
O
0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2564 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995
1995 Integrated Device Technology, Inc. 6.12 DSC-4216/6
1
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT373/2373T
OE
O
D
D
O
O
D
D
O
GND
1
2
0
3
0
4
1
5
1
2
6
2
7
3
8
3
9
10 11
DIP/SOIC/SSOP/QSOP/CERPACK
IDT54/74FCT573/2573T
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
DIP/SOIC/SSOP/QSOP/CERPACK
2
3
4
5
6
7
8
9
10 11
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
TOP VIEW
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
TOP VIEW
20
19
18
17
16
15
14
13
12
20
19
18
17
16
15
14
13
12
V
O
D
D
O
O
D
D
O
LE
VCC1
O
O1
O2
O3
O4
O
O6
O7
LE
CC
7
7
6
6
5
5
4
4
2564 cnv* 03
0
5
INDEX
INDEX
D0
O0
VCC
OE
O7
3 2 20 19
D
O
O
D
D
4
1
5
1
6
2
7
2
8
3
1
L20-2
18
17
16
15
14
D
7
D
6
O
6
O
5
D
5
9 10111213
4
D4
LE
O
O3
2564 cnv* 04
GND
LCC
TOP VIEW
D2
D3
D4
D5
D6
D0
D1
3 2 20 19
4
1
5
6
L20-2
7
8
OE
VCC
O0
18
17
16
15
14
O1
O2
O3
O4
O5
9 10111213
GND
LE
7
O
O6
2564 cnv* 062564 cnv* 05
D7
LCC
TOP VIEW
IDT54/74FCT533
OE
O
D
D
O
O
D
D
O
GND
1
0
2
3
0
4
1
1
2
2
3
3
5
6
7
8
9
P20-1
D20-1
SO20-2
&
E20-1
10 11
DIP/SOIC/CERPACK
TOP VIEW
20
19
18
17
16
15
14
13
12
V
O
D
D
O
O
D
D
O
LE
CC
7
6
5
4
INDEX
D0
7
3 2 20 19
D1 D7
6
5
O1
O2
D2
D3
4
2564 cnv* 07 2564 cnv* 08
4
5
6
7
8
9 10111213
O3
O0
1
L20-2
OE
LE
CC
V
4
O
O7
18
17
16
15
14
D4
D
O6
O5
D5
6
GND
LCC
TOP VIEW
6.12 2
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (533)
(1)
Inputs Outputs
DN LE
OE
OE
O
N
O
HHLL
LHLH
XXHZ
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2564 tbl 01
DEFINITION OF FUNCTIONAL TERMS
Pin Names Description
DN Data Inputs
LE Latch Enable Input (Active HIGH)
OE
ON 3-State Outputs
O
N Complementary 3-State Outputs
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Commercial Military Unit
(2)
VTERM
(3)
VTERM
TA Operating
TBIAS Temperature
TSTG Storage
PT Power Dissipation 0.5 0.5 W
IOUT DC Output
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC by +0.5V unless otherwise noted.
2. Input and V
3. Outputs and I/O terminals only.
Output Enable Input (Active LOW)
Terminal Voltage
–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND
Terminal Voltage
with Respect to
GND
–0.5 to
V
CC +0.5
0 to +70 –55 to +125 °C
Temperature
–55 to +125 –65 to +135 °C
Under Bias
–55 to +125 –65 to +150 °C
Temperature
–60 to +120 –60 to +120 mA
Current
CC terminals only.
(1)
–0.5 to
VCC +0.5
2564 tbll 03
V
2564 lnk 04
FUNCTION TABLE (373 and 573)
(1)
Inputs Outputs
DN LE
OE
OE
ON
HHLH
LHLL
XXHZ
NOTE: 2564 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
CIN Input
Capacitance
COUT Output
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 6 10 pF
VOUT = 0V 8 12 pF
2564 lnk 05
6.12 3
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