Integrated Device Technology Inc. IDT54FCT240, IDT54FCT240A, IDT54FCT240C, IDT54FCT241, IDT54FCT241A User Manual

查询IDT54FCT2373AT供应商

FAST CMOS OCTAL
TRANSPARENT

Integrated Device Technology, Inc.

FEATURES:

• Common features:

– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility

– VOH = 3.3V (typ.)

– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation

Enhanced versions
– Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK

and LCC packages

• Features for FCT373T/FCT533T/FCT573T:

– Std., A, C and D speed grades
– High drive outputs (-15mA I
– Power off disable outputs permit “live insertion”

• Features for FCT2373T/FCT2573T:

– Std., A and C speed grades
– Resistor output (-15mA IOH, 12mA IOL Com.)

(-12mA IOH, 12mA IOL Mil.)

LATCHES

OH, 48mA IOL)

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT

IDT54/74FCT533T/AT/CT

IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT

– Reduced system switching noise

DESCRIPTION:

The FCT373T/FCT2373T, FCT533T and FCT573T/
FCT2573T are octal transparent latches built using an ad­vanced dual metal CMOS technology. These octal latches
have 3-state outputs and are intended for bus oriented appli­cations. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH, the

bus output is in the high- impedance state.

The FCT2373T and FCT2573T have balanced drive out­puts with current limiting resistors. This offers low ground
bounce, minimal undershoot and controlled output fall times­reducing the need for external series terminating resistors.
The FCT2xxxT parts are plug-in replacements for FCTxxxT
parts.

FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T

D0

D

LE

OE

D1

D

O

G

O

0

D2

D

O

G

O

1

D3

D

O

G

O

2

D4

D

O

G

O

3

D5

D

O

G

O

4

D6

D

O

G

O

5

D7

D

O

G

O

6

O

G

FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T

D0

D

LE

D1

D

O

G

D2

D

O

G

D3

D

O

G

D4

D

O

G

D5

D

O

G

D6

D

O

G

D7

D

O

G

O

G

O

7

2564 cnv* 01

OE

O

0

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

O

1

O

2

O

3

O

4

O

5

O

6

O

7

2564 cnv* 02

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc. 6.12 DSC-4216/6

1

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

IDT54/74FCT373/2373T

OE

O
D

D

O
O

D

D

O

GND

1
2

0

3

0

4

1

5

1
2

6

2

7

3

8

3

9
10 11

DIP/SOIC/SSOP/QSOP/CERPACK

IDT54/74FCT573/2573T

OE

D0
D1

D2
D3
D4
D5
D6
D7

GND

DIP/SOIC/SSOP/QSOP/CERPACK

2
3
4

5
6
7
8
9
10 11

P20-1

D20-1
SO20-2
SO20-7
SO20-8

&

E20-1

TOP VIEW

P20-1

D20-1
SO20-2
SO20-7
SO20-8

&

E20-1

TOP VIEW

20
19
18
17
16
15
14
13
12

20
19
18
17
16
15
14
13
12

V
O
D
D
O
O
D
D

O
LE

VCC1
O

O1
O2
O3
O4

O
O6

O7
LE

CC

7
7
6
6
5
5
4

4

2564 cnv* 03

0

5

INDEX

INDEX

D0

O0

VCC

OE

O7

3 2 20 19

D
O
O
D
D

4

1

5

1

6

2

7

2

8

3

1

L20-2

18
17
16
15
14

D

7

D

6

O

6

O

5

D

5

9 10111213

4

D4

LE

O

O3

2564 cnv* 04

GND

LCC

TOP VIEW

D2
D3
D4
D5
D6

D0

D1

3 2 20 19

4

1

5
6

L20-2
7
8

OE

VCC

O0

18
17

16
15
14

O1
O2
O3
O4
O5

9 10111213

GND

LE

7

O

O6

2564 cnv* 062564 cnv* 05

D7

LCC

TOP VIEW

IDT54/74FCT533

OE

O
D
D
O
O
D
D
O

GND

1

0

2
3

0

4

1
1
2
2
3
3

5
6
7
8
9

P20-1
D20-1

SO20-2

&

E20-1

10 11

DIP/SOIC/CERPACK

TOP VIEW

20
19
18
17
16
15
14
13
12

V
O
D
D
O
O
D
D
O
LE

CC

7
6

5
4

INDEX

D0

7

3 2 20 19

D1 D7

6
5

O1
O2
D2
D3

4

2564 cnv* 07 2564 cnv* 08

4
5
6
7
8

9 10111213

O3

O0

1

L20-2

OE

LE

CC

V

4

O

O7

18
17
16
15
14

D4

D
O6

O5
D5

6

GND

LCC

TOP VIEW

6.12 2

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE (533)

(1)

Inputs Outputs

DN LE

OE

OE

O

N

O

HHLL

LHLH

XXHZ

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance

2564 tbl 01

DEFINITION OF FUNCTIONAL TERMS

Pin Names Description

DN Data Inputs

LE Latch Enable Input (Active HIGH)

OE

ON 3-State Outputs

O

N Complementary 3-State Outputs

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Military Unit

(2)

VTERM

(3)

VTERM

TA Operating

TBIAS Temperature

TSTG Storage

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V

CC by +0.5V unless otherwise noted.

2. Input and V

3. Outputs and I/O terminals only.

Output Enable Input (Active LOW)

Terminal Voltage

–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

Terminal Voltage
with Respect to
GND

–0.5 to

V

CC +0.5

0 to +70 –55 to +125 °C

Temperature

–55 to +125 –65 to +135 °C
Under Bias

–55 to +125 –65 to +150 °C
Temperature

–60 to +120 –60 to +120 mA
Current

CC terminals only.

(1)

–0.5 to

VCC +0.5

2564 tbll 03

V

2564 lnk 04

FUNCTION TABLE (373 and 573)

(1)

Inputs Outputs

DN LE

OE

OE

ON

HHLH

LHLL

XXHZ

NOTE: 2564 tbl 02

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

Capacitance

COUT Output

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 6 10 pF

VOUT = 0V 8 12 pF

2564 lnk 05

6.12 3

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current
II L Input LOW Current

(4)

(4)

VI = 0.5V — — ±1

VCC = Max. VI = 2.7V — — ±1 µA

IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA

(4)

(4)

VO = 0.5V — — ±1

VCC = Max., VI = VCC (Max.) — — ±1 µA

IOZL (3-State Output pins)
II Input HIGH Current
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis — — 200 — mV
ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA

(2)

Max. Unit

2564 lnk 06

OUTPUT DRIVE CHARACTERISTICS FOR FCT373T/533T/573T

Symbol Parameter Test Conditions

V

OH

Output HIGH Voltage VCC = Min.

IN

= V

IH

V

or V

IOH = –6mA MIL.

IL

OH

= –8mA COM'L.

I
IOH = –12mA MIL.

OH

= –15mA COM'L.

I

V

I
I

OL

OS
OFF

Output LOW Voltage VCC = Min.

IN

= V

IH

or V

V

IL

Short Circuit Current VCC = Max., VO = GND
Input/Output Power Off Leakage

(5)

VCC = 0V, V

IN

or V

O

I

OL

= 32mA MIL.

OL

= 48mA COM'L.

I

(3)

≤ 4.5V — —

(1)

Min. Typ.

2.4 3.3 — V

2.0 3.0 — V

— 0.3 0.5 V

–60 –120 –225 mA

(2)

Max. Unit

±

1

µ

A

2564 lnk 07

OUTPUT DRIVE CHARACTERISTICS FOR FCT2373T/2573T

Symbol Parameter Test Conditions

IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V
IODH Output HIGH Current VCC = 5V, VIN = VIH or V

IL,

VOH Output HIGH Voltage VCC = Min.

V

IN = VIH or VIL

VOL Output LOW Voltage VCC = Min.

V

IN = VIH or VIL

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. The test limit for this parameter is ±5µA at T

5. This parameter is guaranteed but not tested.

A = –55°C.

(1)

(3)

VOUT = 1.5V

(3)

IOH = –12mA MIL.
I

OH = –15mA COM'L.

Min. Typ.

16 48 — mA

–16 –48 — mA

2.4 3.3 — V

IOL = 12mA — 0.3 0.50 V

(2)

Max. Unit

2564 lnk 08

6.12 4

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

ICCD Dynamic Power Supply

(4)

Current

VCC = Max.

IN = 3.4V

V

(3)

VCC = Max.
Outputs Open

OE

= GND

(1)

VIN = VCC
VIN = GND

Min. Typ.

— 0.5 2.0 mA

FCTxxxT — 0.15 0.25 mA/

FCT2xxxT — 0.06 0.12
One Input Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max. VIN = VCC FCTxxxT — 1.5 3.5 mA
Outputs Open

VIN = GND FCT2xxxT — 0.6 2.2
fi = 10MHz
50% Duty Cycle

OE

= GND

LE = VCC

VIN = 3.4

IN = GND

V

FCTxxxT — 1.8 4.5

FCT2xxxT 0.9 3.2
One Bit Toggling
VCC = Max. VIN = VCC FCTxxxT — 3.0 6.0

Outputs Open

VIN = GND FCT2xxxT — 1.2 3.4
fi = 2.5MHz
50% Duty Cycle

OE

= GND

LE = VCC

VIN = 3.4

IN = GND

V

FCTxxxT — 5.0 14.0

FCT2xxxT — 3.2 11.4

Eight Bits Toggling

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
I

CC = Quiescent Current

∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

D

H = Duty Cycle for TTL Inputs High

N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

N

i = Number of Inputs at fi

All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)
(5)

(5)

(5)

2564 tbl 09

6.12 5

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT373T/2373T/573T/2573T FCT373AT/2373AT/573AT/2573AT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions

t
t

t
t
t
t
t
t
t

t

t

PLH
PHL

PLH
PHL
PZH
PZL
PHZ
PLZ
SU

H

W

Propagation Delay
D

N

to O

N

CL = 50pF

R

L

= 500

Propagation Delay
LE to O

N

Output Enable Time 1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 ns

Output Disable Time 1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 ns

Set-up Time HIGH
or LOW, D

N

to LE
Hold Time HIGH
or LOW, D

N

to LE
LE Pulse Width HIGH 6.0 — 6.0 — 5.0 — 6.0 — ns

(1)

Ω

Min

(2)

.

Max.Min

(2)

.

Max.Min

(2)

.

Max.Min

(2)

.

Max

. Unit

1.5 8.0 1.5 8.5 1.5 5.2 1.5 5.6 ns

2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 ns

2.0 — 2.0 — 2.0 — 2.0 — ns

1.5 — 1.5 — 1.5 — 1.5 — ns

2564 tbl 10

FCT373CT/2373CT/573CT/2573CT FCT373DT/573DT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions

tPLH
tPHL

tPLH
tPHL
tPZH

Propagation Delay
D

N to ON

CL = 50pF

R

L = 500Ω

Propagation Delay
LE to O

N

Output Enable Time 1.5 5.5 1.5 6.3 1.5 4.8 — — ns

(1)

tPZL
tPHZ

Output Disable Time 1.5 5.0 1.5 5.9 1.5 4.0 — — ns

tPLZ
tSU Set-up Time HIGH

or LOW, D

N to LE

tH Hold Time HIGH

or LOW, D

tW LE Pulse Width HIGH

Symbol Parameter Conditions

tPLH
tPHL

tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ

Propagation Delay
D

N to ON

Propagation Delay
LE to
Output Enable
Time
Output Disable
Time

tSU Set-up Time HIGH

or LOW, D

tH Hold Time HIGH

or LOW, D

O

N

N to LE

N to LE

N to LE

(3)

CL = 50pF

R

L = 500Ω

FCT533T FCT533AT FCT533CT

Com'l. Mil. Com'l. Mil. Com'l. Mil.

(1)

(2)

Min.

Max. Min.

1.5 10.0 1.5 12.0 1.5 5.2 1.5 5.6 1.5 4.2 1.5 5.1 ns

2.0 13.0 2.0 14.0 2.0 8.5 2.0 9.8 2.0 5.5 2.0 8.0 ns

1.5 11.0 1.5 12.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns

1.5 7.0 1.5 8.5 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns

2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

tW LE Pulse Width HIGH 6.0 — 6.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns

NOTES: 2564 tbl 12

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. This parameter is guaranteed but not tested.

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

1.5 4.2 1.5 5.1 1.5 3.8 — — ns

2.0 5.5 2.0 8.0 2.0 4.0 — — ns

2.0 — 2.0 — 1.5 — — — ns

1.5 — 1.5 — 1.0 — — — ns

5.0 — 6.0 — 3.0 — — — ns

2564 tbl 11

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

6.12 6

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

Test

V

CC

7.0V

Open Drain
Disable Low

500

Pulse

Generator

Ω

V

V

IN

D.U.T.

T

R

OUT

50pF

C

L

500

Ω

2564 drw 09

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C
R

T = Termination resistance: should be equal to ZOUT of the Pulse

Enable Low

All Other Tests

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

t

t

REM

H

t

H

t

SU

t

SU

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

2564 drw 10

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

Switch

Closed

Open

2564 lnk 13

1.5V

t

W

1.5V

2564 drw 11

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

PLH

t

PLH

t

t

PHL

PHL

3V

1.5V
0V

OH

V

1.5V

V

OL

3V

1.5V
0V

2564 drw 12

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

t

PHZ

PLZ

t

F ≤ 2.5ns; tR ≤ 2.5ns

t

PZL

OUTPUT

NORMALLY

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

LOW

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

0.3V

0.3V

1.5V
0V

3.5V

V

OL

V

OH

0V

2564 drw 13

6.12 7

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX

Temp. Range

FCT

X

Family

XXXX
Device TypeXPackage

X

Process

Blank
B

P
D
SO
L
E
PY
Q

373T
573T
533T

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Shrink Small Outline Package
Quarter-size Small Outline Package

Non-Inverting Octal Transparent Latch
Non-Inverting Octal Transparent Latch

Inverting Octal Transparent Latch
373AT
573AT
533AT
373CT
573CT
533CT
373DT
573DT

Blank2High Drive

Balanced Drive

54
74

–55°C to +125°C
0°C to +70°C

2564 drw 14

6.12 8