IDT IDT54FCT16646T, IDT54FCT16646AT, IDT54FCT16646CT, IDT54FCT16646ET, IDT54FCT162646T User Manual

查询IDT54FCT162646ATE供应商

FAST CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS (3-STATE)

Integrated Device Technology, Inc.

FEATURES:

• Common features:

– 0.5 MICRON CMOS Technology

– High-speed, low-power CMOS replacement for

ABT functions

– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)

– ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

– Packages include 25 mil pitch SSOP, 19.6 mil pitch

TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%

• Features for FCT16646T/AT/CT/ET:

– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at

VCC = 5V, TA = 25°C

• Features for FCT162646T/AT/CT/ET:

– Balanced Output Drivers: ±24mA (commercial),

±16mA (military)

– Reduced system switching noise
– Typical V

VCC = 5V,TA = 25°C

DESCRIPTION:

The IDT54/74FCT16646T/AT/CT/ET and IDT54/

OLP (Output Ground Bounce) < 0.6V at

IDT54/74FCT16646T/AT/CT/ET

IDT54/74FCT162646T/AT/CT/ET

74FCT162646T/AT/CT/ET 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power devices are organized as two inde­pendent 8-bit bus transceivers with 3-state D-type registers.
The control circuitry is organized for multiplexed transmission
of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register fea­tures direction control (xDIR), over-riding Output Enable con­trol (xOE) and Select lines (xSAB and xSBA) to select either

real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data
bus, or both, can be stored in the internal registers by the
LOW-to-HIGH transitions at the appropriate clock pins. Flow­through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.

The IDT54/74FCT16646T/AT/CT/ET are ideally suited for
driving high-capacitance loads and low-impedance
backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used
as backplane drivers.

The IDT54/74FCT162646T/AT/CT/ET have balanced
output drive with current limiting resistors. This offers low
ground bounce, minimal undershoot, and controlled output
fall times–reducing the need for external series terminating
resistors. The IDT54/74FCT162646T/AT/CT/ET are plug-in
replacements for the IDT54/74FCT16646T/AT/CT/ET and
54/74ABT16646 for on-board bus interface applications.

FUNCTIONAL BLOCK DIAGRAM

1

OE

1DIR

1CLKBA

1SBA

1CLKAB

1SAB

B REG

D
C

A1

1

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

A REG

D

C

TO 7 OTHER CHANNELS

2540 drw 01

1B1

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996

1996 Integrated Device Technology, Inc. 5.13 DSC-4231/9

2

2

2

CLKBA

2

SBA

2

CLKAB

2

SAB

OE

DIR

2A1

A REG

D

C

TO 7 OTHER CHANNELS

B REG

D
C

2B1

2540 drw 02

1

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

1DIR

1CLKAB

1SAB

GND

1A1

A2

1

VCC

A3

1

A4

1
1A5

GND

A6

1

A7

1

A8

1
2A1

A2

2

2

A3

GND

2

A4

2A5
2A6

VCC

A7

2
2A8

GND

SAB

2

2

CLKAB

2DIR

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

26
27
28

SO56-1
SO56-2
SO56-3

48

43

56
55
54
53
52
51
50
49

47
46
45
44

42
41
40
39
38
37
36
35
34
33
3225
31
30
29

1

OE

1CLKBA
1SBA

GND

1B1

B2

1

VCC

1B3

B4

1

B5

1

GND

B6

1
1B7

B8

1

B1

2

B2

2
2B3

GND

2

B4

2

B5

2

B6

VCC

2B7

B8

2

GND

2SBA
2CLKBA
2OE

1DIR

1CLKAB

1SAB

GND

1A1

A2

1

VCC

A3

1

A4

1
1A5

GND

A6

1

A7

1

A8

1
2A1

A2

2

A3

2

GND

2

A4

2A5
2A6

VCC

2

A7

2A8

GND

SAB

2

CLKAB

2

2DIR

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

26
27
28

E56-1

56
55

54
53
52
51
50
49

48

47
46
45
44

43

42
41
40
39
38
37
36
35
34
33
3225
31
30
29

1OE
1CLKBA

1

SBA

GND

1

B1
B2

1

VCC

1B3

B4

1

1

B5

GND

B6

1
1B7

B8

1

B1

2

B2

2
2B3

GND

B4

2

2

B5

2

B6

VCC

2B7

2

B8

GND

2SBA
2CLKBA

2OE

SSOP/

TSSOP/TVSOP

TOP VIEW

2540 drw 03

CERPACK

2540 drw 04

TOP VIEW

5.13 2

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Pin Names Description

xAx Data Register A Inputs

Data Register B Outputs

xBx Data Register B Inputs

Data Register A Outputs

xCLKAB, xCLKBA Clock Pulse Inputs

xSAB, xSBA Output Data Source Select Inputs

xDIR, x

OE

FUNCTION TABLE

x

OE

OE

H
H

L
L
L
L

NOTES: 2540 tbl 03

1. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data

input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.

2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition

Output Enable Inputs

2540 tbl 01

(2)

Inputs Data I/O

xDIR xCLKAB xCLKBA xSAB xSBA xAx xBx

X
X

L
L
H
H

H or L

↑

X
X
X

H or L

H or L

↑

X

H or L

X
X

X
X

X
X
L
H

CAPACITANCE (TA = +25°C, f = 1.0MHz)

(1)

(1)

Conditions Typ. Max. Unit

VIN = 0V 3.5 6.0 pF

VOUT = 0V 3.5 8.0 pF

Operation or Function

Store A and B Data

Stored B Data to A Bus

Stored A Data to B Bus

Symbol Parameter

CIN Input

Capacitance

CI/O I/O

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

X

Input Input Isolation

X
L

Output Input Real Time B Data to A Bus
H
X

Input Output Real Time A Data to B Bus

X

2540 tbl 02

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Description Max. Unit

(2)

VTERM
VTERM

Terminal Voltage with Respect to
GND

(3)

Terminal Voltage with Respect to
GND

–0.5 to +7.0 V

–0.5 to

CC +0.5

V

V

TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. All device terminals except FCT162XXXT Output and I/O terminals.

3. Output and I/O terminals for FCT162XXXT.

2540 tbl 04

5.13 3

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

BUS

A

xDIR xOE

xCLKAB

xCLKBA xSAB xSBA

BUS

B

2540 drw 05

LL X X X L

REAL-TIME TRANSFER

BUS B TO A

BUS

A

xDIR xOE xCLKAB xCLKBA xSAB xSBA

H

L

X

REAL-TIME TRANSFER

BUS A TO B

BUS

B

2540 drw 06

XL X

BUS

A

xDIR xOE xCLKAB xCLKBA xSAB xSBA

HL
LLX

LX

XH XX

↑

↑

STORAGE FROM

A AND/OR B

BUS

B

2540 drw 07

XX

↑

X
X

X

↑

BUS

A

(1)

xDIR xOE xCLKAB xCLKBA xSAB xSBA

LL

H

NOTE:

1. Cannot transfer data to A bus and B bus simultaneously.

L

X

H or L

TRANSFER STORED

DATA TO A AND/OR B

H or L

X

BUS

B

2540 drw 08

X

H

H
X

5.13 4

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)

Input HIGH Current (I/O pins)

II L Input LOW Current (Input pins)

Input LOW Current (I/O pins)

(5)

VCC = Max. VI = VCC — — ±1 µA

(5)

(5)

VI = GND — — ±1

(5)

— — ±1

— — ±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)

(5)

VO = 0.5V — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND

(3)

–80 –140 –225 mA
VH Input Hysteresis — — 100 — mV
ICCL

Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
ICCH
ICCZ

(2)

Max. Unit

2540 lnk 05

OUTPUT DRIVE CHARACTERISTICS FOR FCT16646T

Symbol Parameter Test Conditions

IO Output Drive Current VCC = Max., VO = 2.5V

(3)

(1)

Min. Typ.

–50 —–180 mA

VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V

VIN = VIH or VIL IOH = –12mA MIL.

VOL Output LOW Voltage VCC = Min.

IN = VIH or VIL

V

IOFF Input/Output Power Off Leakage

(5)

VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA

OH = –15mA COM'L.

I
IOH = –24mA MIL.

OH = –32mA COM'L.

I
IOL = 48mA MIL.

OL = 64mA COM'L.

I

2.4 3.5 — V

2.0 3.0 — V

(4)

— 0.2 0.55 V

(2)

Max. Unit

2540 lnk 06

OUTPUT DRIVE CHARACTERISTICS FOR FCT162646T

Symbol Parameter Test Conditions

IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V
IODH Output HIGH Current VCC = 5V, VIN = VIH or V IL,
VOH Output HIGH Voltage VCC = Min.

V

IN = VIH or VIL

VOL Output LOW Voltage VCC = Min.

V

IN = VIH or VIL

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ± 5µA at T

A = –55°C.

(1)

(3)

VOUT = 1.5V

(3)

IOH = –16mA MIL.
I

OH = –24mA COM'L.

IOL = 16mA MIL.
I

OL = 24mA COM'L.

Min. Typ.

60 115 200 mA

–60 –115 –200 mA

2.4 3.3 — V

— 0.3 0.55 V

(2)

Max. Unit

2540 lnk 07

5.13 5

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

ICCD Dynamic Power Supply Current

(4)

VCC = Max.

IN = 3.4V

V
VCC = Max.

(3)

Outputs Open

(1)

IN = VCC

V
VIN = GND

Min. Typ.

— 0.5 1.5 mA

— 75 120 µA/

xDIR = xOE= GND
One Input Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open

CP = 10MHz (xCLKBA)

f

IN = VCC

V
VIN = GND

— 0.8 1.7 mA

50% Duty Cycle
xDIR = xOE = GND
One Bit Toggling

IN = 3.4V

V

IN = GND

V

— 1.3 3.2

fi = 5MHz
50% Duty Cycle

VCC = Max.
Outputs Open

CP = 10MHz (xCLKBA)

f

IN = VCC

V
VIN = GND

— 3.8 6.5

50% Duty Cycle
xDIR = xOE = GND
Sixteen Bits Toggling

IN = 3.4V

V

IN = GND

V

— 8.3 20.0

fi = 2.5MHz
50% Duty Cycle

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)

I

CC = Quiescent Current (ICCL, ICCH and ICCZ)

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D

T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

CP = Number of Clock Inputs at fCP

N
fi = Input Frequency
N

i = Number of Inputs at fi

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

2540 tbl 08

5.13 6

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT16646T/162646T FCT16646AT/162646AT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Condition

tPLH

Propagation Delay

tPHL

Bus to Bus

tPZH

Output Enable Time

tPZL

xDIR or xOE to Bus

tPHZ

Output Disable Time

tPLZ

xDIR or xOE to Bus

tPLH

Propagation Delay

tPHL

Clock to Bus

tPLH

Propagation Delay

tPHL

xSBA or xSAB to Bus

CL = 50pF

L = 500Ω

R

tSU Set-up Time HIGH or

LOW Bus to Clock

tH Hold Time HIGH or

LOW Bus to Clock

tW Clock Pulse Width

HIGH or LOW

tSK(o) Output Skew

(3)

(1)

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns

2.0 14.0 2.0 15.0 2.0 9.8 2.0 10.5 ns

2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns

2.0 9.0 2.0 10.0 2.0 6.3 2.0 7.0 ns

2.0 11.0 2.0 12.0 2.0 7.7 2.0 8.4 ns

4.0 — 4.5 — 2.0 — 2.0 — ns

2.0 — 2.0 — 1.5 — 1.5 — ns

6.0 — 6.0 — 5.0 — 5.0 — ns

— 0.5 — 0.5 — 0.5 — 0.5 ns

2540 tbl 09

FCT16646CT/162646CT FCT16646ET/162646ET

Com'l. Mil. Com'l. Mil.

Symbol Parameter Condition

tPLH

Propagation Delay

tPHL

Bus to Bus

tPZH

Output Enable Time

tPZL

xDIR or xOE to Bus

tPHZ

Output Disable Time

tPLZ

xDIR or xOE to Bus

tPLH

Propagation Delay

tPHL

Clock to Bus

tPLH

Propagation Delay

tPHL

xSBA or xSAB to Bus

CL = 50pF

L = 500Ω

R

tSU Set-up Time HIGH or

(1)

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

1.5 5.4 1.5 6.0 1.5 3.8 — — ns

1.5 7.8 1.5 8.9 1.5 4.8 — — ns

1.5 6.3 1.5 7.7 1.5 4.0 — — ns

1.5 5.7 1.5 6.3 1.5 3.8 — — ns

1.5 6.2 1.5 7.0 1.5 4.2 — — ns

2.0 — 2.0 — 2.0 — — — ns

LOW Bus to Clock

tH Hold Time HIGH or

1.5 — 1.5 — 0.0 — — — ns

LOW Bus to Clock

tW Clock Pulse Width

5.0 — 5.0 — 3.0

(4)

———ns

HIGH or LOW

tSK(o) Output Skew

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This limit is guaranteed but not tested.

(3)

— 0.5 — 0.5 — 0.5 — — ns

(2)

Max. Unit

2540 tbl10

5.13 7

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

Test Switch

V

CC

7.0V

Open Drain
Disable Low

500

Pulse

Generator

Ω

V

V

IN

D.U.T.

T

R

OUT

50pF

C

L

500

Ω

2556 drw 05

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Enable Low

All Other Tests

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

t

t

REM

H

t

H

t

SU

t

SU

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

3V

1.5V
0V

2556 drw 06

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

Closed

Open

2556 lnk 10

1.5V

t

W

1.5V

2556 drw 07

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

PLH

t

PLH

t

t

PHL

PHL

3V

1.5V
0V

OH

V

1.5V

V

OL

3V

1.5V
0V

2556 drw 08

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

t

PHZ

t

PLZ

t

PZL

OUTPUT

NORMALLY

OUTPUT

NORMALLY

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

LOW

HIGH

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

1.5V
0V

3.5V

0.3V

V

OL

V

0.3V

F ≤ 2.5ns; tR ≤ 2.5ns

OH

0V

2556 drw 09

5.13 8

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX FCT

Temperature

Device Type

Range

XXXX

X

Package

X

Process

Blank
B

PV
PA
PF
E

16646T
16646AT
16646CT
16646ET
162646T
162646AT
162646CT
162646ET

54
74

Commercial
MIL-STD-883, Class B

Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)

Non-Inverting 16-Bit Transceiver/Register

°C to +125°C

–55

°C to +85°C

–40

2540 drw 14

5.13 9