IDT IDT2305 Technical data

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IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK BUFFER
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2305-1 for Standard Drive
• IDT2305-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC package
IDT2305
DESCRIPTION:
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25µA, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
PLL
REF
1
Control
Logic
8
3
2
5
7
CLKOUT
CLK1
CLK2
CLK3
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2001 Integrated Device Technology, Inc. DSC 5174/4c
1
APRIL 2001
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
REF CLK2 CLK1
GND
1
2 3 4
SOIC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Max. Unit
VDD Supply Voltage Range –0.5 to +4.6 V
(2)
8
7 6 5
CLKOUT CLK4 V
DD
CLK3
VI V
I Input Voltage Range –0.5 to V
IIK (VI < 0) Input Clamp Current –5 0 mA IO (VO = 0 to VDD) Continuous Output Current ±50 mA VDD or GND Continuous Current ±100 mA T
A = 55°C Maximum Power Dissipation 0.7 W
(in still air) TSTG Storage Temperature Range –65 to +150 °C Operating Commercial Temperature 0 to +70 °C Temperature Range Operating Industrial Temperature -40 to +85 °C Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. The input and output negative-voltage ratings may be exceeded if the input and output
3. The maximum package power dissipation is calculated using a junction temperature
(3)
permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
clamp-current ratings are observed. of 150°C and a board trace length of 750 mils.
Input Voltage Range (REF) –0.5 to +5.5 V
(except REF) VDD+0.5
(1)
APPLICA TIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
PIN DESCRIPTION
Pin Name Pin Number Type Functional Description
(1)
REF
(2)
CLK2
(2)
CLK1 GND 4 Ground Ground
(2)
CLK3 VDD 6 PWR 3.3V Supply
(2)
CLK4 CLKOUT
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
(2)
1 IN Input reference clock, 5 Volt tolerant input 2 Ou t Output clock 3 Ou t Output clock
5 Ou t Output clock
7 Ou t Output clock 8 Ou t Output clock, internal feedback on this pin
2
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS - COMMERCIAL
Symbol Parameter Min. Max. Unit
VDD Supply Voltage 3 3.6 V
TA Operating Temperature (Ambient Temperature) 0 7 0 °C
CL Load Capacitance < 100MHz 30 pF
Load Capacitance 100MHz - 133MHz 10
C
IN Input Capacitance 7 pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol Parameter Conditions Min. Max. Unit
VIL Input LOW Voltage Level 0.8 V VIH Input HIGH Voltage Level 2 V
IIL Input LOW Current VIN = 0V 50 µA IIH Input HIGH Current VIN = VDD 100 µA
VOL Output LOW Voltage Standard Drive IOL = 8mA 0.4 V
High Drive IOL = 12mA (-1H)
VOH Output HIGH Voltage Standard Drive IOH = -8mA 2.4 V
High Drive IOH = -12mA (-1H)
IDD_PD Power Down Current REF = 0MHz 12 µA
IDD Supply Current Unloaded Outputs at 66.66MHz 32 mA
SWITCHING CHARACTERISTICS (2305-1) - COMMERCIAL
(1,2)
Symbol Parameter Conditions Min. Typ. Max. Unit
t
1 Output Frequency 10pF Load 1 0 13 3 MHz
30pF Load 1 0 10 0
Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 4 0 50 60 % t3 Rise Time Measured between 0.8V and 2V 2.5 ns t4 Fall Time Measured between 0.8V and 2V 2.5 ns t5 Output to Output Skew All outputs equally loaded 2 50 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 0 ±350 ps t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices 0 70 0 ps tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs 2 00 ps
t
LOCK PLL Lock Time Stable power supply, valid clock presented on REF pin 1 ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
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