Datasheet IDT2305 Datasheet (IDT)

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IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

3.3V ZERO DELAY
CLOCK BUFFER

FEA TURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• IDT2305-1 for Standard Drive

• IDT2305-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Power down mode

• Available in SOIC package

IDT2305

DESCRIPTION:

The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.

The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the

-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In

this mode, the device will draw less than 25µA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.

The IDT2305 is characterized for both Industrial and Commercial
operation.

FUNCTIONAL BLOCK DIAGRAM

PLL

REF

1

Control

Logic

8

3

2

5

7

CLKOUT

CLK1

CLK2

CLK3

CLK4

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2001 Integrated Device Technology, Inc. DSC 5174/4c

1

APRIL 2001

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

PIN CONFIGURATION

REF
CLK2
CLK1

GND

1

2
3
4

SOIC

TOP VIEW

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Max. Unit

VDD Supply Voltage Range –0.5 to +4.6 V

(2)

8

7
6
5

CLKOUT
CLK4
V

DD

CLK3

VI
V

I Input Voltage Range –0.5 to V

IIK (VI < 0) Input Clamp Current –5 0 mA
IO (VO = 0 to VDD) Continuous Output Current ±50 mA
VDD or GND Continuous Current ±100 mA
T

A = 55°C Maximum Power Dissipation 0.7 W

(in still air)
TSTG Storage Temperature Range –65 to +150 °C
Operating Commercial Temperature 0 to +70 °C
Temperature Range
Operating Industrial Temperature -40 to +85 °C
Temperature Range

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

2. The input and output negative-voltage ratings may be exceeded if the input and output

3. The maximum package power dissipation is calculated using a junction temperature

(3)

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

clamp-current ratings are observed.
of 150°C and a board trace length of 750 mils.

Input Voltage Range (REF) –0.5 to +5.5 V

(except REF) VDD+0.5

(1)

APPLICA TIONS:

• SDRAM

• Telecom

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

PIN DESCRIPTION

Pin Name Pin Number Type Functional Description

(1)

REF

(2)

CLK2

(2)

CLK1
GND 4 Ground Ground

(2)

CLK3
VDD 6 PWR 3.3V Supply

(2)

CLK4
CLKOUT

NOTES:

1. Weak pull down.

2. Weak pull down on all outputs.

(2)

1 IN Input reference clock, 5 Volt tolerant input
2 Ou t Output clock
3 Ou t Output clock

5 Ou t Output clock

7 Ou t Output clock
8 Ou t Output clock, internal feedback on this pin

2

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

OPERATING CONDITIONS - COMMERCIAL

Symbol Parameter Min. Max. Unit

VDD Supply Voltage 3 3.6 V

TA Operating Temperature (Ambient Temperature) 0 7 0 °C

CL Load Capacitance < 100MHz — 30 pF

Load Capacitance 100MHz - 133MHz — 10

C

IN Input Capacitance — 7 pF

DC ELECTRICAL CHARACTERISTICS - COMMERCIAL

Symbol Parameter Conditions Min. Max. Unit

VIL Input LOW Voltage Level — 0.8 V
VIH Input HIGH Voltage Level 2 — V

IIL Input LOW Current VIN = 0V — 50 µA
IIH Input HIGH Current VIN = VDD — 100 µA

VOL Output LOW Voltage Standard Drive IOL = 8mA — 0.4 V

High Drive IOL = 12mA (-1H)

VOH Output HIGH Voltage Standard Drive IOH = -8mA 2.4 — V

High Drive IOH = -12mA (-1H)

IDD_PD Power Down Current REF = 0MHz — 12 µA

IDD Supply Current Unloaded Outputs at 66.66MHz — 32 mA

SWITCHING CHARACTERISTICS (2305-1) - COMMERCIAL

(1,2)

Symbol Parameter Conditions Min. Typ. Max. Unit

t

1 Output Frequency 10pF Load 1 0 — 13 3 MHz

30pF Load 1 0 — 10 0

Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 4 0 50 60 %
t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns
t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns
t5 Output to Output Skew All outputs equally loaded — — 2 50 ps
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 70 0 ps
tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 2 00 ps

t

LOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms

NOTES:

1. REF Input has a threshold voltage of VDD/2.

2. All parameters specified with loaded outputs.

3

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS (2305-1H) - COMMERCIAL

(1,2)

Symbol Parameter Conditions Min. Typ. Max. Unit

1 Output Frequency 10pF Load 1 0 — 13 3 MHz

t

30pF Load 1 0 — 10 0

Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 4 0 50 60 %

Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 %

t3 Rise Time Measured between 0.8V and 2V — — 1. 5 ns
t4 Fall Time Measured between 0.8V and 2V — — 1. 5 ns
t5 Output to Output Skew All outputs equally loaded — — 250 ps
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 70 0 ps
t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit #2 1 — — V/ns
tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 200 ps

t

LOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms

NOTES:

1. REF Input has a threshold voltage of VDD/2.

2. All parameters specified with loaded outputs.

OPERATING CONDITIONS - INDUSTRIAL

Symbol Parameter Min. Max. Unit

VDD Supply Voltage 3 3.6 V

TA Operating Temperature (Ambient Temperature) -40 +85 °C

CL Load Capacitance < 100MHz — 30 pF

Load Capacitance 100MHz - 133MHz — 10

CIN Input Capacitance — 7 pF

DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL

Symbol Parameter Conditions Min. Max. Unit

VIL Input LOW Voltage Level — 0.8 V

VIH Input HIGH Voltage Level 2 — V

IIL Input LOW Current VIN = 0V — 50 µA
IIH Input HIGH Current VIN = VDD — 100 µA

VOL Output LOW Voltage Standard Drive IOL = 8mA — 0.4 V

High Drive IOL = 12mA (-1H)

VOH Output HIGH Voltage Standard Drive IOH = -8mA 2.4 — V

High Drive IOH = -12mA (-1H)

IDD_PD Power Down Current REF = 0MHz — 25 µA

IDD Supply Current Unloaded Outputs at 66.66MHz — 35 mA

4

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS (2305-1) - INDUSTRIAL

(1,2)

Symbol Parameter Conditions Min. Typ. Max. Unit

t1 Output Frequency 10pF Load 1 0 — 1 33 MHz

30pF Load 1 0 — 10 0
Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 4 0 50 60 %

t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns
t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns
t5 Output to Output Skew All outputs equally loaded — — 2 50 ps
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 70 0 ps
tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 2 00 ps

t

LOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms

NOTES:

1. REF Input has a threshold voltage of V

2. All parameters specified with loaded outputs.

DD/2.

SWITCHING CHARACTERISTICS (2305-1H) - INDUSTRIAL

(1,2)

Symbol Parameter Conditions Min. Typ. Max. Unit

1 Output Frequency 10pF Load 1 0 — 13 3 MHz

t

30pF Load 1 0 — 10 0

Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 4 0 50 60 %

Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 %

t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns
t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns
t5 Output to Output Skew All outputs equally loaded — — 2 50 ps
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 70 0 ps
t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit #2 1 — — V/ns
tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 2 00 ps

tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms

NOTES:

1. REF Input has a threshold voltage of VDD/2.

2. All parameters specified with loaded outputs.

5

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

ZERO DELA Y AND SKEW CONTROL

All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative

loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.

For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive

load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.

REF TO CLKA/CLKB RELA Y vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS

1500

1000

500

0

-30 -25 -20

-500

REF to CLKA/CLKB Delay (ps)

-100 0

-150 0

OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)

-15

-10

-5

05

10 15 20 25

30

6

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

SWITCHING WAVEFORMS

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Output

t2

1.4V

1.4V

Duty Cycle Timing

0.8V

t3

2V

All Outputs Rise/Fall Time

2V

t1

0.8V

1.4V

t4

3.3V
0V

Output

Output

REF

Output

CLKOUT

Device 1

1.4V

1.4V

t5

Output to Output Skew

VDD/2

VDD/2

t6

Input to Output Propagation Delay

V

DD/2

TEST CIRCUITS

VDD

0.1

0.1

µF

µF

OUTPUTS

DD

V

GND GND

CLKOUT

CLOAD

0.1

0.1

CLKOUT

Device 2

µF

µF

t7

VDD

V

GND

Device to Device Skew

OUTPUTS

DD

GND

V

DD/2

1KΩ

1KΩ

CLKOUT

10pF

Test Circuit 1 (all Parameters Except t8)

Test Circuit 2 (t8, Output Slew Rate On -1H Devices)

7

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

TYPICAL DUTY CYCLE

(for 30pf loads over frequency - 3.3V, 25C)

60
58
56

)

54

%

(
e

52

l
c
y

C

50

y

t
u

D

48
46
44
42
40

3

3.1

(for 30pf loads over temperature - 3.3V)

60

58

56

)

54

%

(
e

l
c

52

y
C
y

50

t
u

D

48
46
44
42
40

20

40

Duty C yc le vs V

3.2

Duty Cycle vs Frequency

60

Frequency (MHz)

I

DD vs Number of Loaded Outputs

140

(for 30pf loads over frequency - 3.3V, 25C)

DD

3.4

3.3

VDD (V)

80 100 120 140

(1)

AND IDD TRENDS

33MHz

66MHz
100MHz

3.5 3.6

-40C
0C
25C
70C
85C

(2)

FOR IDT2305-1

(for 10pF loads over frequency - 3.3V, 25C)

60

58

56

)

54

%

(
e

52

l
c
y

C

50

y

t
u

D

48
46
44
42
40

3

3.1

3.2

Duty Cycle vs F requ en cy

(for 10pF loads over tem perature - 3.3V)

60
58
56

)

54

%

(
e

l
c

52

y
C
y

50

t
u

D

48
46

44

42
40

20

40

60

Frequency (M H z )

I

DD vs Number of Loaded O utputs

140

(for 10pF loads over frequency - 3.3V, 25C)

Duty Cycle vs V

3.3

DD

3.4

VDD (V)

80 100 120 140

3.5 3.6

33MHz

66MHz
100MHz
133MHz

-40C
0C
25C
70C
85C

120

100

80

)
A

m

(

D

60

D

I

40

20

0

02

Number of Loaded Outputs

33MHz

66MHz
100MHz

4

6

8

120

100

80

)
A

m

(

D

60

D

I

40

20

0

02

Numb er of Loaded O utputs

4

6

NOTES:

1. Duty Cycle is taken from typical chip measured at 1.4V.

2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F);
V = Supply Voltage (V); f = Frequency (Hz))

8

33MHz

66MHz
100MHz

8

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

TYPICAL DUTY CYCLE

(for 30pf loads over frequency - 3.3V, 2 5C)

60
58
56

)

54

%

(
e

52

l
c
y

C

50

y

t
u

D

48
46
44
42
40

3

3.1

(for 30pf loads over temperature - 3.3V )

60

58

56

)

54

%

(
e

l
c

52

y
C
y

50

t
u

D

48
46
44
42
40

20

40

Duty Cycle vs V

3.2

Duty Cycle vs Fre quency

60

Frequency (M H z)

I

DD vs Number of Loaded Outputs

(for 30pf loads over frequency - 3.3V, 25C)

160

140

120

DD

3.4

3.3

VDD (V)

80 100 120 140

(1)

AND IDD TRENDS

33MHz

66MHz
100MHz

3.5 3.6

-40C
0C
25C
70C
85C

(2)

FOR IDT2305-1H

(for 10pF loads over frequency - 3.3V, 25C)

60
58
56

)

54

%

(
e

52

l
c
y

C

50

y

t
u

D

48

46
44
42
40

3

3.1

(for 10pF loads over temperature - 3.3V)

60

58
56

)

54

%

(
e

l
c

52

y
C
y

50

t
u
D

48
46
44
42
40

20

40

Duty C yc le vs V

3.2

Duty Cycle vs Frequency

60

Frequency (MHz )

I

DD vs Number of Loaded Outputs

(for 10pF loads over frequency - 3.3V, 25C)

160

140

120

DD

3.4

3.3

3.5 3.6

VDD (V)

80 100 120 140

33MHz

66MHz
100MHz
133MHz

-40C
0C
25C
70C
85C

100

80

)
A

m

(

D

60

D

I

40

20

0

02

Number of Loaded Outputs

33MHz

66MHz
100MHz

4

6

8

100

80

)
A

m

(

D

60

D

I

40

20

0

02

Number of Loaded Outputs

33MHz

66MHz
100MHz

4

6

8

NOTES:

1. Duty Cycle is taken from typical chip measured at 1.4V.

2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
f = Frequency (Hz))

9

IDT2305

3.3V ZERO DELAY CLOCK BUFFER

ORDERING INFORMATION

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT

IDT2305-1DC 8-Pin SOIC Commercial
IDT2305-1DCG 8-Pin SOIC Commercial
IDT2305-1DCI 8-Pin SOIC Industrial
IDT2305-1DCGI 8-Pin SOIC Industrial
IDT2305-1HDC 8-Pin SOIC Commercial
IDT2305-1HDCI 8-Pin SOIC Industrial

XXXXX XX X

Device Typ e

Package Process

Ordering Code Package Type Operating Range

Blank
I

DC
DCG

2305-1
2305-1H

Commercial (0
Industrial (-40

Small O utline
SOIC - Green

Zero Delay Clock Buffer
High Drive Output

o

C to +70oC)

o

C to +85oC)

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [e-mail]
Santa Clara, CA 95054 fax: [phone] [phone]

www.idt.com

10