• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2305-1 for Standard Drive
• IDT2305-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC package
IDT2305
DESCRIPTION:
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25µA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
PLL
REF
1
Control
Logic
8
3
2
5
7
CLKOUT
CLK1
CLK2
CLK3
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IIK (VI < 0)Input Clamp Current–5 0mA
IO (VO = 0 to VDD)Continuous Output Current±50mA
VDD or GNDContinuous Current±100mA
T
A = 55°CMaximum Power Dissipation0.7W
(in still air)
TSTGStorage Temperature Range–65 to +150°C
OperatingCommercial Temperature0 to +70°C
TemperatureRange
OperatingIndustrial Temperature-40 to +85°C
TemperatureRange
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. The input and output negative-voltage ratings may be exceeded if the input and output
3. The maximum package power dissipation is calculated using a junction temperature
(3)
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
clamp-current ratings are observed.
of 150°C and a board trace length of 750 mils.
Input Voltage Range (REF)–0.5 to +5.5V
(except REF) VDD+0.5
(1)
APPLICA TIONS:
•SDRAM
•Telecom
•Datacom
•PC Motherboards/Workstations
•Critical Path Delay Designs
PIN DESCRIPTION
Pin NamePin NumberTypeFunctional Description
(1)
REF
(2)
CLK2
(2)
CLK1
GND4Ground Ground
(2)
CLK3
VDD6PWR 3.3V Supply
(2)
CLK4
CLKOUT
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
(2)
1IN Input reference clock, 5 Volt tolerant input
2Ou t Output clock
3Ou t Output clock
5Ou t Output clock
7Ou t Output clock
8Ou t Output clock, internal feedback on this pin
2
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS - COMMERCIAL
SymbolParameterMin.Max.Unit
VDDSupply Voltage33.6V
TAOperating Temperature (Ambient Temperature)07 0°C
CLLoad Capacitance < 100MHz—30pF
Load Capacitance 100MHz - 133MHz—10
C
INInput Capacitance—7pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
SymbolParameterConditionsMin.Max.Unit
VILInput LOW Voltage Level—0.8V
VIHInput HIGH Voltage Level2—V
IILInput LOW CurrentVIN= 0V—50µA
IIHInput HIGH CurrentVIN= VDD—100µA
VOLOutput LOW VoltageStandard DriveIOL= 8mA—0.4V
High DriveIOL= 12mA (-1H)
VOHOutput HIGH VoltageStandard DriveIOH= -8mA2.4—V
High DriveIOH= -12mA (-1H)
IDD_PDPower Down CurrentREF = 0MHz—12µA
IDDSupply CurrentUnloaded Outputs at66.66MHz—32mA
SWITCHING CHARACTERISTICS (2305-1) - COMMERCIAL
(1,2)
SymbolParameterConditionsMin.Typ.Max.Unit
t
1Output Frequency10pF Load1 0—13 3MHz
30pF Load1 0—10 0
Duty Cycle = t2÷ t1Measured at 1.4V, FOUT = 66.66MHz4 05060%
t3Rise TimeMeasured between 0.8V and 2V——2.5ns
t4Fall TimeMeasured between 0.8V and 2V——2.5ns
t5Output to Output SkewAll outputs equally loaded——2 50ps
t6Delay, REF Rising Edge to CLKOUT Rising EdgeMeasured at VDD/2—0±350ps
t7Device-to-Device SkewMeasured at VDD/2 on the CLKOUT pins of devices—070 0ps
tJCycle-to-Cycle Jitter, pk - pkMeasured at 66.66MHz, loaded outputs——2 00ps
t
LOCKPLL Lock TimeStable power supply, valid clock presented on REF pin——1ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
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