• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT2308A-1 1x
– IDT2308A-2 1x, 2x
– IDT2308A-3 2x, 4x
– IDT2308A-4 2x
– IDT2308A-1H and -2H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
IDT2308A
DESCRIPTION:
The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308A has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308A enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT2308A is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308A is characterized for both Industrial and Commercial opera-
tion.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
16
FBK
REF
S2
S1
2
1
8
9
PLL
Control
Logic
(-2, -3)
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
2
6
CLKB1
7
CLKB2
10
CLKB3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1Input Reference Clock, 5 Volt Tolerant Input
2Clock Output for Bank A
3Clock Output for Bank A
6Clock Output for Bank B
7Clock Output for Bank B
8Select Input, Bit 2
9Select Input, Bit 1
1 0Clock Output for Bank B
1 1Clock Output for Bank B
1 4Clock Output for Bank A
1 5Clock Output for Bank A
161
15
14
13
12
11
10
ABSOLUTE MAXIMUM RATINGS
SymbolRatingMax.Unit
VDDSupply Voltage Range–0.5 to +4.6V
(2)
FBK
VI
V
IInput Voltage Range–0.5 toV
CLKA4
CLKA3
DD
V
GND
CLKB4
CLKB3
9
S1
IIK (VI < 0)Input Clamp Current–5 0mA
IOContinuous Output Current±50mA
(VO = 0 to VDD)
VDD or GNDContinuous Current±100mA
TA = 55°CMaximum Power Dissipation0.7W
(in still air)
TSTGStorage Temperature Range–65 to +150°C
OperatingCommercial Temperature0 to +70°C
TemperatureRange
OperatingIndustrial Temperature-40 to +85°C
TemperatureRange
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
2. The input and output negative-voltage ratings may be exceeded if the input and output
3. The maximum package power dissipation is calculated using a junction temperature
(3)
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DeviceFeedback FromBank A FrequencyBank B Frequency
IDT2308A-1Bank A or Bank BReference Reference
IDT2308A-1HBank A or Bank BReference Reference
IDT2308A-2Bank AReference Reference/2
IDT2308A-2Bank B2 x Reference Reference
IDT2308A-2HBank AReference Reference/2
IDT2308A-2HBank B2 x Reference Reference
IDT2308A-3Bank A2 x Reference Reference or Reference
IDT2308A-3Bank B4 x Reference 2 x Reference
IDT2308A-4Bank A or Bank B2 x Reference 2 x Reference
NOTE:
1. Output phase is indeterminant (0° or 180° from input clock).
(1)
ZERO DELA Y AND SKEW CONTROL
To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
3
Page 4
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS- COMMERCIAL
SymbolParameterTest ConditionsMin.Max.Unit
VDDSupply Voltage33.6V
TAOperating Temperature (Ambient Temperature)07 0°C
CLLoad Capacitance below 100MHz—3 0pF
Load Capacitance from 100MHz to 133MHz—1 5pF
CINInput Capacitance
NOTE:
1. Applies to both REF and FBK.
(1)
—7pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
SymbolParameterConditionsMin.Typ.
VILInput LOW Voltage Level——0.8V
VIHInput HIGH Voltage Level2——V
IILInput LOW CurrentVIN= 0V——50µA
IIHInput HIGH CurrentVIN= VDD——100µA
Duty Cycle = t
(-1, -2, -3, -4, -1H, -2H)30pF Load
Duty Cycle = t
(-1, -2, -3, -4, -1H, -2H)15pF Load
t3Rise Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 30pF Load——2.2ns
t3Rise Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 15pF Load——1.5ns
t3Rise Time (-1H, -2H)Measured between 0.8V and 2V, 30pF Load——1.5ns
t4Fall Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 30pF Load——2.2n s
t4Fall Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 15pF Load——1.5n s
t4Fall Time (-1H)Measured between 0.8V and 2V, 30pF Load——1.25ns
t5Output to Output Skew on same BankAll outputs equally loaded——20 0ps
(-1, -2, -3, -4)
Output to Output Skew (-1H, -2H)All outputs equally loaded——20 0p s
Output Bank A to Output Bank B (-1, -4, -2H)All outputs equally loaded——20 0p s
Output Bank A to Output Bank B Skew (-2, -3)All outputs equally loaded——400ps
t6Delay, REF Rising Edge to FBK Rising EdgeMeasured at VDD/2—0±25 0ps
t7Device to Device SkewMeasured at VDD/2 on the FBK pins of devices—070 0ps
t8Output Slew RateMeasured between 0.8V and 2V on -1H, -2H1——V/ns
tJCycle to Cycle JitterMeasured at 66.67 MHz, loaded outputs, 15pF Load——20 0
(-1, -2, -3, -4, -1H, -2H)15pF Load
t3Rise Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 30pF Load⎯⎯2.2ns
t3Rise Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 15pF Load⎯⎯1.5ns
t3Rise Time (-1H, -2H)Measured between 0.8V and 2V, 30pF Load⎯⎯1.5ns
t4Fall Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 30pF Load⎯⎯2.2ns
t4Fall Time (-1, -2, -3, -4)Measured between 0.8V and 2V, 15pF Load⎯⎯1.5ns
t4Fall Time (-1H)Measured between 0.8V and 2V, 30pF Load⎯⎯1.25ns
t5Output to Output Skew on same BankAll outputs equally loaded⎯⎯200ps
(-1, -2, -3, -4)
Output to Output Skew (-1H, -2H)All outputs equally loaded⎯⎯200ps
Output Bank A to Output Bank B (-1, -4, -2H)All outputs equally loaded⎯⎯200ps
Output Bank A to Output Bank B Skew (-2, -3)All outputs equally loaded⎯⎯400ps
t6Delay, REF Rising Edge to FBK Rising EdgeMeasured at VDD/2⎯0±250ps
t7Device to Device SkewMeasured at VDD/2 on the FBK pins of devices⎯0700ps
t8Output Slew RateMeasured between 0.8V and 2V on -1H, -2H1⎯⎯V/ns
tJCycle to Cycle JitterMeasured at 66.67 MHz, loaded outputs, 15pF Load⎯⎯200
(-1, -1H, -4)Measured at 66.67 MHz, loaded outputs, 30pF Load⎯⎯200ps
tJCycle to Cycle JitterMeasured at 66.67 MHz, loaded outputs, 30pF Load⎯⎯400ps
(-2, -2H, -3)Measured at 66.67 MHz, loaded outputs, 15pF Load⎯⎯400
tLOCKPLL Lock TimeStable Power Supply, valid clocks presented⎯⎯1ms
2 ÷ t1Measured at 1.4V, FOUT = 50MHz455055%
device using Test Circuit 2
Measured at 133.3 MHz, loaded outputs, 15pF Load⎯⎯100
on REF and FBK pins
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IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
SWITCHING WAVEFORMS
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
t1
t2
Output
1.4V
0.8V
t3
Duty Cycle Timing
2V
2V
All Outputs Rise/Fall Time
Output
Output
1.4V
t5
1.4V1.4V
0.8V
t4
1.4V
3.3V
0V
Input
FBK
FBK,
Device 1
FBK,
Device 2
Output to Output Skew
VDD/2
VDD/2
t6
Input to Output Propagation Delay
V
DD/2
V
t7
DD/2
Device to Device Skew
8
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IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
TEST CIRCUITS
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
0.1µF
0.1µF
TEST CIRCUIT 1
VDD
DD
V
OUTPUTS
CLK
OUT
C
LOAD
GNDGND
Test Circuit for all Parameters Except t8
TEST CIRCUIT 2
0.1µF
VDD
OUTPUTS
1KΩ
1KΩ
DD
V
0.1µF
GND
GND
Test Circuit for t8, Output Slew Rate On -1H and -2H Devices