ICT PA7536J-15, PA7536JI-15, PA7536P-15, PA7536PI-15, PA7536S-15 Datasheet

1 04-02-052D

Commercial/Industrial

PA7536 PEEL Array™

Programmable Electrically Erasable Logic Array

Versatile Logic Array Architecture

- 12 I/Os, 14 inputs, 36 registers/latches

- Up to 36 logic cell output functions

- PLA structure with true product-term sharing

- Logic functions and registers can be I/O-buried

Ideal for Combinatorial, Synchronous and

Asynchronous Logic Applications

- Integration of multiple PLDs and random logic

- Buried counters, complex state-machines

- Comparators, decoders, multiplexers and

other wide-gate functions

High-Speed Commercial and Industrial Versions

- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f

MAX

)

- Industrial grade available for 4.5 to 5.5V V

CC

and

-40 to +85 °C temperatures

CMOS Electrically Erasable Technology

- Reprogrammable in 28-pin DIP, SOIC and PLCC
packages

Flexible Logic Cell

- Up to 3 output functions per logic cell

- D,T and JK registers with special features

- Independent or global clocks, resets, presets,

clock polarity and output enables

- Sum-of-products logic for output enables

Development and Programmer Support

- ICT WinPLACE Development Software

- Fitters for ABEL, CUPL and other software

- Programming support by popular third-party

programmer

General Description

The PA7536 is a m ember of the Pr ogramm able Electr icall y
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the arc hitectural flexibilit y and speed needed for
today’s programmable logic designs. The PA7536 offers
versatile logic ar ray architecture with 1 2 I/O pins, 14 input
pins and 36 registers/latches (12 buried logic cells, 12
Input registers/latc hes and 12 buried reg isters/latches). Its
logic array implem ents 50 sum-of-products logic functions
that share 64 product terms. The PA7536’s logic and I/O
cells (LCCs, IOCs) are extremely flexible offering up to
three output functions per cell (a tot al of 36 for all 12 logic
cells). Cells are co nfigurab le as D, T , and J K registers with

independent or global clocks, resets, presets, clock
polarity, and other special features, making the PA7536
suitable for a variety of combinatorial, synchronous and
asynchronous logic applications. The PA7536 offers pin
compatibility and super-set functionality to popular 28-pin
PLDs, such as the 26V 12. Thus, designs that exceed th e
architectures of such de vices can be expanded u pon. The
PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx)
and 83.3MHz (f

MAX

) and moderate power consumption
60mA (45mA typical). Packaging includes 28-pin DIP,
SOIC, and PLCC (see Figure 1). Development and
programming support for the PA7536 is provided by ICT
and popular third-party development tool manufacturers.

Figure 1. Pin Configuration

08-16-001A

DIP

I/CLK1 1

I

2

I

3

I

4

I

5

I

6

VCC

7

I

8

I

9

I

10

I

11

I

12

I/O24
I/O

23

I/O

22

GND

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I

13

I

14

I/CLK2

28

I/O

27

I/O

26

I/O

25

1

I/CLK1

2

I

3

I

4

I

5

I

6

I

7

VCC

8

I

9

I

10

I

11

I

12

I

24

I/O

23

I/O

22

I/O

21

GND

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

SOIC/TSSOP

13

I

14

I

28

I/CLK2

27

I/O

26

I/O

25

I/O

PLCC

25

I/O

24

I/O

23

I/O

22

I/O

21

GND

20

I/O

19

I/O

4I3I2I1

I/CLK128I/CLK227I/O26I/O

5

I

6

I

7

VCC

8

I

9

I

10

I

11

I

12I13I14I15

I/O16I/O17I/O18I/O

Figure 2. Block Diagram

Input
Cells
(INC)

12 Input Pins

2 Input/
Global Clock Pins

Global

Cells

2

12

I/O
Cells
(IOC)

Logic

Control

Cells

(LCC)

12

12

12

12

A
B
C
D

76 (38X2)
Array In pu ts
true and
complement

Buried
logic

2 sum terms
3 product terms
for Glob al Cells

12 Logic Control Cells
up to 3 output functions per cell
(36 total ou tp ut fu nc tion s po s s ible )

Logic functions
to I/O cells

12 I/O P ins

48 sum terms
(four per LC C)

Logic
Array

08-16-002A

PA7536

I
I
I
I
I

VCC

I

I
I
I

I/O
I/O
I/O
I/O
I/O
I/O
GND

I/CLK 2I/CLK 1

I
I

I/O
I/O

I/O

Global Cells

Input C ells

I/O C e lls

I I/O

I/O
I/O

Log ic Con t r o l Ce lls

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Commercial/Industrial

Inside the Logic Array

The heart of the P EEL™ Array architecture is based on a
logic array structur e s imilar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provi des interconnection and contr ol of
the cells. Depending on the PEEL™ Array selected, a
range of 38 to 62 inputs is availab le into the arra y from the
I/O cells, inputs cells and input/global-clock pins.

All inputs provide bo th true and c omplem ent signa ls, which
can be programm ed to any product term in the array. T he
number of product-terms among PEEL™ Arrays ranges
from 67 to 125. All product terms (with the exception of
certain ones fed to t he global cells) can b e programmably
connected to any of the s um- terms of the logic c ontrol cells
(four sum-terms per logic control cell). Product-terms and
sum-terms are also routed to the global cells for control
purposes. Figure 3 shows a detailed view of the logic
array structure.

From
IO Cells
(IOC,INC,
I/CLK )

From
Logic
Control
Cells
(LCC)

To
Global
Cells

38 Array Inputs

67 Product Terms

To
Logic Control
Cells
(LCC)

50 Sum Terms

PA7536 Logic Array

08-16-003A

Figure 3 PA7536 Logic Array
True Product-Term Sharing

The PEEL™ logic arra y provides several advantages over
common PLD logic arra ys. First, it allows for true pro duct­term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing

ensures that product-terms are used where they are
needed and not lef t unutilized or dupl icated. Secondl y, the
sum-of-products functions provided to the logic cells can
be used for clocks, resets, presets and output enables
instead of just simple product-term control.

The PEEL™ logic arra y can also implem ent logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product
terms to implement 16 exclusive-OR functions. The
PEEL™ logic array easily handles this in a single level
delay. Other PLDs/CPL Ds either run out of product-term s
or require expanders or additional logic levels that often
slow performance and skew timing.

Logic Control Cell (LCC)

Logic Control Cells (LCC) are us ed to allocate and control
the logic functions created i n the log ic arr a y. Each LCC has
four primary inputs and t hree outputs. The inputs to each
LCC are complete sum- of-product logic functions fr om the
array, which can b e used to implement com binatorial and
sequential logic functio ns, and to c ontr ol LCC regis ter s and
I/O cell output enables.

A
B
C
D

REG

D,T,J

K

R

P

Q

MUX

System Cloc k

Preset Reset

On/Off

RegType

From Glob al C ell

MUX

MUX

To

Array

To
I/O

Cell

From
Array

08-16-004A

Figure 4. Logic Control Cell Block Diagram

As shown in Figure 4, th e LCC is made up of three s ignal
routing multiplexers and a versatile register with
synchronous or asynchronous D, T, or JK registers
(clocked-SR register s, which are a subset of JK, are also
possible). See Figure 5. EEPROM memory cells are used
for programming the desired configuration. Four sum-of­product logic functions (SUM terms A, B, C and D) ar e fed
into each LCC from the logi c arra y. Each SUM term c an be
selectively used for multiple functions as listed below.

3 04-02-052D

Commercial/Industrial

Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D

D

R

P

Q

D Register

Q = D after clocked

Best for storage, simple counters,
shifters and state machines with
few hold (loop) conditions.

T

R

P

Q

T Register

Q toggles when T = 1
Q holds when T = 0

Best for wide binary counters (saves
product terms) and state machines
with many hold (loop) conditions.

JK Register

Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q = 1 when J/K = 1/0
Q = 0 when J/K = 0/1

Combines features of both D and T
registers.

J

R

P

Q

K

08-16-005A

Figure 5. LCC Register Types

SUM-A can serve as the D, T, or J in put of the register or a
combinatorial path. S UM-B can ser ve as th e K inp ut, or the
preset to the register , or a combinator ial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I /O cell, or an internal feedback
node. Note that the sums controlling clock s , res ets , pres ets
and output enables ar e co m plete sum -of- product f unctions,
not just product term s as with most other PLDs . This also
means that any inp ut or I/O pin can b e used as a cl ock or
other control function.

Several signals f rom the global cell are provided pr imarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows d ynamic switching of register type. T his
last feature is especially useful for saving product terms
when implementing loa dable counters and state m achines
by dynamicall y switching from D-type register s to load and
T-type registers to count (see Figure 11).

Multiple Outputs Per Logic Cell

An important feature of the logic c ontrol cell is its c apabilit y
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C com binatorial paths. T hus, one LCC output
can be registered, one output c an be com binator ial an d the

third, an output enable or an additional buried logic
function. The multi-function PEEL™ Array logic cells are
equivalent to two or three macrocells of other PLDs, which
have only one output per c ell. They also allow reg isters to
be truly buried from I/O pins without limiting them to input­only (see Figure 8 and Figure 9).

I/O C ell (IO C )

Input Cell (INC)

REG/
Latch

Q

MUX

Input

To

Array

Input Cell Clock

From Global Cell

MUX

From
Logic
Control
Cell

A,B,C

or
Q

MUX

MUX

1

0

D

I/O P in

MUX

To

Array

REG/
Latch

Q

Input Cell Clock

From Global Cell

Input

Input

08-16-006A

Figure 6. I/O Cell Block Diagram

IOC/INC Register

Q = D after rising edge of clock
holds until next rising edge

IOC /IN C L atc h

Q = L when clock is high
holds value when clock is low

LQ

D Q

08-16-007A

Figure 7. IOC Register Configurations