ICT PA7140F-20, PA7140F-25, PA7140FI-20, PA7140FI-25, PA7140J-20 Datasheet

Commercial/

Industrial

PA7140 PEELTM Array

Features	Programmable Electrically Erasable Logic Array

■Versatile Logic Array Architecture

-24 I/Os, 14 inputs, 60 registers/latches

-Up to 72 logic cell output functions

-PLA structure with true product-term sharing

-Logic functions and registers can be I/O-buried

■High-Speed Commercial and Industrial Versions

-As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX)

-Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85 °C temperatures Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications

-Integration of multiple PLDs and random logic

-Buried counters, complex state-machines

-Comparators, decoders, other wide-gate functions

General Description

The PA7140 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7140 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches). Its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells. Each group shares half (60) of the 120 product-terms available for logic cells.

■CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP,

44-pin PLCC, and TQFP packages

■Flexible Logic Cell

-Up to 3 output functions per logic cell

-D,T and JK registers with special features

-Independent or global clocks, resets, presets, clock polarity and output enables

-Sum-of-products logic for output enables

■Development and Programmer Support

-ICT PLACE Development Software

-Fitters for ABEL, CUPL and other software -Programming support for by ICT PDS-3 and popular

third-party programmers

The PA7140’s logic and I/O cells (LCCs, IOCs) are extremely flexible with up to three output functions per cell (a total of 72 for all 24 logic cells). Cells are configurable as D, T, and JK registers with independent or global clocks, resets, presets, clock polarity, and other features, making the PA7140 suitable for a variety of combinatorial, synchronous and asynchronous logic applications. The PA7140 supports speeds as fast as 13ns/20ns (tpdi/tpdx) and 66.6MHz (fMAX) at moderate power consumption 140mA (100mA typical). Packaging includes 40-pin DIP and 44-pin PLCC (see Figure 1). Development and programming support for the PA7140 is provided by ICT and popular thirdparty development tool manufacturers.

Figure 1: Pin Configuration

Figure 2. Block Diagram

TQFP	44 43 42 41 40 39 38 37 36 35 34
1	Pin 1	33
2		32
3		31
4		30
5		29
6		28
7		27
8		26
9		25
10		24
11		23
	12 13 14 15 16 17 18 19 20 21 22

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PA7140

Table 1. Absolute Maximum Ratings

This device has been designed and tested for the recommended operating conditions. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.

Symbol	Parameter	Conditions	Ratings	Unit
VCC	Supply Voltage	Relative to Ground	-0.5 to + 7.0	V
VI, VO	Voltage Applied to Any Pin	Relative to Ground1	-0.5 to VCC + 0.6	V
IO	Output Current	Per pin (IOL, IOH)	±25	mA
TST	Storage Temperature		-65 to + 150	°C
TLT	Lead Temperature	Soldering 10 seconds	+300	°C
Table 2. Operating Ranges

Symbol	Parameter		Conditions	Min	Max	Unit
VCC	Supply Voltage		Commercial	4.75	5.25	V
			Industrial	4.5	5.5
TA	Ambient Temperature		Commercial	0	+70	°C
			Industrial	-40	+85
TR	Clock Rise Time		See Note 2		20	ns
TF	Clock Fall Time		See Note 2		20	ns
TRVCC	VCC Rise Time		See Note 2		250	ms
Table 3. D.C. Electrical Characteristics over the recommended operating conditions

Symbol	Parameter	Conditions		Min	Max	Unit
VOH	Output HIGH Voltage - TTL	VCC = Min, IOH = -4.0mA		2.4		V
VOHC	Output HIGH Voltage - CMOS	VCC = Min, IOH = -10µA		VCC - 0.3		V
VOL	Output LOW Voltage - TTL	VCC = Min, IOL = 16mA			0.5	V
VOLC	Output LOW Voltage - CMOS	VCC = Min, IOL = -10µA			0.15	V
VIH	Input HIGH Level			2.0	VCC + 0.3	V
VIL	Input LOW Level			-0.3	0.8	V
IIL	Input Leakage Current	VCC = Max, GND ≤ VIN ≤ VCC			±10	µA
IOZ	Output Leakage Current	I/O = High-Z, GND ≤ VO ≤ VCC			±10	µA
ISC	Output Short Circuit Current4	VCC = 5V, VO = 0.5V, TA= 25°C		-30	-120	mA
		VIN = 0V or VCC3,11	-20		140
ICC11	VCC Current	f = 25MHz	-25	100 (typ.)18	140	mA
		All outputs disabled4
			I-25		150
CIN7	Input Capacitance5	TA = 25°C, V CC = 5.0V			6	pF
COUT7	Output Capacitance5	@ f = 1 MHz			12	pF

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