ICT PA7024JN-25, PA7024JN-20, PA7024JN-15, PA7024JI-20, PA7024JI-15 Datasheet

Commercial/PA7024

Industrial

PA7024 PEELTM Array

Programmable Electrically Erasable Logic Array

Features

■	CMOS Electrically Erasable Technology	■ High-Speed Commercial and Industrial Versions
	- Reprogrammable in 24-pin DIP, SOIC and	- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
	28-pin PLCC packages	- Industrial grade available for 4.5 to 5.5V Vcc
	-Optional JN package for 22V10 power/ground	and -40 to +85°C temperatures
	compatibility	■ Ideal for Combinatorial, Synchronous and
■ Most Powerful 24-pin PLD Available		Asynchronous Logic Applications
	- 20 I/Os, 2 inputs/clocks, 40 registers/latches	- Integration of multiple PLDs and random logic
	- 40 logic cell output functions	- Buried counters, complex state-machines
	- PLA structure with true product-term sharing	- Comparators, decoders, multiplexers and
	- Logic functions and registers can be I/O-buried	other wide-gate functions
■	Flexible Logic Cell	■ Development and Programmer Support
	- Multiple output functions per cell	- ICT PLACE Development Software
	- D,T and JK registers with special features	- Fitters for ABEL, CUPL and other software
	- Independent or global clocks, resets, presets,	-Programming support by ICT PDS-3 and popular third-
	clock polarity and output enables	party programmers
	-Sum of products logic for output enable

General Description

The PA7024 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7024 is by far the most powerful 24-pin PLD available today with 20 I/O pins, 2 input/global-clocks and 40 registers/latches (20 buried logic cells and 20 I/O registers/latches). Its logic array implements 84 sum-of-product logic functions that share 80 product terms. The PA7024’s logic and I/O cells (LCCs, IOCs) are extremely flexible, offering two output functions per logic cell (a total of 40 for all 20 logic cells). Logic cells are configurable as D, T, and JK registers with independent

or global clocks, resets, presets, clock polarity, and other special features. This makes them suitable for a wide variety of combinatorial, synchronous and asynchronous logic applications. With pin compatibility and super-set functionality to most 24-pin PLDs, (22V10, EP610/630, GAL6002), the PA7024 can implement designs that exceed the architectures of such devices. The PA7024 supports speeds as fast as 10ns/15ns (tpdi/tpdx) and 71.4MHz (fMAX) at moderate power consumption 120mA (85mA typical). Packaging includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure 1). Development and programming support for the PA7024 is provided by ICT and popular third-party development tool manufacturers.

Figure 1: Pin Configuration

Figure 2. Block Diagram

SOIC

DIP

PLCC-J	PLCC-JN

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PA7024

Table 1. Absolute Maximum Ratings

This device has been designed and tested for the recommended operating conditions. Proper operation outside these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.

Symbol	Parameter	Conditions	Ratings	Unit
VCC	Supply Voltage	Relative to Ground	-0.5 to + 7.0	V
VI, VO	Voltage Applied to Any Pin2	Relative to Ground1	-0.5 to VCC + 0.6	V
IO	Output Current	Per pin (IOL, IOH)	±25	mA
TST	Storage Temperature		-65 to + 150	°C
TLT	Lead Temperature	Soldering 10 seconds	+300	°C
Table 2. Operating Ranges

	Symbol	Parameter	Conditions	Min	Max	Unit
	VCC	Supply Voltage	Commercial	4.75	5.25	V
			Industrial	4.5	5.5
	TA	Ambient Temperature	Commercial	0	+70	°C
			Industrial	-40	+85
	TR	Clock Rise Time	See Note 2		20	ns
	TF	Clock Fall Time	See Note 2		20	ns
	TRVCC	VCC Rise Time	See Note 2		250	ms
	Table 3. D.C. Electrical Characteristics over the recommended operating conditions

	Symbol	Parameter	Conditions		Min	Max	Unit
	VOH	Output HIGH Voltage - TTL	VCC = Min, IOH = -4.0mA		2.4		V
	VOHC	Output HIGH Voltage - CMOS	VCC = Min, IOH = -10µA		VCC - 0.3		V
	VOL	Output LOW Voltage - TTL	VCC = Min, IOL = 16mA			0.5	V
	VOLC	Output LOW Voltage - CMOS	VCC = Min, IOL = 10µA			0.15	V
	VIH	Input HIGH Level			2.0	VCC + 0.3	V
	VIL	Input LOW Level			-0.3	0.8	V
	IIL	Input Leakage Current	VCC = Max, GND ≤ VIN ≤ VCC			±10	µA
	IOZ	Output Leakage Current	I/O = High-Z, GND ≤ VO ≤ VCC			±10	µA
	ISC	Output Short Circuit Current4	VCC = 5V, VO = 0.5V, TA= 25°C		-30	-120	mA
				-15		120
			VIN = 0V or VCC3,11
	ICC11			-20	85 (typ.)17	120
		VCC Current	f = 25MHz				mA
				-25		120
			All outputs disabled4
				I-25		130
	CIN7	Input Capacitance5	TA = 25°C, VCC = 5.0V			6	pF
	COUT7	Output Capacitance5	@ f = 1 MHz			12	pF

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