ICT PA7128J-15, PA7128J-20, PA7128JI-15, PA7128JI-20, PA7128S-15 Datasheet
...
1 of 6
PA7128
or global clocks, resets, presets, clock polarity and other
special features, making the P A7128 suitable for a variety of
combinatorial, synchronou s and asynchronous logic appl ications. The PA 7128 offers pin compatibility a nd super-set
functionality to popular 28-pin PLDs, such as the 26V12.
Thus, designs that exceed the architectures of such
devices can be expanded upon. The PA7128 supports
speeds as fast as 9ns/15ns (tpdi/tpdx) and 83.3MHz (f
MAX
)
at moderate power consumption 105mA (75mA typical).
Packaging includes 28-pin DIP, SOIC and PLCC (see Figure 1). Development and programming support for the
PA7128 is provided by ICT and popular third-party development tool manufacturers.
PA7128 PEELTM Array
Programmable Electrica lly Erasable Logic Array
■
CMOS Electrically Erasable Technology
− Reprogrammable in 28-pin DIP, SOIC and PLCC
packages
■
Versatile Logic Array Architecture
− 12 I/Os, 14 inputs, 36 registers/latches
− Up to 36 logic cell output functions
− PLA structure with true product-term sharing
− Logic functions and registers can be I/O-buried
■
Flexible Logic Cell
− Up to 3 output functions per logic cell
− D,T and JK registers with special features
− Independent or global clocks, resets, presets, clock
polarity and output enables
− Sum-of-products logic for output enables
■
High-Speed Commercial and Industrial Versions
− As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f
MAX
)
− Industrial grade available for 4.5 to 5.5V Vcc
and -40 to +85 °C temperatures
■
Ideal for Comb in at orial, Synch ronous and Asynchronous Logi c A pplication s
− Integration of multiple PLDs and random logic
− Buried counters, complex state-machines
− Comparitors, decoders, other wide-gate functions
■
Development and Programmer Support
− ICT PLACE Development Software
− Fitters for ABEL, CUPL and other software
− Programming support by ICT PDS-3 and other popu-
lar third-party programmers.
General Description
Features
DIP
PLCC
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1/CLK1
I
I
I
I
I
Vcc
I
I
I
I
I
I
I
1/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
1/CLK
1
1
1
1
1
1
Vcc
1
1
1
1
1
1
1
1CLK2
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Logic Control Cells
Global Cells
I/O Cells
Input Cells
Commercial/
Industrial
Figure 1. Pin Configuration
Figure 2. Block Diagram
The PA71 28 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinar y PLDs by providing the
architectural flexibility and speed needed for today’s programmable logic designs. The PA7128 offers a versatile
logic array architecture with 12 I/O pi ns, 14 input pins and
36 registers/latches (12 buried logic cells, 12 input registers/latches, 12 buried I/O registers/latches). Its l ogic array
implements 50 sum-of-products logic f unctions that share
64 product terms. The PA7128’s logic and I/O cells (LCCs,
IOCs) are extremely flexible offering up to three output
functions per cell (a total of 36 for all 12 logic cells). Cells
are configurable as D, T and JK registers with independent
2
2 of 6
PA7128
This device has been designed and tested for the recommended operating conditions. Proper operation outside of
these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage
Table 2. Absolute Maximum Ratings
Symbol Parameter Conditions Ratings Unit
V
CC
Supply Voltage Relative to Ground -0.5 to + 7.0 V
V
I
, V
O
Voltage Applied to Any Pin
Relative to Ground
1
-0.5 to VCC + 0.6 V
I
O
Output Current Per pin (IOL, IOH)±25mA
T
ST
Storage Temperature -65 to + 150 °C
T
LT
Lead Temperature Soldering 10 seconds +300 °C
Table 3. Operating Ranges
Symbol Parameter Conditions Min Max Unit
V
CC
Supply Voltage
Commercial 4.75 5.25
V
Industrial 4.5 5.5
T
A
Ambient Temperature
Commercial 0 +70
°C
Industrial -40 +85
T
R
Clock Rise Time See Note 2 20 ns
T
F
Clock Fall Time See Note 2 20 ns
T
RVCC
V
CC
Rise Time See Note 2 250 ms
Table 4. D.C. Electrical Characteristics
Symbol Parameter Conditions Min Max Unit
V
OH
Output HIGH Voltage - TTL VCC = Min, IOH = -4.0mA 2.4 V
V
OHC
Output HIGH Voltage - CMOS VCC = Min, IOH = -10µA VCC - 0.3 V
V
OL
Output LOW Voltage - TTL V
CC
= Min, I
OL
= 16mA 0.5 V
V
OLC
Output LOW Voltage - CMOS VCC = Min, IOL = -10µA 0.15 V
V
IH
Input HIGH Level 2.0 VCC + 0.3 V
V
IL
Input LOW Level -0.3 0.8 V
I
IL
Input Le ak ag e C ur re n t V
CC
= Max, GND ≤ V
IN
≤
V
CC
±10 µA
I
OZ
Outp ut Le ak ag e C urr e nt I/O = High- Z , GN D ≤ V
O
≤
V
CC
±10 µA
I
SC
Output Short Circuit Current
4
VCC = 5V, VO = 0.5V, TA= 25°C -30 -120 mA
ICC
11
VCC Current
V
IN
= 0V or V
CC
3,11
f = 25MHz
All outputs disabled
4
-15
75 (typ.)
19
105
mA-20 105
I-20 115
C
IN
7
Input Capacitance
5
TA = 25°C, VCC = 5.0V
@ f = 1 MHz
6pF
C
OUT
7
Output Capacitance
5
12 pF
Over the recommended operating conditions
Loading...