ICT PA7024JN-25, PA7024JN-20, PA7024JN-15, PA7024JI-20, PA7024JI-15 Datasheet

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PA7024

PA7024 PEEL

TM

Array

Programmable Electrically Erasable Logic A rray

■

CMOS Electrically Erasable Technology

- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages

-Optional JN package for 22V10 power/ground
compatibility

■

Most Powerful 24-pin PLD Available

- 20 I/Os, 2 inputs/clocks, 40 registers/latches

- 40 logic cell output functions

- PLA structure with true product-term sharing

- Logic functions and registers can be I/O-buried

■

Flexible Logic Cell

- Multiple output functions per cell

- D,T and JK registers with special features

- Independent or global clocks, resets, presets,

clock polarity and output enables

-Sum of products logic for output enable

■

High-Speed Commercial and Industrial Versions

- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)

- Industrial grade available for 4.5 to 5.5V Vcc
and -40 to +85°C temperatures

■

Ideal for Comb in at orial, Synchronous and
Asynchrono us Lo gi c Applications

- Integration of multiple PLDs and random logic

- Buried counters, complex state-machines

- Comparators, decoders, multiplexers and
other wide-gate functions

■

Development and Programmer Support

- ICT PLACE Development Software

- Fitters for ABEL, CUPL and other software

-Programming support by ICT PDS-3 and popular third­party programmer s

The PA70 24 is a member of the Programmable Electrical ly
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free design­ers from the limitations of ordina ry PLDs by providing the
architectural flexibility and speed needed for today’s pro­grammable logic designs. The PA7024 is by far the most
powerful 24-pin PLD available today with 20 I/O pins, 2
input/global-clocks and 40 registers/latches (20 buried logic
cells and 20 I/O registers/latches). Its logic array imple­ments 84 sum-of-product logic functions that share 80
product terms. The PA7024’s logic and I/O cells (LCCs,
IOCs) are extremely flexible, offering two output functions
per logic cell (a total of 40 for all 20 logic cells). Logic cells
are configurable as D, T, and JK registers w ith indepe ndent

or global clocks, resets, presets, clock polarity, and other
special features. This makes them suitable for a wide vari­ety of combinator ial, synchronous an d asynchrono us logic
applications. With pin compatib ility and super-set function­ality to most 24-pin PLDs, (22V10, EP610/630, GAL6002),
the PA7024 c an implement designs that exceed the archi­tectures of such devices. The PA7024 suppor ts speeds as
fast as 10ns/15ns (tpdi/tpdx) and 71.4MH z (fMAX) at mod­erate power consumption 120mA (85mA typical). Packag­ing includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure

1). Development and programming suppor t for the PA7024
is provided by ICT and popular third-party development tool
manufacturers.

General Description

Features

DIP

PLCC-J

PLCC-JN

SOIC

Figur e 1: Pin Configuration Figur e 2. Block Diagram

Commercial/

Industrial

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PA7024

Table 1. Absolute Maximum Ratings

Symbol Parameter Conditions Ratings Unit

V

CC

Supply Voltage Relative to Ground -0.5 to + 7.0 V

V

I

, V

O

Voltage Applied to Any Pin

2

Relative to Ground

1

-0.5 to VCC + 0.6 V

I

O

Output Current Per pin (IOL, IOH)±25mA

T

ST

Storage Temperature -65 to + 150 °C

T

LT

Lead Temperature Soldering 10 seconds +300 °C

Table 2. Operating Ranges

Symbol Parameter Conditions Min Max Unit

V

CC

Supply Voltage

Commercial 4.75 5.25

V

Industrial 4.5 5.5

T

A

Ambient Temperature

Commercial 0 +70

°C

Industrial -40 +85

T

R

Clock Rise Time See Note 2 20 ns

T

F

Clock Fall Time See Note 2 20 ns

T

RVCC

V

CC

Rise Time See Note 2 250 ms

Table 3. D.C. Electrical Characteristics over the recommended operating conditions

Symbol Parameter Conditions Min Max Unit

V

OH

Output HIGH Voltage - TTL VCC = Min, IOH = -4.0mA 2.4 V

V

OHC

Output HIGH Voltage - CMOS VCC = Min, IOH = -10µA VCC - 0.3 V

V

OL

Output LOW Voltage - TTL V

CC

= Min, I

OL

= 16mA 0.5 V

V

OLC

Output LOW Voltage - CMOS VCC = Min, IOL = 10µA 0.15 V

V

IH

Input HIGH Leve l 2.0 VCC + 0.3 V

V

IL

Input LOW Level -0.3 0.8 V

I

IL

Input Le ak ag e C ur re n t V

CC

= Max, GND ≤ V

IN

≤

V

CC

±10 µA

I

OZ

Outp ut Le ak ag e C urr e nt I/O = High- Z , GN D ≤ V

O

≤

V

CC

±10 µA

I

SC

Output Short Circuit Current

4

VCC = 5V, VO = 0.5V, TA= 25°C -30 -120 mA

I

CC

11

VCC Current

V

IN

= 0V or V

CC

3,11

f = 25MHz
All outputs disabled

4

-15

85 (typ.)

17

120

mA

-20 120

-25 120

I-25 130

C

IN

7

Input Capacitance

5

TA = 25°C, VCC = 5.0V
@ f = 1 MHz

6pF

C

OUT

7

Output Capacitance

5

12 pF

This device has been designed and tested for the recommended
operating conditions. Proper operation outside these levels is not
guaranteed. Exposure to absolute maximum ratings may cause per­manent damage.