ICST AV9248F-87, ICS9248F-87 Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-87

Third party brands and names are the property of their respective owners.

Block Diagram

9248-87 Rev D 10/27/00

Recommended Application:

810/810E type chipset.

Output Features:

• 2- CPUs @2.5V, up to 155MHz.

• 9 - SDRAM @ 3.3V, up to 155MHz.

• 8 - PCICLK @ 3.3V

• 1 - IOAPIC @ 2.5V,

• 2 - 3V66MHz @ 3.3V

• 2- 48MHz, @3.3V fixed.

• 1- 24/48MHz, @3.3V

• 1- REF @3.3V, 14.318MHz.

Features:

• Up to 155MHz frequency support

• Support FS0-FS3 strapping status bit for I

2

C read back.

• Support power management: Power down Mode from I

2

C

programming.

• Spread spectrum for EMI control ( ± 0.25% center).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• SDRAM - SDRAM: < 250ps

• 3V66 – 3V66: <175ps

• PCI – PCI: <500ps

• For group skew specification, please refer to group
timing relationships table.

Preliminary Product Preview

Functionality

Pin Configuration

48-Pin 300mil SSOP

*: These inputs have a 120K pull up to VDD.
1: These are double strength.

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0000

3.3800.13.3884.5547.7278.3147.72

0001

00.42100.100.42176.2833.1476.0233.14

0010

00.55100.100.55133.30176.1538.5276.15

0011

69.34133.100.80100.2700.6300.8100.63

0100

00.0776.000.50100.0700.5305.7100.53

0101

00.21100.100.21176.4733.7376.8133.73

0110

00.05100.100.05100.00100.0500.5200.05

0111

00.04133.100.50100.0700.5305.7100.53

1000

33.8676.005.20133.8671.4380.7171.43

1001

00.70100.100.70133.1776.5338.7176.53

10 10

00.83100.100.83100.2900.6400.3200.64

10 11

33.73133.100.30176.8643.4371.7143.43

1100

08.6676.002.00108.6604.3307.6104.33

1101

03.00100.103.00108.6604.3307.6104.33

1110

06.33100.106.33170.9835.4472.2235.44

1111

06.33133.102.00108.6604.3307.6104.33

Frequency Generator & Integrated Buffers for Celeron & PII/III™

SEL24_48#

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK [1:0]

SDRAM [7:0]

SDRAM_F

IOAPIC

PCICLK [7:0]

8

2

8

2

2

3V66 [1:0]

X1

X2

XTAL

OSC

CPU

DIVDER

SDRAM
DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

S DATA

SCLK

IC

2

FS[3:0]

PD#

Control

Logic

Config.

Reg.

/ 2

REF1

{

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

2

ICS9248-87

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

Power Groups

GNDREF, VDDREF = REF1, X1, X2
GNDPCI, VDDPCI = PCICLK [7:0]
GNDSDRAM, VDDSDRAM = SDRAM [8:0]
GND3V66, VDD3V66 = 3V66
VDD48 = 48MHz, 24MHz
GNDCOR, VDDCOR = supply for PLL core
VDDLAPIC = IOAPIC
GNDLCPU, VDDLCPU = CPUCLKL [1:0]

The ICS9248-87 is the single chip clock solution for designs
using 810/810E style chipset. It provides all necessary clock
signals for such a system.

Spread spectrum may be enabled through I

2

C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-87
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Serial programming I

2

C interface allows changing functions,

stop clock programming and frequency selection.

PIN NUMBER PIN NAME TYPE DESCRIPTION

REF1 OUT 14.318 MHz reference clock.

FS3 IN Frequency select pin.

2, 6, 16, 24, 27, 34,

42

VDD PWR

3.3V Power supply for SD R A M output buffers, PCI output buff ers , re ference

o

utput buffers and 48MHz output
3 X1 IN Crystal input,no mi nally 14.318MHz.
4 X2 OUT Crystal output, nominally 14.318MHz.

5, 9, 13, 20, 26, 30,

38

GND PWR Ground pin for 3V outputs.

8, 7 3V66 [1:0] OUT 3V66 clock outputs.

FS0 IN Frequency select pin.

PCICLK0 OUT PCI clock outp ut .

FS1 IN Frequency select pin.

PCICLK1 OUT PCI clock outp ut .

FS2 IN Frequency select pin.

PCICLK2 OUT PCI clock outp ut .

19, 18, 17, 15, 14 PCICLK [7:3] OUT PCI clock outputs.

21, 22 48MHz OUT 48MHz output clocks

SEL24_48# IN

Sel pin for enabling 24MHz or 48MHz
H=24MHz L=48MHz

24_48MHz OUT Clock output for super I/O/USB
25 SDATA IN Data input for I2C serial input, 5V tolera nt input
28 SCLK IN Clock input of I2C input, 5V t ole rant input

29 PD# IN

Asynchronous active low input pin used to power down the devic e into a low
power state. The internal clocks are disabled and the VCO and the crystal are

s

topped. The latency of the power down will not be greater than 3ms.

31 SDRAM_F OUT

SDRAM clock output - free running not affected by I

2

C

32, 33, 35, 36, 37,

39, 40, 41

SDRAM [7:0] OUT SDRAM clock outputs

43 GNDL C P U PWR Ground pin for the CPU clocks.

44, 45 CPUCLK [1:0] OUT CPU clock output s.

46 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V
47 IOAPIC OUT 2.5V clock output
48 VDDLAPIC PWR Power pin f or the IOAPIC. 2.5V

23

1

11

12

10

3

ICS92 48-87

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I

2

C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I

2

C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.

 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

ACK

Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Stop Bit

H

ow to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D2

(H)

ACK

Dummy Command Code

ACK

Dummy Byte Count

ACK

Byte 0

ACK

Byte 1

ACK

Byte 2

ACK

Byte 3

ACK

Byte 4

ACK

Byte 5

ACK

Stop Bit

H

ow to Write:

4

ICS9248-87

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte4: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

1) All entries selectable through I2C. Entries 1 -16 are also selectable through FS pins.

2) The IOAPIC Frequency change from IOAPIC=PCICLK/2 to IOAPIC=PCICLK is
controlled by IOAPC_Freq control in I2C Byte 3 Bit 1, default is IOAPIC=PCICLK/2.

3) Read back code of PWD shows revision ID.

I2C is a trademark of Philips Corporation

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00000 3.3800.13.3884.5547.7278.3147.72
00001 00.42100.100.42176.2833.1476.0233.14
00010 00.55100.100.55133.30176.1538.5276.15
00011 69.34133.100.80100.2700.6300.8100.63
00100 00.0776.000.50100.0700.5305.7100.53
00101 00.21100.100.21176.4733.7376.8133.73
00110 00.05100.100.05100.00100.0500.5200.05
00111 00.04133.100.50100.0700.5305.7100.53
01000 33.8676.005.20133.8671.4380.7171.43
01001 00.70100.100.70133.1776.5338.7176.53
01010 00.83100.100.83100.2900.6400.3200.64
01011 33.73133.100.30176.8643.4371.7143.43
01100 08.6676.002.00108.6604.3307.6104.33
01101 03.00100.103.00108.6604.3307.6104.33
01110 06.33100.106.33170.9835.4472.2235.44
01111 06.33133.102.00108.6604.3307.6104.33
10000 00.54100.100.54176.6933.8471.4233.84
10001 00.04100.100.04133.3976.6433.3276.64
10010 00.63100.100.63176.0933.5476.2233.54
10011 00.03100.100.03176.6833.3476.1233.34
10100 00.92100.100.92100.6800.3405.1200.34
1010 1 00.72100.100.72176.4833.2471.1233.24
10110 00.12100.100.12176.0833.0471.0233.04
10111 00.91100.100.91133.9776.9338.9176.93
11000 00.71100.100.71100.8700.9305.9100.93
11001 00.41100.100.41100.6700.8300.9100.83
11010 00.01100.100.01133.3776.6333.8176.63
11011 00.50100.100.50100.0700.5305.7100.53
11100 33.5776.000.31133.5776.7338.8176.73
11101 33.35133.100.51176.6733.8371.9133.83
11110 36.05133.100.31133.5776.7338.8176.73
11111 36.64133.100.01133.3776.6333.8176.63

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