IS61LV6432
IS61LV6432
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
FEATURES
•Internal self-timed write cycle
•Individual Byte Write Control and Global Write
•Clock controlled, registered address, data and control
•Pentium™ or linear burst sequence control using MODE input
•Three chip enables for simple depth expansion and address pipelining
•Common data inputs and data outputs
•Power-down control by ZZ input
•JEDEC 100-Pin LQFP and PQFP package
•3.3V VCC and 2.5V VCCQ for 2.5 I/O's
•Two Clock enables and one Clock disable to eliminate multiple bank bus contention.
•Control pins mode upon power-up:
–MODE in interleave burst mode
–ZZ in normal operation mode
These control pins can be connected to GNDQ or VCCQ to alter their power-up state
• Industrial temperature available
FAST ACCESS TIME
DESCRIPTION
The ICSI IS61LV6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-perfor- mance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61LV6432 and controlled by the ADV (burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
Symbol |
Parameter |
-166 |
-133 |
-117 |
-5 |
-6 |
-7 |
-8 |
Unit |
tKQ |
CLK Access Time |
5 |
5 |
5 |
5 |
6 |
7 |
8 |
ns |
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tKC |
Cycle Time |
6 |
7.5 |
8.5 |
10 |
12 |
13 |
15 |
ns |
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— |
Frequency |
166 |
133 |
117 |
100 |
83 |
75 |
66 |
MHz |
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ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc. |
1 |
SSR005-0B |
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IS61LV6432
BLOCK DIAGRAM
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MODE |
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CLK |
CLK |
Q0 |
A0 |
A0’ |
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BINARY |
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COUNTER |
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A1’ |
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ADV |
CE |
Q1 |
A1 |
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64K x 32 |
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ADSC |
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CLR |
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MEMORY |
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ADSP |
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ARRAY |
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16 |
D |
Q |
14 |
16 |
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A15-A0 |
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ADDRESS |
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REGISTER |
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CE |
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CLK |
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32 |
32 |
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GW |
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Q |
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BWE |
DQ32-DQ25 |
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BW4 |
BYTE WRITE |
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REGISTERS |
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CLK |
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D |
Q |
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BW3 |
DQ24-DQ17 |
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BYTE WRITE |
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REGISTERS |
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CLK |
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D |
Q |
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DQ16-DQ9 |
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BW2 |
BYTE WRITE |
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REGISTERS |
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CLK |
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D |
Q |
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BW1 |
DQ8-DQ1 |
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BYTE WRITE |
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REGISTERS |
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CLK |
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CE1 |
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4 |
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CE2 |
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Q |
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INPUT |
OUTPUT |
32 |
CE3 |
ENABLE |
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REGISTERS |
REGISTERS |
DATA[32:1] |
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OE |
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REGISTER |
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CLK |
CLK |
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CE |
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CLK |
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D |
Q |
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ENABLE |
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DELAY |
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REGISTER |
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CLK |
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OE |
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2 |
Integrated Circuit Solution Inc. |
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SSR005-0B |
IS61LV6432
PIN CONFIGURATION
100-Pin LQFP and PQFP (Top View)
NC DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
VCCQ
VCC
NC
GND DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
A6 |
A7 |
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CE1 |
CE2 |
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BW4 |
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BW3 |
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BW2 |
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BW1 |
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CE3 VCC |
GND CLK |
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GW |
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BWE |
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OE |
ADSC |
ADSP |
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ADV |
A8 |
A9 |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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1 |
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80 |
NC |
2 |
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79 |
DQ16 |
3 |
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78 |
DQ15 |
4 |
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77 |
VCCQ |
5 |
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76 |
GNDQ |
6 |
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75 |
DQ14 |
7 |
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74 |
DQ13 |
8 |
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73 |
DQ12 |
9 |
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72 |
DQ11 |
10 |
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71 |
GNDQ |
11 |
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70 |
VCCQ |
12 |
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69 |
DQ10 |
13 |
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68 |
DQ9 |
14 |
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67 |
GND |
15 |
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66 |
NC |
16 |
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65 |
VCC |
17 |
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64 |
ZZ |
18 |
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63 |
DQ8 |
19 |
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62 |
DQ7 |
20 |
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61 |
VCCQ |
21 |
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60 |
GNDQ |
22 |
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59 |
DQ6 |
23 |
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58 |
DQ5 |
24 |
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57 |
DQ4 |
25 |
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56 |
DQ3 |
26 |
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55 |
GNDQ |
27 |
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54 |
VCCQ |
28 |
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53 |
DQ2 |
29 |
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52 |
DQ1 |
30 |
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51 |
NC |
31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
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MODE |
A5 |
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A4 |
A3 |
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A2 A1 A0 NC |
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NC GND |
VCC NC NC A10 A11 |
A12 A13 |
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A14 |
A15 |
NC |
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PIN DESCRIPTIONS
A0-A15 |
Address Inputs |
CLK |
Clock |
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ADSP |
Processor Address Status |
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ADSC |
Controller Address Status |
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ADV |
Burst Address Advance |
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BW1-BW4 |
Synchronous Byte Write Enable |
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BWE |
Byte Write Enable |
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GW |
Global Write Enable |
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CE1, CE2, CE3 |
Synchronous Chip Enable |
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OE |
Output Enable |
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DQ1-DQ32 |
Data Input/Output |
ZZ |
Sleep Mode |
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MODE |
Burst Sequence Mode |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
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VCCQ |
Isolated Output Buffer Supply: |
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+3.3V |
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GNDQ |
Isolated Output Buffer Ground |
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NC |
No Connect |
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Integrated Circuit Solution Inc. |
3 |
SSR005-0B |
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IS61LV6432
TRUTH TABLE
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Address |
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Operation |
Used |
CE1 |
CE2 |
CE3 |
ADSP |
ADSC |
ADV |
WRITE |
OE |
DQ |
Deselected, Power-down |
None |
H |
X |
X |
X |
L |
X |
X |
X |
High-Z |
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Deselected, Power-down |
None |
L |
L |
X |
L |
X |
X |
X |
X |
High-Z |
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Deselected, Power-down |
None |
L |
X |
H |
L |
X |
X |
X |
X |
High-Z |
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Deselected, Power-down |
None |
L |
L |
X |
H |
L |
X |
X |
X |
High-Z |
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Deselected, Power-down |
None |
L |
X |
H |
H |
L |
X |
X |
X |
High-Z |
Read Cycle, Begin Burst |
External |
L |
H |
L |
L |
X |
X |
X |
L |
Q |
Read Cycle, Begin Burst |
External |
L |
H |
L |
L |
X |
X |
X |
H |
High-Z |
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Write Cycle, Begin Burst |
External |
L |
H |
L |
H |
L |
X |
L |
X |
D |
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Read Cycle, Begin Burst |
External |
L |
H |
L |
H |
L |
X |
H |
L |
Q |
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Read Cycle, Begin Burst |
External |
L |
H |
L |
H |
L |
X |
H |
H |
High-Z |
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Read Cycle, Continue Burst |
Next |
X |
X |
X |
H |
H |
L |
H |
L |
Q |
Read Cycle, Continue Burst |
Next |
X |
X |
X |
H |
H |
L |
H |
H |
High-Z |
Read Cycle, Continue Burst |
Next |
H |
X |
X |
X |
H |
L |
H |
L |
Q |
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Read Cycle, Continue Burst |
Next |
H |
X |
X |
X |
H |
L |
H |
H |
High-Z |
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Write Cycle, Continue Burst |
Next |
X |
X |
X |
H |
H |
L |
L |
X |
D |
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Write Cycle, Continue Burst |
Next |
H |
X |
X |
X |
H |
L |
L |
X |
D |
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Read Cycle, Suspend Burst |
Current |
X |
X |
X |
H |
H |
H |
H |
L |
Q |
Read Cycle, Suspend Burst |
Current |
X |
X |
X |
H |
H |
H |
H |
H |
High-Z |
Read Cycle, Suspend Burst |
Current |
H |
X |
X |
X |
H |
H |
H |
L |
Q |
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Read Cycle, Suspend Burst |
Current |
H |
X |
X |
X |
H |
H |
H |
H |
High-Z |
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Write Cycle, Suspend Burst |
Current |
X |
X |
X |
H |
H |
H |
L |
X |
D |
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Write Cycle, Suspend Burst |
Current |
H |
X |
X |
X |
H |
H |
L |
X |
D |
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Notes: |
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1.All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2.Wait states are inserted by suspending burst.
3.X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH.
4.For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time.
5.ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function |
GW |
BWE |
BW1 |
BW2 |
BW3 BW4 |
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READ |
H |
H |
X |
X |
X |
X |
READ |
H |
X |
H |
H |
H |
H |
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WRITE Byte 1 |
H |
L |
L |
H |
H |
H |
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WRITE All Bytes |
X |
L |
L |
L |
L |
L |
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WRITE All Bytes |
L |
X |
X |
X |
X |
X |
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4 |
Integrated Circuit Solution Inc. |
|
SSR005-0B |
IS61LV6432
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address |
1st Burst Address |
2nd Burst Address |
3rd Burst Address |
A1 A0 |
A1 A0 |
A1 A0 |
A1 A0 |
00 |
01 |
10 |
11 |
|
|
|
|
01 |
00 |
11 |
10 |
10 |
11 |
00 |
01 |
|
|
|
|
11 |
10 |
01 |
00 |
|
|
|
|
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1’, A0’ = 1,1 |
0,1 |
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
TBIAS |
Temperature Under Bias |
–10 to +85 |
°C |
|
|
|
|
TSTG |
Storage Temperature |
–55 to +150 |
°C |
|
|
|
|
PD |
Power Dissipation |
1.8 |
W |
|
|
|
|
IOUT |
Output Current (per I/O) |
100 |
mA |
|
|
|
|
VIN, VOUT |
Voltage Relative to GND for I/O Pins |
–0.5 to VCCQ + 0.3 |
V |
|
|
|
|
VIN |
Voltage Relative to GND for |
–0.5 to 4.6 |
V |
|
for Address and Control Inputs |
|
|
|
|
|
|
Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3.This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc. |
5 |
SSR005-0B |
|