IC62LV256
Document Title
32K x 8 Low Power SRAM with 3.3V
Revision History
Revision No |
History |
Draft Date |
Remark |
0A |
Initial Draft |
October 5,2001 |
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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
ALSR007-0A 10/5/2001
IC62LV256
32K x 8 LOW VOLTAGE STATIC RAM
FEATURES
•Access time: 45, 70, 100 ns
•Low active power: 70 mW
•Low standby power
— 60 µW CMOS standby
•Fully static operation: no clock or refresh required
•TTL compatible inputs and outputs
•Single 3.3V power supply
DESCRIPTION
The ICSI IC62LV256 is a low power, 32, 768-word by 8-bit static RAM. It is fabricated using ICSI's high-performance CMOS double-metal technology.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 20 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IC62LV256 is pin compatible with other 32K x 8 SRAMs in 300mil DIP and SOJ, 330mil SOP, and 8*13.4mm TSOP-1 packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14 |
DECODER |
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256 X 1024 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
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CE |
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CONTROL |
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OE |
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CIRCUIT |
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WE |
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ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc. |
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ALSR007-0A 10/5/2001 |
IC62LV256
PIN CONFIGURATION |
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PIN CONFIGURATION |
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28-Pin DIP, SOJ and SOP |
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8x13.4mm TSOP-1 |
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A14 |
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28 |
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VCC |
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A10 |
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OE |
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A12 |
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27 |
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WE |
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20 |
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26 |
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A13 |
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A11 |
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CE |
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A7 |
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I/O7 |
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A6 |
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A8 |
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A9 |
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4 |
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I/O6 |
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A8 |
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A5 |
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24 |
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A9 |
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A13 |
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26 |
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I/O5 |
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I/O4 |
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A4 |
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A11 |
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WE |
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A3 |
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VCC |
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I/O3 |
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OE |
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A2 |
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8 |
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A10 |
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A14 |
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GND |
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A12 |
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I/O2 |
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A1 |
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CE |
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A7 |
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I/O1 |
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A0 |
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I/O7 |
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A6 |
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I/O0 |
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I/O0 |
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I/O6 |
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A5 |
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A0 |
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I/O1 |
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I/O5 |
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A4 |
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A1 |
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I/O2 |
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I/O4 |
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A3 |
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A2 |
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GND |
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14 |
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I/O3 |
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PIN DESCRIPTIONS
A0-A14 |
Address Inputs |
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CE |
Chip Enable Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Input/Output |
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Vcc |
Power |
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GND |
Ground |
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TRUTH TABLE
Mode |
WE |
CE |
OE |
I/O Operation |
Vcc Current |
Not Selected |
X |
H |
X |
High-Z |
ISB1, ISB2 |
(Power-down) |
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Output Disabled |
H |
L |
H |
High-Z |
ICC1, ICC2 |
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Read |
H |
L |
L |
DOUT |
ICC1, ICC2 |
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Write |
L |
L |
X |
DIN |
ICC1, ICC2 |
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
–0.5 to +4.6 |
V |
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TBIAS |
Temperature Under Bias |
–55 to +125 |
°C |
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TSTG |
Storage Temperature |
–65 to +150 |
°C |
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PT |
Power Dissipation |
0.5 |
W |
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IOUT |
DC Output Current (LOW) |
20 |
mA |
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Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc. |
3 |
ALSR007-0A 10/5/2001