IC62LV1008L
IC62LV1008LL
Document Title
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No |
History |
Draft Date |
Remark |
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0A |
Initial Draft |
January 3,2002 |
Preliminary |
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc. |
1 |
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
1M x 8 LOW POWER and LOW VCC |
Preliminary |
CMOS STATIC RAM |
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FEATURES
•Access times of 55, 70, 100 ns
•CMOS Low power operation: ICC=15mA (typical)* operation ISB2=2µA (typical)* standby
•Low data retention voltage: 1.5V (min.)
•Output Enable (OE) and Two Chip Enables (CE1, CE2) inputs for ease in applications
•TTL compatible inputs and outputs
•Fully static operation:
— No clock or refresh reguired
•Single 2.7V-3.6V power supply
•Wafer level burn in test mode
•Available in the know good die form and 48-pin 8*10mm TF-BGA
* Typical values are measured at VCC=3.0V, TA=25°C
DESCRIPTION
The ICSI IC62LV1008L and IC62LV1008LL is a low voltage, 1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers.
When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable ( WE) controls both writing and reading of the memory.
The IC62LV1008L and IC62LV1008LL are available in know good die form and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A19 |
DECODER |
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1024K x 8 |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
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CE1 |
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CE2 |
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CONTROL |
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OE |
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CIRCUIT |
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ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 |
Integrated Circuit Solution Inc. |
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
PIN CONFIGURATIONS
48-Pin 8*10mm TF-BGA (TOP View)
1 |
2 |
3 |
4 |
5 |
6 |
A
B
C
D
E
F
G
H
NC |
OE |
A0 |
A1 |
A2 |
CE2 |
NC |
NC |
A3 |
A4 |
CE1 |
NC |
I/O0 |
NC |
A5 |
A6 |
NC |
I/O4 |
GND |
I/O1 |
A17 |
A7 |
I/O5 |
Vcc |
Vcc |
I/O2 |
Vcc |
A16 |
I/O6 |
GND |
I/O3 |
NC |
A14 |
A15 |
NC |
I/O7 |
NC |
NC |
A12 |
A13 |
WE |
NC |
A18 |
A8 |
A9 |
A10 |
A11 |
A19 |
PIN DESCRIPTIONS
A0-A19 |
Address Inputs |
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CE1 |
Chip Enable 1 Input |
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CE2 |
Chip Enable 2 Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Data Input/Output |
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NC |
No Connection |
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Vcc |
Power |
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GND |
Ground |
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TRUTH TABLE
Mode |
WE |
CE1 |
CE2 |
OE |
I/O Operation |
Vcc Current |
Not Selected |
X |
H |
X |
X |
High-Z |
ISB1, ISB2 |
(POWER-DOWN) |
X |
X |
L |
X |
High-Z |
ISB1, ISB2 |
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Output Disabled |
H |
L |
H |
H |
High-Z |
ICC |
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Read |
H |
L |
H |
L |
DOUT |
ICC |
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Write |
L |
L |
H |
X |
DIN |
ICC |
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OPERATING RANGE
Range |
Ambient Temperature |
VCC |
Commercial |
0°C to +70°C |
2.7V - 3.6V |
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Industrial |
–40°C to +85°C |
2.7V - 3.6V |
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Integrated Circuit Solution Inc. |
3 |
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
–0.5 to Vcc + 0.5 |
V |
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VCC |
Vcc related to GND |
–0.3 to +4.0 |
V |
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TBIAS |
Temperature Under Bias |
–40 to +85 |
°C |
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TSTG |
Storage Temperature |
–65 to +150 |
°C |
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PT |
Power Dissipation |
1 |
W |
Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1)(2)
Symbol |
Parameter |
Conditions |
Max. |
Unit |
CIN |
Input Capacitance |
VIN = 0V |
6 |
pF |
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COUT |
Output Capacitance |
VOUT = 0V |
8 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25oC, f = 1 MHz, VCC = 3.0 V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol |
Parameter |
Test Conditions |
Min. |
Max. |
Unit |
VOH |
Output HIGH Voltage |
VCC = Min., IOH = –1.0 mA |
2.0 |
— |
V |
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VOL |
Output LOW Voltage |
VCC = Min., IOL = 2.1 mA |
— |
0.4 |
V |
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VIH |
Input HIGH Voltage(1) |
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2.2 |
VCC + 0.3 |
V |
VIL |
Input LOW Voltage(2) |
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–0.2 |
0.4 |
V |
ILI |
Input Leakage |
GND ≤ VIN ≤ VCC |
–1 |
1 |
µA |
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ILO |
Output Leakage |
GND ≤ VOUT ≤ VCC |
–1 |
1 |
µA |
Notes:
1. VIH(max.) = VCC +2.0V for pulse width less than 10 ns. 1. VIL(min.) = –2.0V for pulse width less than 10 ns.
4 |
Integrated Circuit Solution Inc. |
LPSR015-0A 1/3/2001