ICSI IC61C256AH-10U, IC61C256AH-12J, IC61C256AH-12JI, IC61C256AH-12N, IC61C256AH-12NI, IC61C256AH-12T, IC61C256AH-12TI, IC61C256AH-12U, IC61C256AH-12UI, IC61C256AH-20NI, IC61C256AH-20T, IC61C256AH-20TI, IC61C256AH-20U, IC61C256AH-20UI, IC61C256AH-25JI, IC61C256AH-25NI, IC61C256AH-25TI, IC61C256AH-25UI, IC61C256AH-10J, IC61C256AH-10N, IC61C256AH-10T, IC61C256AH-15J, IC61C256AH-15JI, IC61C256AH-15N, IC61C256AH-15NI, IC61C256AH-15T, IC61C256AH-15TI, IC61C256AH-15U, IC61C256AH-20J, IC61C256AH-20JI, IC61C256AH-20N Datasheet

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IC61C256AH

Document Title

32K x 8 High Speed SRAM

Revision History

Revision No

History

Draft Date

Remark

0A

Initial Draft

March 23,2001

 

0B

Revise typo of tHA on page 7

October 18,2001

 

0C

Add SOP package type

February 18,2002

 

0D

Revise typo of sop size at page 2,9

April 19,2002

 

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc.

1

AHSR010-0D 4/19/2002

ICSI IC61C256AH-10U, IC61C256AH-12J, IC61C256AH-12JI, IC61C256AH-12N, IC61C256AH-12NI, IC61C256AH-12T, IC61C256AH-12TI, IC61C256AH-12U, IC61C256AH-12UI, IC61C256AH-20NI, IC61C256AH-20T, IC61C256AH-20TI, IC61C256AH-20U, IC61C256AH-20UI, IC61C256AH-25JI, IC61C256AH-25NI, IC61C256AH-25TI, IC61C256AH-25UI, IC61C256AH-10J, IC61C256AH-10N, IC61C256AH-10T, IC61C256AH-15J, IC61C256AH-15JI, IC61C256AH-15N, IC61C256AH-15NI, IC61C256AH-15T, IC61C256AH-15TI, IC61C256AH-15U, IC61C256AH-20J, IC61C256AH-20JI, IC61C256AH-20N Datasheet

IC61C256AH

32K x 8 HIGH-SPEED CMOS STATIC RAM

FEATURES

High-speed access times: 10, 12, 15, 20, 25 ns

Low active power: 400 mW (typical)

Low standby power

--250 W (typical) CMOS standby

--55 mW (typical) TTL standby

Fully static operation: no clock or refresh required

TTL compatible interface and outputs

Single 5V power supply

DESCRIPTION

The ICSI IC61C256AH is very high-speed, low power, 32,768 word by 8-bit static RAMs. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum.

When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 W (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IC61C256AH is pin compatible with other 32k x 8 SRAMs and are available in 28-pin 300mil PDIP, 300mil SOJ, and 8*13.4mm TSOP-1 package, 330 mil SOP.

FUNCTIONAL BLOCK DIAGRAM

A0-A14

DECODER

 

32K X 8

 

MEMORY ARRAY

 

 

 

 

 

 

 

VCC

GND

I/O

I/O0-I/O7 DATA COLUMN I/O

CIRCUIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

CIRCUIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

2

Integrated Circuit Solution Inc.

 

AHSR010-0D 4/19/2002

IC61C256AH

PIN CONFIGURATION

 

 

 

 

 

 

PIN CONFIGURATION

 

 

 

 

 

28-Pin DIP and SOJ and SOP

 

8x13.4mm TSOP-1

 

 

 

 

 

A14

 

1

28

 

VCC

 

 

 

 

 

 

22

21

 

A10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

A12

 

2

27

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

A13

 

A11

 

23

20

 

CE

A7

3

 

 

 

 

 

 

 

 

19

 

I/O7

A6

 

4

25

 

A8

 

 

 

A9

24

 

 

 

 

 

 

 

 

 

 

18

 

I/O6

 

 

 

A8

25

 

A5

 

 

24

 

A9

 

 

 

 

 

5

 

 

A13

 

26

17

 

I/O5

 

 

A4

 

23

 

A11

 

 

 

 

 

27

16

 

I/O4

 

6

 

 

 

WE

 

 

 

A3

 

 

22

 

 

 

 

 

 

VCC

 

28

15

 

I/O3

 

7

 

 

OE

 

 

 

 

 

 

A2

 

8

21

 

A10

 

A14

 

1

14

 

GND

 

 

A12

 

2

13

 

I/O2

 

 

 

 

 

 

 

 

 

 

 

 

A1

9

20

 

CE

 

 

 

A7

 

3

12

 

I/O1

 

 

 

19

 

I/O7

 

 

 

 

 

A0

10

 

 

 

 

A6

 

4

11

 

I/O0

 

 

 

 

 

I/O0

 

 

18

 

I/O6

 

 

 

 

 

 

11

 

 

 

 

A5

 

5

10

 

A0

 

 

 

 

 

I/O1

 

 

17

 

I/O5

 

 

 

 

 

 

 

 

 

 

A4

 

6

9

 

A1

 

12

 

 

 

 

 

 

 

 

I/O2

 

 

16

 

I/O4

 

 

 

A3

 

7

8

 

A2

 

13

 

 

 

 

 

 

GND

 

15

 

I/O3

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTIONS

A0-A14

Address Inputs

 

 

CE

Chip Enable Input

 

 

OE

Output Enable Input

 

 

WE

Write Enable Input

 

 

I/O0-I/O7

Input/Output

 

 

Vcc

Power

 

 

GND

Ground

 

 

TRUTH TABLE

Mode

WE

CE

OE

I/O Operation

Vcc Current

Not Selected

X

H

X

High-Z

ISB1, ISB2

(Power-down)

 

 

 

 

 

Output Disabled

H

L

H

High-Z

ICC1,ICC2

 

 

 

 

 

 

Read

H

L

L

DOUT

ICC1, ICC2

 

 

 

 

 

 

Write

L

L

X

DIN

ICC1, ICC2

 

 

 

 

 

 

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Parameter

Value

Unit

VTERM

Terminal Voltage with Respect to GND

–0.5 to +7.0

V

 

 

 

 

TBIAS

Temperature Under Bias

–55 to +125

°C

 

 

 

 

TSTG

Storage Temperature

–65 to +150

°C

 

 

 

 

PD

Power Dissipation

1.5

W

 

 

 

 

IOUT

DC Output Current (LOW)

20

mA

 

 

 

 

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Integrated Circuit Solution Inc.

3

AHSR010-0D 4/19/2002

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