Icom IC-V8 Service Manual

VHF TRANSCEIVER

iC-v8

INTRODUCTION

This service manual describes the latest service information for the

IC-V8 at the time of publication.

To upgrade quality, all electrical or mechanical parts and internal circuits are subject to change without notice or obligation.

DANGER

NEVER connect the transceiver to an AC outlet or to a DC

power supply that uses more than 10.3 V. Such a connection could cause a fire hazard and/or electric shock.

DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when con-

necting the transceiver. DO NOT apply an RF signal of more than 20 dBm (100mW)

to the antenna connector. This could damage the transceiver’s front end.

ORDERING PARTS

Be sure to include the following four points when ordering replacement parts:

1. 10-digit order numbers

2. Component part number and name

3. Equipment model name and unit name

4. Quantity required <SAMPLE ORDER>

0910053802 PCB B-5649B IC-V8 MAIN UNIT 1 pieces 8810009560 Screw BT M2 x 6 ZK IC-V8 Chassis 10 pieces 8810009510 Screw BT 2 x 4 NI IC-V8 Chassis 10 pieces

Addresses are provided on the inside back cover for your convenience.

REPAIR NOTES

1. Make sure a problem is internal before disassembling the transceiver.

2. DO NOT open the transceiver until the transceiver is disconnected from its power source.

3. DO NOT force any of the variable components. Turn them slowly and smoothly.

4. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.

5. DO NOT keep power ON for a long time when the transceiver is defective.

6. DO NOT transmit power into a signal generator or a sweep generator.

7. ALWAYS connect a 40 dB to 50 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.

8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

SECTION 1 SPECIFICATIONS

SECTION 2 INSIDE VIEWS

SECTION 3 DISASSEMBLY INSTRUCTIONS

SECTION 4 CIRCUIT DESCRIPTION

4 - 1 RECEIVER CIRCUITS ................................................................................................... 4 - 1

4 - 2 TRANSMITTER CIRCUITS ............................................................................................ 4 - 2

4 - 3 PLL CIRCUIT................................................................................................................... 4 - 3

4 - 4 OTHER CIRCUITS .......................................................................................................... 4 - 3

4 - 5 POWER SUPPLY CIRCUITS ......................................................................................... 4 - 3

4 - 6 CPU PORT ALLOCATIONS ........................................................................................... 4 - 4

SECTION 5 ADJUSTMENT PROCEDURES

5 - 1 PREPARATION................................................................................................................ 5 - 1

5 - 2 PLL ADJUSTMENT.......................................................................................................... 5 - 2

SECTION 6 PARTS LIST

SECTION 7 MECHANICAL PARTS AND DISASSEMBLY

SECTION 8 SEMI-CONDUCTOR INFORMATION

SECTION 9 BOARD LAYOUTS

9 - 1 MAIN UNIT....................................................................................................................... 9 - 1

SECTION 10 BC-146 OPTIONAL DESKTOP CHARGER INFORMATION

10 - 1 PARTS LIST................................................................................................................... 10 - 1

10 - 2 DISASSEMBLY INFORMATION.................................................................................... 10 - 1

10 - 3 VOLTAGE DIAGRAM..................................................................................................... 10 - 2

10 - 4 BOARD LAYOUT........................................................................................................... 10 - 2

SECTION 11 BLOCK DIAGRAM

SECTION 12 VOLTAGE DIAGRAM

SECTION 1 SPECIFICATIONS

1 - 1

‘‘

GENERAL

• Frequency coverage :

*Specifications Guaranteed: 144–148 MHz only

• Type of emission : F2D/ F3E

• Frequency stability : ± 10 ppm (–10˚C to +60˚C; +14˚F to +140˚F)

• Tuning steps : 5, 10, 12.5, 15, 20, 25, 30 or 50 kHz

• Antnna connector : BNC (50 Ω)

• Power supply requirement : 7.2 V DC (Operable voltage range: 6.0 to 10.3 V) (negative ground)

• Number of memory channel : 100 channels

• Call channel : 1 channel

• Scanning mode : Program, Memory, Skip, Priority or Tone

• Current drain (approx.) : Transmit at High (5.5 W) 2.0 A

at Low (0.5 W) 0.7 A

Receive Max. audio 250 mA

stand-by 70 mA power saved 20 mA

• Usable temperature range : –10˚C to +60˚C; +14˚F to +140˚F

• Dimensions (projections not included) : 54(W)

× 132(H) × 35(D) mm; 2 1⁄8(W) × 5 3⁄16(H) × 1 3⁄8(D) in.

• Weight (with ant., BP-222) : 350 g; 12.3 oz.

‘‘

TRANSMITTER

• RF output power (at 7.2 V DC) : 5.5 W / 0.5 W (High / Low) (with supplied battery pack)

• Modulation system : Variable reactance frequency modulation

• Maximum frequency deviation : ±5.0 kHz

• Spurious emissions : Less than –60 dB

• Ext. microphone connector : 3-conductor 2.5(d) mm (1⁄10”)/2.2 kΩ

‘‘

RECEIVER

• Receive system : Double conversion superheterodyne system

• Intermediate frequencies : 1st 21.7 MHz

2nd 450 kHz

• Sensitivity : 0.16 µV at 12 dB SINAD (typical)

• Squelch sensitivity : 0.1 µV at threshold (typical)

• Adjacent channel selectivity : 65 dB (typical)

• Spurious response rejection : 75 dB (typical)

• Intermodulation rejection ratio : 65 dB (typical)

• Audio output power (at 7.2 V DC) : More than 300 mW at 10% distortion with an 8 Ω load

• Ext. speaker connector : 3-conductor 3.5(d) mm (

⁄8”)/8 Ω

All stated specifications are subject to change without notice or obligation.

Receive

136.000–174.000 MHz*

Transmit

144.000–148.000 MHz

136.000–174.000 MHz*

Version

[USA] [GEN]

2- 1

SECTION 2 INSIDE VIEWS

TOP VIEW BOTT OM VIEW

Antenna swtching circuit (D2, D8: MA77)

Power amplifier (Q1: 2SK3476)

APC IC3A: NJM12902V

( )

Q37: DTA144EU FM IF IC

(IC2: TA31136FN)

IF amplifier (Q14: 2SC4406)

PLL IC (IC1: LV2105V)

TX/RX switch (D3, D4: MA77)

Antenna swtching circuit (D1: MA77)

RF amplifier (Q12: 3SK274)

1st mixer (Q13: 3SK274)

Crystal filter FI1, Fl3:FL-298

( )

PLL reference oscillator (X1: CR-659 21.25 MHz)

VCO circuit

D/A converter (IC10: M62363FP)

EEPROM (IC7: BR24C16FV)

21.700 MHz

CPU (IC8: HD6473877H)

3- 1

SECTION 3 DISASSEMBLY INSTRUCTIONS

3-1 DISASSEMBLY INSTRUCTION

• REMOVING THE CHASSIS PANEL

1 Unscrew 1 nut A, and remove 1 knob B. 2 Unscrew 2 screws C. 3 Take off the chassis in the direction of the arrow. 4 Unplug J6 to separate front panel and chassis.

• REMOVING THE MAIN UNIT

1 2

Unsolder 3 points D, and unscrew 1 nut E.

Unscrew 2 screws F, 2 screws H, and 6 screws G (silver, 2 mm) to separate the chassis and the MAIN unit.

(black, 2 mm) x 2

Front panel

Chassis

J6 (Speaker connector)

(black, 2 mm) x 2

(silver, 2 mm) x 6

Shield cover

Guide holes

MAIN unit

Chassis

(black, 2 mm) x 2

Take off the MAIN unit in the direction of the arrow.

3 - 2

3-2 OPTIONAL UNIT INSTALLATIONS

1 Remove the option cover. 2 Remove the bottom protective paper of spoge. 3 Connect the UT-108 optional unit to J5. 4 Replace the option cover to the chassis-hole.

Option cover

Option unit

SPONGE Parts name : 1556 sponge Order No. : 8930013545

SECTION 4 CIRCUIT DESCRIPTION

4 - 1

4-1 RECEIVER CIRCUITS

4-1-1 ANTENNA SWITCHING CIRCUIT

Received signals passed through the low-pass filter (L1, L2, C1–C5). The filtered signals are applied to the 1/4

λ type

antenna switching circuit (D1, D2, D8, L15, C76). The antenna swtiching circuit functions as a low-pass filter

while transmitting. However, its impedance becomes very high while D2 and D8 are turn ON. Thus transmit signals are blocked from entering the receiver circuits. The antenna switching circuit employs a 1/4

λ type diode swtiching system. The passed signals are then applied to the RF amplifier circuit.

4-1-2 RF CIRCUIT

The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.

The signals from the antenna switching circuit are applied to the limitter (D50), and are then passed through the bandpass filter (D9, L16, C80). The filtered signals are amplified at the RF amplifier (Q12), then applied to the 1st mixer circuit after out-of-band signals are suppressed at the bandpass filter (D11, D12, L19, C91–C97).

D9, D11, D12 employ varactor diodes that track the bandpass filters and are controlled by the T1–T3 signals from the D/A convertor (IC10, pins 2, 3, 10). These diodes tune the center frequency of an RF passband for wide bandwidth receiving and good image response rejection.

4-1-3 1ST MIXER AND 1ST IF CIRCUITS

The 1st mixer circuit converts the received signal to a fixed frequency of the 1st IF signal with a PLL output frequency. By changing the PLL frequency, only the desired frequency will pass through two crystal filters at the next stage of the 1st mixer.

The signals from the RF circuit are mixed at the 1st mixer (Q13) with a 1st LO signal coming from the VCO circuit to produce a 21.70 MHz 1st IF signal.

The 1st IF signal is applied to two crystal filters (FI1 and FI3) to suppress out-of-band signals. The filtered 1st IF signal is applied to the IF amplifier (Q14), then applied to the 2nd mixer circuit (IC1, pin 16).

4-1-4 2ND IF AND DEMODULATOR CIRCUITS

The 2nd mixer circuit converts the 1st IF signal to a 2nd IF signal. Adouble conversion superheterodyne system (which converts receive signal twice) improves the image rejection ratio and obtain stable receiver gain.

The 1st IF signal from the IF amplifier is applied to the 2nd mixer section of the FM IF IC (IC2, pin 16), and is mixed with the 2nd LO signal to be converted to a 450 kHz 2nd IF signal.

The FM IF IC contains the 2nd mixer, limiter amplifier, quadrature detector and active filter circuits. A21.25 MHz 2nd LO signal is produced at the PLL circuit.

The 2nd IF signal from the 2nd mixer (IC2, pin 3) passes through a ceramic filter (FI2) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier (IC2, pin 5) and applied to the quadrature detector (IC2, pins 10, 11) to demodulate the 2nd IF signal into AF signals.

4-1-5 AF CIRCUIT

The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker.

AF signals from the FM IF IC (IC2, pin 9) are applied to the analog swtich (IC4, pin 1) via the AF filter circuit (IC3b, pins 6, 7). The output signals from pin 2, 3 are passed through the low-pass filter (IC3d, pins 13, 14), and are then applied to the analog swtich (IC4, pin 9, 10) again. The signals from the IC4, pin 11 are applied to the AF power amplifier (IC5, pin 4) after passing through the D/A convertor (IC10, pins 12, 11).

Mixer

Limiter amp.

2nd IF filter 450 kHz

PLL IC

IC1

21.25 MHz

IC2 TA31136F

1st IF from the IF amplifier (Q14)

"SD" signal to the CPU pin 98

11109

87 5 3

AF signal "DET"

R86

C122

C121

R88R87

R83

"SQLIN" signal from the D/A convertor (IC10, pin 23)

R82

C112 C113

C116

16 1

Active filter

FI2

Noise

detector

"NOIS" signal to the CPU pin 19

RSSI

Noise comp.

R84

LPF

• 2ND IF AND DEMODULATOR CIRCUITS

4 - 2

The AF signals are applied to the AF power amplifier circuit (IC5, pin 4) to obtain the specified audio level. The amplified AF signals, output from pin 10, are applied to the internal speaker (SP1) via the speaker jack (CHASSIS unit; J3) when no plug is connected to the jack.

4-1-6 SQUELCH CIRCUIT

Asquelch circuit cuts out AF signals when no RF signals are received. By detecting noise components in the AF signals, the squelch switches the analog swtich.

Aportion of the AF signals from the FM IF IC (IC2, pin 9) are applied to the active filter section (IC2, pin 8) where noise components are amplified and detected with an internal noise detector.

The trigger circuit converts the detected signals to a HIGH or LOW signal and applies this (from pin 13) to the CPU (IC8, pin 19) as the NOIS signal. When the CPU receives a HIGH level NOIS signal, the CPU controls the RMUT line to cut the AF signals at the analog swtich IC (IC4). At the same time, the AFON line controls the AF regulator circuit (Q15, Q16) to cut out the VCC power source for the AF power amplifier (IC5).

4-2 TRANSMITTER CIRCUITS

4-2-1 MICROPHONE AMPLIFIER CIRCUIT

The microphone amplifier circuit amplifies audio signals with +6 dB/octave pre-emphasis from the microphone to a level needed for the modulation circuit.

The AF signals from the microphone are applied to the microphone amplifier circuit (IC3c, pin 10). The amplified AF signals are passed through the low-pass filter circuit (IC3d, pins 13, 14) via the analog swtich (IC4, pins 4, 3). The filtered AF signals are applied to the modulator circuit after passing through the analog swtich (IC4, pins 8, 9).

4-2-2 MODULATION CIRCUIT

The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone audio signals.

The audio signals (SHIFT) change the reactance of D37 to modulate an oscillated signal at the VCO (Q50, D38). The oscillated signal is amplified at the LO (Q6) and buffer (Q4) amplifiers, then applied to the TX/RX switch circuit (D3, D4).

4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS

The signal from the VCO circuit passes through the TX/RX swtiching circuit (D3) and is amplified at the pre-drive (Q3), drive (Q2) and power (Q1) amplifiers to obtain 5.5 W of RF power (at 7.2 V DC/typical). The amplified signal passes through the low-pass filter (L4, C278, C287), and then applied to the antenna swtiching circuit (D1). The signal is applied to the antenna connector (J1) after being passed through the low-pass filter (L1, L2, C1–C5).

The bias current of the drive (Q2) and power (Q1) amplifiers is controlled by the APC circuit to stabilize the output power.

4-2-4 APC CIRCUIT

The APC (Automatic Power Control) circuit (IC3a, Q37) protects drive and power amplifiers from excessive currents and selects HIGH or LOW output power.

The output voltage from the power detector circuit (D32, D33) is applied to the differential amplifier (IC3a, pin 2), and the “T3” signal from the D/A convertor (IC10, pin 10) is applied to the other input for reference.

When the driving current increases, the input voltage of the differential amplifier (IC3a, pin 2) will be increased. In such cases, the differential amplifier output voltage (pin 1) is decreased to reduce the drive current.

Q37 is controlled by the TXC signal from the CPU (IC8, pin

55) to select HIGH or LOW output power.

Q1 Power amp.

Q2 Driver amp.

IC3a

VCC

Q3 Pre drive

RF signal from PLL IC (IC1)

to antenna

TXC

Q37

PS5

APC control circuit

Power detector circuit (D32, D33)

D33 D32

L4, C278, C287

LPF

• APC CIRCUIT

4 - 3

4-3 PLL CIRCUITS

A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by the divided ratio (N-data) of a programmable divider.

The PLL circuit contains the VCO circuit (Q50, D38). The oscillated signal is amplified at the LO (Q6) and buffer (Q5) amplifiers and then applied to the PLL IC (IC1, pin 6).

The PLL IC contains a prescaler, programmable counter, programmable divider, phase detector, charge pump, etc. The entered signal is divided at the prescaler and programmable counter section by the N-data ratio from the CPU. The divided signal is detected on phase at the phase detector using the reference frequency.

If the oscillated signal drifts, its phase changes from the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency.

A portion of the VCO circuit is amplified at the LO (Q6) and buffer (Q4) amplifiers and is then applied to the receive 1st mixer or transmit pre-drive amplifier circuit via the TX/RX swtiching diode (D3, D4).

4-4 OTHER CIRCUITS

4-4-1 TONE SQUELCH CIRCUIT

A portion of the detected audio signals from the “DET” line are passed through the tone filter (Q53). The filtered signal is then applied to the CPU (IC1, pin 94) via the “CTCIN” signal, and is compared with the programmed tone signal. The CPU (IC1) outputs control signals as “CTCC” signal to the AF mute and AF regulator circuits to open the squelch when a matched tone signal is received.

The programmed subaudible tone signal is output from the CPU (IC1, pin 91) directly when transmitting with a tone.

Shift register

Prescaler

Phase detector

Loop

filter

Programmable counter

Programmable divider

21.25 MHz

21.25 MHz signal to the FM IF IC

"DEV" signal from the D/A convertor (IC10, pin 22) when transmitting

Q50, D38

VCO circuit

LO amp.

Buffer

2 3 4

PLCK SO PLST

to transmitter circuit to 1st mixer circuit

Q6 Q4

IC1 LV2105V

VCO SHIFT

Q51, D37

• PLL CIRCUIT

LINE

VCC

CPU5

SW5V

VCO5

PS5

DESCRIPTION

The voltage from the attached battery pack. Common 5 V converted from the VCC line by the

CPU5 regulator (IC12). The output voltage is applied to the CPU (IC8), EEPROM (IC7) and reset IC (IC11).

Common 5 V converted from the VCC line by the SW5 regulator circuit (Q55, Q57, D39). The output voltage is applied to the T5, R5, PS5 and VCO5 regulator circuits, D/Aconvertor (IC10, pin

16), etc. Common 5 V converted from the SW5V line by

the VCO5 regulator circuit (Q11) using the LO (Q6) and buffer (Q4, Q5) amplifiers. The VCO5 regulator circuit is controlled by the PSVCO line from the CPU (IC8, pin 62).

Common 5 V converted from the SW5V line by the PS5 regulator circuit (Q54) using the analog switch (IC14, pin 14) and APC controller (Q37). The PS5 regulator circuit is controlled by the PS5C line from the CPU (IC8, pin 63).

5 V for receiver circuits converted from the SW5V line by the R5 regulator circuit (Q21) using the 2nd IF IC (IC2, pin 4), RF (Q12) and IF (Q14) amplifiers, etc. The R5 regulator circuit is controlled by the R5C line from the CPU (IC8, pin 53).

5 V for the transmitter circuit converted from the SW5V line by the T5 regulator circuit (Q22) using the pre-drive amplifier (Q3). The T5 regulator circuit is controlled by the T5C line from the CPU (IC8, pin 54).

4-5 POWER SUPPLY CIRCUITS

VOLTAGE LINE

+ 21 hidden pages

Icom IC-V8 Service Manual

INTRODUCTION

TABLE OF CONTENTS

SECTION 1 SPECIFICATIONS

SECTION 2 INSIDE VIEWS

SECTION 3 DISASSEMBLY INSTRUCTIONS

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS

4-2 TRANSMITTER CIRCUITS

4-3 PLL CIRCUITS

4-4 OTHER CIRCUITS